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a10gx- xilinx/altera sync-up

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Rejeesh Kutty 2017-01-30 09:59:01 -05:00
parent b14e7fe4ee
commit 97d72d2f65
1 changed files with 7 additions and 5 deletions
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12
projects/daq3/a10gx/system_top.v
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@ -209,12 +209,14 @@ module system_top (
// gpio in & out are separate cores // gpio in & out are separate cores
assign sysref = gpio_o[43]; assign gpio_i[63:40] = gpio_o[63:40];
assign adc_pd = gpio_o[42]; assign sysref = gpio_o[40];
assign dac_txen = gpio_o[41]; assign gpio_i[39:39] = trig;
assign gpio_i[38:37] = gpio_o[38:37];
assign adc_pd = gpio_o[38];
assign dac_txen = gpio_o[37];
assign gpio_i[63:38] = gpio_o[63:38];
assign gpio_i[37:37] = trig;
assign gpio_i[36:36] = adc_fdb; assign gpio_i[36:36] = adc_fdb;
assign gpio_i[35:35] = adc_fda; assign gpio_i[35:35] = adc_fda;
assign gpio_i[34:34] = dac_irq; assign gpio_i[34:34] = dac_irq;