pzsdr/ccpci- initial version
Rejeesh Kutty
parent
14bccb6062
commit
9832ea95a8
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@ -1,107 +1,27 @@
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# constraints
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_p] ; ## IO_L13P_T2_MRCC_12
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_n] ; ## IO_L13N_T2_MRCC_12
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set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_p] ; ## IO_L13P_T2_MRCC_13
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_n] ; ## IO_L13N_T2_MRCC_13
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports fmc_prstn] ; ## IO_25_13
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set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[0]] ; ## IO_L12P_T1_MRCC_12
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[0]] ; ## IO_L12N_T1_MRCC_12
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[1]] ; ## IO_L11P_T1_SRCC_12
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set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[1]] ; ## IO_L11N_T1_SRCC_12
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[2]] ; ## IO_L1P_T0_12
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set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[2]] ; ## IO_L1N_T0_12
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[3]] ; ## IO_L2P_T0_12
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set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[3]] ; ## IO_L2N_T0_12
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[4]] ; ## IO_L3P_T0_DQS_12
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set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[4]] ; ## IO_L3N_T0_DQS_12
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set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[5]] ; ## IO_L4P_T0_12
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set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[5]] ; ## IO_L4N_T0_12
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set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[6]] ; ## IO_L5P_T0_12
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set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[6]] ; ## IO_L5N_T0_12
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set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[7]] ; ## IO_L6P_T0_12
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[7]] ; ## IO_L6N_T0_VREF_12
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set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[8]] ; ## IO_L7P_T1_12
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set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[8]] ; ## IO_L7N_T1_12
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[9]] ; ## IO_L8P_T1_12
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[9]] ; ## IO_L8N_T1_12
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set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[10]] ; ## IO_L9P_T1_DQS_12
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set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[10]] ; ## IO_L9N_T1_DQS_12
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[11]] ; ## IO_L10P_T1_12
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[11]] ; ## IO_L10N_T1_12
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[12]] ; ## IO_L14P_T2_SRCC_12
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set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[12]] ; ## IO_L14N_T2_SRCC_12
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set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[13]] ; ## IO_L15P_T2_DQS_12
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set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[13]] ; ## IO_L15N_T2_DQS_12
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[14]] ; ## IO_L16P_T2_12
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set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[14]] ; ## IO_L16N_T2_12
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[15]] ; ## IO_L17P_T2_12
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set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[15]] ; ## IO_L17N_T2_12
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[16]] ; ## IO_L18P_T2_12
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set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[16]] ; ## IO_L18N_T2_12
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set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[17]] ; ## IO_L12P_T1_MRCC_13
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set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[17]] ; ## IO_L12N_T1_MRCC_13
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set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[18]] ; ## IO_L11P_T1_SRCC_13
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set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[18]] ; ## IO_L11N_T1_SRCC_13
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set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[19]] ; ## IO_L1P_T0_13
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set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[19]] ; ## IO_L1N_T0_13
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set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[20]] ; ## IO_L2P_T0_13
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set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[20]] ; ## IO_L2N_T0_13
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set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[21]] ; ## IO_L3P_T0_DQS_13
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set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[21]] ; ## IO_L3N_T0_DQS_13
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[22]] ; ## IO_L4P_T0_13
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set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[22]] ; ## IO_L4N_T0_13
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set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[23]] ; ## IO_L6P_T0_13
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set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[23]] ; ## IO_L6N_T0_VREF_13
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set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[24]] ; ## IO_L7P_T1_13
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set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[24]] ; ## IO_L7N_T1_13
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set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[25]] ; ## IO_L8P_T1_13
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set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[25]] ; ## IO_L8N_T1_13
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set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[26]] ; ## IO_L9P_T1_DQS_13
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set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[26]] ; ## IO_L9N_T1_DQS_13
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set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[27]] ; ## IO_L10P_T1_13
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set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[27]] ; ## IO_L10N_T1_13
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set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[28]] ; ## IO_L14P_T2_SRCC_13
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set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[28]] ; ## IO_L14N_T2_SRCC_13
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set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[29]] ; ## IO_L15P_T2_DQS_13
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[29]] ; ## IO_L15N_T2_DQS_13
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set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[30]] ; ## IO_L16P_T2_13
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set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[30]] ; ## IO_L16N_T2_13
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set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[31]] ; ## IO_L17P_T2_13
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set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[31]] ; ## IO_L17N_T2_13
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set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[32]] ; ## IO_L18P_T2_13
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set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[32]] ; ## IO_L18N_T2_13
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set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[33]] ; ## IO_L19P_T3_13
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[33]] ; ## IO_L19N_T3_VREF_13
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set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pmod0[0]] ; ## IO_L21P_T3_DQS_13
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pmod0[1]] ; ## IO_L21N_T3_DQS_13
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports pmod0[2]] ; ## IO_L22P_T3_13
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports pmod0[3]] ; ## IO_L22N_T3_13
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports pmod0[4]] ; ## IO_L23P_T3_13
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports pmod0[5]] ; ## IO_L23N_T3_13
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports pmod0[6]] ; ## IO_L24P_T3_13
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set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports pmod0[7]] ; ## IO_L24N_T3_13
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports pmod1[0]] ; ## IO_L19P_T3_34
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports pmod1[1]] ; ## IO_L19N_T3_VREF_34
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports pmod1[2]] ; ## IO_L20P_T3_34
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmod1[3]] ; ## IO_L20N_T3_34
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports pmod1[4]] ; ## IO_L21P_T3_DQS_34
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports pmod1[5]] ; ## IO_L21N_T3_DQS_34
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports pmod1[6]] ; ## IO_L22P_T3_34
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set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports pmod1[7]] ; ## IO_L22N_T3_34
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set_property -dict {PACKAGE_PIN W6} [get_ports fmc_gt_ref_clk_p] ; ## MGTREFCLK0P_111
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set_property -dict {PACKAGE_PIN W5} [get_ports fmc_gt_ref_clk_n] ; ## MGTREFCLK0N_111
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set_property -dict {PACKAGE_PIN AF8} [get_ports fmc_gt_tx_p] ; ## MGTXTXP0_111
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set_property -dict {PACKAGE_PIN AF7} [get_ports fmc_gt_tx_n] ; ## MGTXTXN0_111
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set_property -dict {PACKAGE_PIN AD8} [get_ports fmc_gt_rx_p] ; ## MGTXRXP0_111
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set_property -dict {PACKAGE_PIN AD7} [get_ports fmc_gt_rx_n] ; ## MGTXRXN0_111
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# clocks
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create_clock -name ref_clk -period 4.00 [get_ports fmc_gt_ref_clk_p]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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set_property -dict {PACKAGE_PIN AA6} [get_ports pcie_ref_clk_p] ; ## MGTREFCLK1P_111
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set_property -dict {PACKAGE_PIN AA5} [get_ports pcie_ref_clk_n] ; ## MGTREFCLK1N_111
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set_property -dict {PACKAGE_PIN AD8} [get_ports pcie_data_rx_p[0]] ; ## MGTXRXP0_111
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set_property -dict {PACKAGE_PIN AD7} [get_ports pcie_data_rx_n[0]] ; ## MGTXRXN0_111
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set_property -dict {PACKAGE_PIN AE6} [get_ports pcie_data_rx_p[1]] ; ## MGTXRXP1_111
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set_property -dict {PACKAGE_PIN AE5} [get_ports pcie_data_rx_n[1]] ; ## MGTXRXN1_111
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set_property -dict {PACKAGE_PIN AC6} [get_ports pcie_data_rx_p[2]] ; ## MGTXRXP2_111
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set_property -dict {PACKAGE_PIN AC5} [get_ports pcie_data_rx_n[2]] ; ## MGTXRXN2_111
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set_property -dict {PACKAGE_PIN AD4} [get_ports pcie_data_rx_p[3]] ; ## MGTXRXP3_111
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set_property -dict {PACKAGE_PIN AD3} [get_ports pcie_data_rx_n[3]] ; ## MGTXRXN3_111
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set_property -dict {PACKAGE_PIN AF8} [get_ports pcie_data_tx_p[0]] ; ## MGTXTXP0_111
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set_property -dict {PACKAGE_PIN AF7} [get_ports pcie_data_tx_n[0]] ; ## MGTXTXN0_111
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set_property -dict {PACKAGE_PIN AF4} [get_ports pcie_data_tx_p[1]] ; ## MGTXTXP1_111
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set_property -dict {PACKAGE_PIN AF3} [get_ports pcie_data_tx_n[1]] ; ## MGTXTXN1_111
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set_property -dict {PACKAGE_PIN AE2} [get_ports pcie_data_tx_p[2]] ; ## MGTXTXP2_111
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set_property -dict {PACKAGE_PIN AE1} [get_ports pcie_data_tx_n[2]] ; ## MGTXTXN2_111
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set_property -dict {PACKAGE_PIN AC2} [get_ports pcie_data_tx_p[3]] ; ## MGTXTXP3_111
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set_property -dict {PACKAGE_PIN AC1} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN3_111
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set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pcie_rstn] ; ## IO_L19P_T3_13
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports pcie_prsntn] ; ## IO_L19N_T3_VREF_13
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set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pcie_prsnt1n] ; ## IO_L21P_T3_DQS_13
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pcie_prsnt4n] ; ## IO_L21N_T3_DQS_13
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports pcie_waken] ; ## IO_L20N_T3_13
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@ -83,11 +83,6 @@ module system_top (
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enable,
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txnrx,
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gpio_rf0,
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gpio_rf1,
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gpio_rf2,
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gpio_rf3,
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gpio_rfpwr_enable,
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gpio_clksel,
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gpio_resetb,
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gpio_sync,
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@ -100,22 +95,17 @@ module system_top (
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spi_mosi,
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spi_miso,
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fmc_prstn,
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fmc_clk0_p,
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fmc_clk0_n,
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fmc_clk1_p,
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fmc_clk1_n,
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fmc_la_p,
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fmc_la_n,
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pmod0,
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pmod1,
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fmc_gt_ref_clk_p,
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fmc_gt_ref_clk_n,
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fmc_gt_tx_p,
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fmc_gt_tx_n,
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fmc_gt_rx_p,
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fmc_gt_rx_n);
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pcie_rstn,
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pcie_prsntn,
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pcie_prsnt1n,
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pcie_prsnt4n,
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pcie_waken,
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pcie_ref_clk_p,
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pcie_ref_clk_n,
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pcie_data_rx_p,
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pcie_data_rx_n,
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pcie_data_tx_p,
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pcie_data_tx_n);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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@ -161,11 +151,6 @@ module system_top (
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output enable;
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output txnrx;
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inout gpio_rf0;
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inout gpio_rf1;
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inout gpio_rf2;
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inout gpio_rf3;
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inout gpio_rfpwr_enable;
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inout gpio_clksel;
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inout gpio_resetb;
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inout gpio_sync;
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@ -178,142 +163,45 @@ module system_top (
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output spi_mosi;
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input spi_miso;
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input fmc_prstn;
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input fmc_clk0_p;
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input fmc_clk0_n;
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input fmc_clk1_p;
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input fmc_clk1_n;
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inout [33:0] fmc_la_p;
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inout [33:0] fmc_la_n;
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inout [ 7:0] pmod0;
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inout [ 7:0] pmod1;
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input fmc_gt_ref_clk_p;
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input fmc_gt_ref_clk_n;
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output fmc_gt_tx_p;
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output fmc_gt_tx_n;
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input fmc_gt_rx_p;
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input fmc_gt_rx_n;
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input pcie_rstn;
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input pcie_prsntn;
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output pcie_prsnt1n;
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output pcie_prsnt4n;
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inout pcie_waken;
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input pcie_ref_clk_p;
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input pcie_ref_clk_n;
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input [ 3:0] pcie_data_rx_p;
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input [ 3:0] pcie_data_rx_n;
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||||
output [ 3:0] pcie_data_tx_p;
|
||||
output [ 3:0] pcie_data_tx_n;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire fmc_clk0_s;
|
||||
wire fmc_clk0;
|
||||
wire [31:0] up_clk0_count;
|
||||
wire fmc_clk1_s;
|
||||
wire fmc_clk1;
|
||||
wire [31:0] up_clk1_count;
|
||||
wire fmc_gt_ref_clk;
|
||||
wire [31:0] gpio_0_0_i;
|
||||
wire [31:0] gpio_0_0_o;
|
||||
wire [31:0] gpio_0_0_t;
|
||||
wire [31:0] gpio_0_1_i;
|
||||
wire [31:0] gpio_0_1_o;
|
||||
wire [31:0] gpio_0_1_t;
|
||||
wire [31:0] gpio_1_0_i;
|
||||
wire [31:0] gpio_1_0_o;
|
||||
wire [31:0] gpio_1_0_t;
|
||||
wire [31:0] gpio_1_1_i;
|
||||
wire [31:0] gpio_1_1_o;
|
||||
wire [31:0] gpio_1_1_t;
|
||||
wire [31:0] gpio_3_1_o;
|
||||
wire pcie_ref_clk;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire up_clk;
|
||||
wire up_rst;
|
||||
wire up_rstn;
|
||||
wire up_pn_err_clr;
|
||||
wire up_pn_oos_clr;
|
||||
wire up_pn_err;
|
||||
wire up_pn_oos;
|
||||
|
||||
// assignments
|
||||
|
||||
assign pcie_waken = 1'bz;
|
||||
assign pcie_prsnt1n = 1'b1;
|
||||
assign pcie_prsnt4n = pcie_prsntn;
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS i_ibufds_clk0 (
|
||||
.I (fmc_clk0_p),
|
||||
.IB (fmc_clk0_n),
|
||||
.O (fmc_clk0_s));
|
||||
|
||||
BUFG i_bufg_clk0 (
|
||||
.I (fmc_clk0_s),
|
||||
.O (fmc_clk0));
|
||||
|
||||
up_clock_mon i_clk0_mon (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_d_count (up_clk0_count),
|
||||
.d_rst (up_rst),
|
||||
.d_clk (fmc_clk0));
|
||||
|
||||
IBUFDS i_ibufds_clk1 (
|
||||
.I (fmc_clk1_p),
|
||||
.IB (fmc_clk1_n),
|
||||
.O (fmc_clk1_s));
|
||||
|
||||
BUFG i_bufg_clk1 (
|
||||
.I (fmc_clk1_s),
|
||||
.O (fmc_clk1));
|
||||
|
||||
up_clock_mon i_clk1_mon (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_d_count (up_clk1_count),
|
||||
.d_rst (up_rst),
|
||||
.d_clk (fmc_clk1));
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_ref_clk (
|
||||
IBUFDS_GTE2 i_ibufds_pcie_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (fmc_gt_ref_clk_p),
|
||||
.IB (fmc_gt_ref_clk_n),
|
||||
.O (fmc_gt_ref_clk),
|
||||
.I (pcie_ref_clk_p),
|
||||
.IB (pcie_ref_clk_n),
|
||||
.O (pcie_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
assign gpio_0_1_i[31:10] = 'd0;
|
||||
assign gpio_1_1_i[31:10] = 'd0;
|
||||
assign up_pn_err_clr = gpio_3_1_o[1];
|
||||
assign up_pn_oos_clr = gpio_3_1_o[0];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod0_fmc_p (
|
||||
.dio_t ({gpio_0_1_t[9:0], gpio_0_0_t[31:0]}),
|
||||
.dio_i ({gpio_0_1_o[9:0], gpio_0_0_o[31:0]}),
|
||||
.dio_o ({gpio_0_1_i[9:0], gpio_0_0_i[31:0]}),
|
||||
.dio_p ({ pmod1[3],
|
||||
pmod1[2],
|
||||
pmod1[1],
|
||||
pmod1[0],
|
||||
pmod0[3],
|
||||
pmod0[2],
|
||||
pmod0[1],
|
||||
pmod0[0],
|
||||
fmc_la_n[16:0],
|
||||
fmc_la_p[16:0]}));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod1_fmc_n (
|
||||
.dio_t ({gpio_1_1_t[9:0], gpio_1_0_t[31:0]}),
|
||||
.dio_i ({gpio_1_1_o[9:0], gpio_1_0_o[31:0]}),
|
||||
.dio_o ({gpio_1_1_i[9:0], gpio_1_0_i[31:0]}),
|
||||
.dio_p ({ pmod1[7],
|
||||
pmod1[6],
|
||||
pmod1[5],
|
||||
pmod1[4],
|
||||
pmod0[7],
|
||||
pmod0[6],
|
||||
pmod0[5],
|
||||
pmod0[4],
|
||||
fmc_la_n[33:17],
|
||||
fmc_la_p[33:17]}));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf (
|
||||
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
|
||||
.dio_t ({gpio_t[56:51], gpio_t[46:32]}),
|
||||
.dio_i ({gpio_o[56:51], gpio_o[46:32]}),
|
||||
.dio_o ({gpio_i[56:51], gpio_i[46:32]}),
|
||||
.dio_p ({ gpio_rf0, // 56:56
|
||||
gpio_rf1, // 55:55
|
||||
gpio_rf2, // 54:54
|
||||
gpio_rf3, // 53:53
|
||||
gpio_rfpwr_enable, // 52:52
|
||||
gpio_clksel, // 51:51
|
||||
.dio_p ({ gpio_clksel, // 51:51
|
||||
gpio_resetb, // 46:46
|
||||
gpio_sync, // 45:45
|
||||
gpio_en_agc, // 44:44
|
||||
|
|
@ -349,42 +237,18 @@ module system_top (
|
|||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.fmc_gt_ref_clk0 (fmc_gt_ref_clk),
|
||||
.fmc_gt_ref_clk1 (fmc_gt_ref_clk),
|
||||
.fmc_gt_rx_n (fmc_gt_rx_n),
|
||||
.fmc_gt_rx_p (fmc_gt_rx_p),
|
||||
.fmc_gt_tx_n (fmc_gt_tx_n),
|
||||
.fmc_gt_tx_p (fmc_gt_tx_p),
|
||||
.gpio_0_0_i (gpio_0_0_i),
|
||||
.gpio_0_0_o (gpio_0_0_o),
|
||||
.gpio_0_0_t (gpio_0_0_t),
|
||||
.gpio_0_1_i (gpio_0_1_i),
|
||||
.gpio_0_1_o (gpio_0_1_o),
|
||||
.gpio_0_1_t (gpio_0_1_t),
|
||||
.gpio_1_0_i (gpio_1_0_i),
|
||||
.gpio_1_0_o (gpio_1_0_o),
|
||||
.gpio_1_0_t (gpio_1_0_t),
|
||||
.gpio_1_1_i (gpio_1_1_i),
|
||||
.gpio_1_1_o (gpio_1_1_o),
|
||||
.gpio_1_1_t (gpio_1_1_t),
|
||||
.gpio_2_0_i (up_clk0_count),
|
||||
.gpio_2_0_o (),
|
||||
.gpio_2_0_t (),
|
||||
.gpio_2_1_i (up_clk1_count),
|
||||
.gpio_2_1_o (),
|
||||
.gpio_2_1_t (),
|
||||
.gpio_3_0_i ({31'd0, fmc_prstn}),
|
||||
.gpio_3_0_o (),
|
||||
.gpio_3_0_t (),
|
||||
.gpio_3_1_i ({30'd0, up_pn_err, up_pn_oos}),
|
||||
.gpio_3_1_o (gpio_3_1_o),
|
||||
.gpio_3_1_t (),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.otg_vbusoc (1'b0),
|
||||
.pcie_data_rxn (pcie_data_rx_n),
|
||||
.pcie_data_rxp (pcie_data_rx_p),
|
||||
.pcie_data_txn (pcie_data_tx_n),
|
||||
.pcie_data_txp (pcie_data_tx_p),
|
||||
.pcie_ref_clk (pcie_ref_clk),
|
||||
.pcie_rstn (pcie_rstn),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
|
|
@ -432,14 +296,7 @@ module system_top (
|
|||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.txnrx (txnrx),
|
||||
.up_clk (up_clk),
|
||||
.up_enable (gpio_o[47]),
|
||||
.up_pn_err (up_pn_err),
|
||||
.up_pn_err_clr (up_pn_err_clr),
|
||||
.up_pn_oos (up_pn_oos),
|
||||
.up_pn_oos_clr (up_pn_oos_clr),
|
||||
.up_rst (up_rst),
|
||||
.up_rstn (up_rstn),
|
||||
.up_txnrx (gpio_o[48]));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -7,25 +7,28 @@ ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
|
|||
set axi_pcie_x4 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.6 axi_pcie_x4]
|
||||
set_property -dict [list CONFIG.NO_OF_LANES {X4}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.MAX_LINK_SPEED {5.0_GT/s}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.DEVICE_ID {0x7022}] $axi_pcie_x4
|
||||
|
||||
set axi_pcie_x4_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_x4_cpu_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_pcie_x4_cpu_interconnect
|
||||
set_property -dict [list CONFIG.VENDOR_ID {0x11D4}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.DEVICE_ID {0x9361}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.SUBSYSTEM_VENDOR_ID {0x11D4}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.SUBSYSTEM_ID {0x0405}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.ENABLE_CLASS_CODE {true}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.CLASS_CODE {0x0D1000}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.BAR0_SCALE {Gigabytes}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.BAR0_SIZE {2}] $axi_pcie_x4
|
||||
set_property -dict [list CONFIG.NUM_MSI_REQ {1}] $axi_pcie_x4
|
||||
|
||||
set axi_pcie_x4_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_pcie_x4_rstgen]
|
||||
|
||||
set axi_pcie_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_pcie_intc]
|
||||
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_pcie_intc
|
||||
|
||||
set pcie_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pcie_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {3}] $pcie_concat_intc
|
||||
|
||||
create_bd_port -dir I -type rst pcie_rstn
|
||||
create_bd_port -dir I -type clk pcie_ref_clk
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_data
|
||||
|
||||
set m_intc_index [get_property CONFIG.NUM_MI [get_bd_cells axi_cpu_interconnect]]
|
||||
set m_intc_str "M$m_intc_index"
|
||||
if {$m_intc_index < 10} {
|
||||
set m_intc_str "M0$m_intc_index"
|
||||
}
|
||||
set m_intc_index [expr $m_intc_index + 1]
|
||||
set_property CONFIG.NUM_MI $m_intc_index [get_bd_cells axi_cpu_interconnect]
|
||||
|
||||
ad_connect pcie_rstn axi_pcie_x4_rstgen/ext_reset_in
|
||||
ad_connect pcie_ref_clk axi_pcie_x4/REFCLK
|
||||
ad_connect pcie_data axi_pcie_x4/pcie_7x_mgt
|
||||
|
|
@ -35,78 +38,176 @@ ad_connect sys_cpu_resetn axi_pcie_x4_rstgen/aux_reset_in
|
|||
ad_connect axi_pcie_x4/mmcm_lock axi_pcie_x4_rstgen/dcm_locked
|
||||
ad_connect axi_pcie_x4/axi_ctl_aclk_out axi_pcie_x4_rstgen/slowest_sync_clk
|
||||
ad_connect pcie_axi_resetn axi_pcie_x4/axi_aresetn
|
||||
ad_connect axi_pcie_x4/axi_ctl_aclk_out axi_pcie_x4_cpu_interconnect/M00_ACLK
|
||||
ad_connect pcie_axi_resetn axi_pcie_x4_cpu_interconnect/M00_ARESETN
|
||||
ad_connect axi_pcie_x4_cpu_interconnect/M00_AXI axi_pcie_x4/S_AXI_CTL
|
||||
ad_connect sys_cpu_clk axi_pcie_x4_cpu_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_pcie_x4_cpu_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_cpu_interconnect/${m_intc_str}_ACLK
|
||||
ad_connect sys_cpu_resetn axi_pcie_x4_cpu_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_pcie_x4_cpu_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_cpu_interconnect/${m_intc_str}_ARESETN
|
||||
ad_connect axi_pcie_x4_cpu_interconnect/S00_AXI axi_cpu_interconnect/${m_intc_str}_AXI
|
||||
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp1_interconnect/S00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp2_interconnect/S00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp1_interconnect/M00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp2_interconnect/M00_AXI]]]
|
||||
# interrupts
|
||||
|
||||
ad_connect axi_pcie_intc/irq axi_pcie_x4/INTX_MSI_Request
|
||||
ad_connect pcie_concat_intc/dout axi_pcie_intc/intr
|
||||
ad_connect pcie_concat_intc/In0 axi_iic_main/iic2intc_irpt
|
||||
ad_connect pcie_concat_intc/In1 axi_ad9361_adc_dma/irq
|
||||
ad_connect pcie_concat_intc/In2 axi_ad9361_dac_dma/irq
|
||||
|
||||
# master split
|
||||
|
||||
set axi_pcie_m_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_m_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {1}] $axi_pcie_m_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {3}] $axi_pcie_m_interconnect
|
||||
|
||||
ad_connect pcie_axi_clk axi_pcie_m_interconnect/ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_m_interconnect/S00_ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_m_interconnect/M00_ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_m_interconnect/M01_ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_m_interconnect/M02_ACLK
|
||||
ad_connect pcie_axi_resetn axi_pcie_m_interconnect/ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_m_interconnect/S00_ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_m_interconnect/M00_ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_m_interconnect/M01_ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_m_interconnect/M02_ARESETN
|
||||
ad_connect axi_pcie_x4/M_AXI axi_pcie_m_interconnect/S00_AXI
|
||||
|
||||
# cpu interconnect
|
||||
|
||||
delete_bd_objs [get_bd_addr_segs sys_ps7/Data/SEG_axi_iic_main_Reg]
|
||||
delete_bd_objs [get_bd_addr_segs sys_ps7/Data/SEG_axi_ad9361_axi_lite]
|
||||
delete_bd_objs [get_bd_addr_segs sys_ps7/Data/SEG_axi_ad9361_dac_dma_axi_lite]
|
||||
delete_bd_objs [get_bd_addr_segs sys_ps7/Data/SEG_axi_ad9361_adc_dma_axi_lite]
|
||||
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_cpu_interconnect/M00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_cpu_interconnect/M01_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_cpu_interconnect/M02_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_cpu_interconnect/M03_AXI]]]
|
||||
|
||||
set_property CONFIG.NUM_MI 6 [get_bd_cells axi_cpu_interconnect]
|
||||
set_property CONFIG.NUM_SI 2 [get_bd_cells axi_cpu_interconnect]
|
||||
|
||||
ad_connect axi_pcie_x4/axi_ctl_aclk_out axi_cpu_interconnect/M04_ACLK
|
||||
ad_connect pcie_axi_resetn axi_cpu_interconnect/M04_ARESETN
|
||||
ad_connect pcie_axi_clk axi_cpu_interconnect/S01_ACLK
|
||||
ad_connect pcie_axi_resetn axi_cpu_interconnect/S01_ARESETN
|
||||
ad_connect axi_pcie_m_interconnect/M02_AXI axi_cpu_interconnect/S01_AXI
|
||||
ad_connect pcie_axi_clk axi_pcie_intc/s_axi_aclk
|
||||
ad_connect pcie_axi_resetn axi_pcie_intc/s_axi_aresetn
|
||||
ad_connect pcie_axi_clk axi_cpu_interconnect/M05_ACLK
|
||||
ad_connect pcie_axi_resetn axi_cpu_interconnect/M05_ARESETN
|
||||
ad_connect axi_cpu_interconnect/M00_AXI axi_iic_main/S_AXI
|
||||
ad_connect axi_cpu_interconnect/M01_AXI axi_ad9361/s_axi
|
||||
ad_connect axi_cpu_interconnect/M02_AXI axi_ad9361_dac_dma/s_axi
|
||||
ad_connect axi_cpu_interconnect/M03_AXI axi_ad9361_adc_dma/s_axi
|
||||
ad_connect axi_cpu_interconnect/M04_AXI axi_pcie_x4/S_AXI_CTL
|
||||
ad_connect axi_cpu_interconnect/M05_AXI axi_pcie_intc/s_axi
|
||||
|
||||
# remove hp1/hp2 interconnects (ipi error- same address on network)
|
||||
|
||||
delete_bd_objs [get_bd_addr_segs axi_ad9361_dac_dma/m_src_axi/SEG_sys_ps7_HP2_DDR_LOWOCM]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp1_interconnect/S00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp1_interconnect/M00_AXI]]]
|
||||
|
||||
delete_bd_objs [get_bd_addr_segs axi_ad9361_adc_dma/m_dest_axi/SEG_sys_ps7_HP1_DDR_LOWOCM]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp2_interconnect/S00_AXI]]]
|
||||
delete_bd_objs [get_bd_intf_nets -of_objects [find_bd_objs -relation connected_to [get_bd_intf_pins axi_hp2_interconnect/M00_AXI]]]
|
||||
|
||||
set axi_pcie_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {2}] $axi_pcie_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_pcie_interconnect
|
||||
# adc-dma split
|
||||
|
||||
ad_connect pcie_axi_clk axi_pcie_interconnect/ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_interconnect/M00_ACLK
|
||||
ad_connect pcie_axi_resetn axi_pcie_interconnect/ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_interconnect/M00_ARESETN
|
||||
ad_connect axi_pcie_interconnect/M00_AXI axi_pcie_x4/S_AXI
|
||||
set axi_adma_m_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_adma_m_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {1}] $axi_adma_m_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {2}] $axi_adma_m_interconnect
|
||||
|
||||
set axi_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_adc_dma_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {1}] $axi_adc_dma_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {2}] $axi_adc_dma_interconnect
|
||||
ad_connect sys_cpu_clk axi_adma_m_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_adma_m_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_adma_m_interconnect/M00_ACLK
|
||||
ad_connect sys_cpu_clk axi_adma_m_interconnect/M01_ACLK
|
||||
ad_connect sys_cpu_resetn axi_adma_m_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adma_m_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adma_m_interconnect/M00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adma_m_interconnect/M01_ARESETN
|
||||
ad_connect axi_ad9361_adc_dma/m_dest_axi axi_adma_m_interconnect/S00_AXI
|
||||
|
||||
ad_connect sys_cpu_clk axi_adc_dma_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_adc_dma_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_adc_dma_interconnect/M00_ACLK
|
||||
ad_connect sys_cpu_clk axi_adc_dma_interconnect/M01_ACLK
|
||||
ad_connect sys_cpu_clk axi_pcie_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_resetn axi_adc_dma_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adc_dma_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adc_dma_interconnect/M00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_adc_dma_interconnect/M01_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_pcie_interconnect/S00_ARESETN
|
||||
ad_connect axi_ad9361_adc_dma/m_dest_axi axi_adc_dma_interconnect/S00_AXI
|
||||
ad_connect axi_adc_dma_interconnect/M00_AXI axi_hp1_interconnect/S00_AXI
|
||||
ad_connect axi_adc_dma_interconnect/M01_AXI axi_pcie_interconnect/S00_AXI
|
||||
# dac-dma split
|
||||
|
||||
set axi_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dac_dma_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {1}] $axi_dac_dma_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {2}] $axi_dac_dma_interconnect
|
||||
set axi_ddma_m_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddma_m_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {1}] $axi_ddma_m_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {2}] $axi_ddma_m_interconnect
|
||||
|
||||
ad_connect sys_cpu_clk axi_dac_dma_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_dac_dma_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_dac_dma_interconnect/M00_ACLK
|
||||
ad_connect sys_cpu_clk axi_dac_dma_interconnect/M01_ACLK
|
||||
ad_connect sys_cpu_clk axi_pcie_interconnect/S01_ACLK
|
||||
ad_connect sys_cpu_resetn axi_dac_dma_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_dac_dma_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_dac_dma_interconnect/M00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_dac_dma_interconnect/M01_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_pcie_interconnect/S01_ARESETN
|
||||
ad_connect axi_ad9361_dac_dma/m_src_axi axi_dac_dma_interconnect/S00_AXI
|
||||
ad_connect axi_dac_dma_interconnect/M00_AXI axi_hp2_interconnect/S00_AXI
|
||||
ad_connect axi_dac_dma_interconnect/M01_AXI axi_pcie_interconnect/S01_AXI
|
||||
ad_connect sys_cpu_clk axi_ddma_m_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_ddma_m_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_ddma_m_interconnect/M00_ACLK
|
||||
ad_connect sys_cpu_clk axi_ddma_m_interconnect/M01_ACLK
|
||||
ad_connect sys_cpu_resetn axi_ddma_m_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_ddma_m_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_ddma_m_interconnect/M00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_ddma_m_interconnect/M01_ARESETN
|
||||
ad_connect axi_ad9361_dac_dma/m_src_axi axi_ddma_m_interconnect/S00_AXI
|
||||
|
||||
ad_mem_hp0_interconnect pcie_axi_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect pcie_axi_clk axi_pcie_x4/M_AXI
|
||||
# pci-e slave
|
||||
|
||||
set axi_pcie_s_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_pcie_s_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {3}] $axi_pcie_s_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_pcie_s_interconnect
|
||||
|
||||
ad_connect pcie_axi_clk axi_pcie_s_interconnect/ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_s_interconnect/M00_ACLK
|
||||
ad_connect pcie_axi_clk axi_pcie_s_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_pcie_s_interconnect/S01_ACLK
|
||||
ad_connect sys_cpu_clk axi_pcie_s_interconnect/S02_ACLK
|
||||
ad_connect pcie_axi_resetn axi_pcie_s_interconnect/ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_s_interconnect/M00_ARESETN
|
||||
ad_connect pcie_axi_resetn axi_pcie_s_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_pcie_s_interconnect/S01_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_pcie_s_interconnect/S02_ARESETN
|
||||
ad_connect axi_pcie_m_interconnect/M00_AXI axi_pcie_s_interconnect/S00_AXI
|
||||
ad_connect axi_adma_m_interconnect/M00_AXI axi_pcie_s_interconnect/S01_AXI
|
||||
ad_connect axi_ddma_m_interconnect/M00_AXI axi_pcie_s_interconnect/S02_AXI
|
||||
ad_connect axi_pcie_s_interconnect/M00_AXI axi_pcie_x4/S_AXI
|
||||
|
||||
# hps7 slave
|
||||
|
||||
set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USE_S_AXI_HP1 {0} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USE_S_AXI_HP2 {0} [get_bd_cells sys_ps7]
|
||||
|
||||
set axi_hps7_s_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hps7_s_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {3}] $axi_hps7_s_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_hps7_s_interconnect
|
||||
|
||||
ad_connect sys_cpu_clk sys_ps7/S_AXI_HP0_ACLK
|
||||
ad_connect sys_cpu_clk axi_hps7_s_interconnect/ACLK
|
||||
ad_connect sys_cpu_clk axi_hps7_s_interconnect/M00_ACLK
|
||||
ad_connect pcie_axi_clk axi_hps7_s_interconnect/S00_ACLK
|
||||
ad_connect sys_cpu_clk axi_hps7_s_interconnect/S01_ACLK
|
||||
ad_connect sys_cpu_clk axi_hps7_s_interconnect/S02_ACLK
|
||||
ad_connect sys_cpu_resetn axi_hps7_s_interconnect/ARESETN
|
||||
ad_connect sys_cpu_resetn axi_hps7_s_interconnect/M00_ARESETN
|
||||
ad_connect pcie_axi_resetn axi_hps7_s_interconnect/S00_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_hps7_s_interconnect/S01_ARESETN
|
||||
ad_connect sys_cpu_resetn axi_hps7_s_interconnect/S02_ARESETN
|
||||
ad_connect axi_pcie_m_interconnect/M01_AXI axi_hps7_s_interconnect/S00_AXI
|
||||
ad_connect axi_adma_m_interconnect/M01_AXI axi_hps7_s_interconnect/S01_AXI
|
||||
ad_connect axi_ddma_m_interconnect/M01_AXI axi_hps7_s_interconnect/S02_AXI
|
||||
ad_connect axi_hps7_s_interconnect/M00_AXI sys_ps7/S_AXI_HP0
|
||||
|
||||
assign_bd_address [get_bd_addr_segs {axi_iic_main/S_AXI/Reg}]
|
||||
assign_bd_address [get_bd_addr_segs {axi_ad9361/s_axi/axi_lite}]
|
||||
assign_bd_address [get_bd_addr_segs {axi_ad9361_dac_dma/s_axi/axi_lite}]
|
||||
assign_bd_address [get_bd_addr_segs {axi_ad9361_adc_dma/s_axi/axi_lite}]
|
||||
assign_bd_address [get_bd_addr_segs {axi_pcie_x4/S_AXI_CTL/CTL0}]
|
||||
assign_bd_address [get_bd_addr_segs {axi_pcie_intc/s_axi/Reg}]
|
||||
|
||||
set_property offset 0x41600000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_iic_main_Reg}]
|
||||
set_property offset 0x79020000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_ad9361_axi_lite}]
|
||||
set_property offset 0x7C400000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_ad9361_dac_dma_axi_lite}]
|
||||
set_property offset 0x7C420000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_ad9361_adc_dma_axi_lite}]
|
||||
set_property offset 0x50000000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_pcie_x4_CTL0}]
|
||||
set_property offset 0x41200000 [get_bd_addr_segs {axi_pcie_x4/M_AXI/SEG_axi_pcie_intc_Reg}]
|
||||
|
||||
set_property offset 0x41600000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_iic_main_Reg}]
|
||||
set_property offset 0x79020000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_ad9361_axi_lite}]
|
||||
set_property offset 0x7C400000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_ad9361_dac_dma_axi_lite}]
|
||||
set_property offset 0x7C420000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_ad9361_adc_dma_axi_lite}]
|
||||
set_property offset 0x50000000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_pcie_x4_CTL0}]
|
||||
set_property offset 0x41200000 [get_bd_addr_segs {sys_ps7/Data/SEG_axi_pcie_intc_Reg}]
|
||||
|
||||
assign_bd_address [get_bd_addr_segs {axi_pcie_x4/S_AXI/BAR0}]
|
||||
|
||||
#create_bd_addr_seg -range 0x10000000 -offset 0x44a60000 [get_bd_addr_spaces sys_ps7/Data] \
|
||||
# [get_bd_addr_segs axi_pcie_x4/S_AXI_CTL/CTL0] SEG_data_axi_pcie_x4
|
||||
assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM}]
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue