From 985ace533e56d89158229de3cd52b5fa6bb7e153 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 24 Jun 2014 14:26:40 -0400 Subject: [PATCH] ad9361: remove unused modules --- library/axi_ad9361/axi_ad9361_ila.tcl | 54 ---- library/axi_ad9361/axi_ad9361_pnlb.v | 221 --------------- library/axi_ad9361/axi_ad9361_pnlb_1.v | 354 ------------------------- library/axi_ad9361/axi_ad9361_tx_dds.v | 133 ---------- 4 files changed, 762 deletions(-) delete mode 100644 library/axi_ad9361/axi_ad9361_ila.tcl delete mode 100755 library/axi_ad9361/axi_ad9361_pnlb.v delete mode 100755 library/axi_ad9361/axi_ad9361_pnlb_1.v delete mode 100755 library/axi_ad9361/axi_ad9361_tx_dds.v diff --git a/library/axi_ad9361/axi_ad9361_ila.tcl b/library/axi_ad9361/axi_ad9361_ila.tcl deleted file mode 100644 index fd79b36fa..000000000 --- a/library/axi_ad9361/axi_ad9361_ila.tcl +++ /dev/null @@ -1,54 +0,0 @@ -# ila debug - -proc adi_ila_probe {w_obj w_msb w_lsb w_name} { - - add_wave_virtual_bus -radix hex $w_name - for {set b $w_lsb} {$b <= $w_msb} {incr b} { - add_wave -into $w_name "$w_obj[$b]" - } -} - -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 5 0 tx_data_n -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 11 6 tx_data_p -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 23 12 tx_data_i1_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 35 24 tx_data_q1_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 47 36 tx_data_i2_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 59 48 tx_data_q2_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 63 60 tx_data_sel_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 66 64 tx_data_cnt -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 67 67 tx_frame -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 68 68 dac_r1_mode -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 69 69 dac_valid -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 81 70 dac_data_i1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 93 82 dac_data_q1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 105 94 dac_data_i2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 117 106 dac_data_q2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 118 118 rx_frame_p_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 119 119 rx_frame_n_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 120 120 rx_frame_n -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 122 121 rx_frame -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 124 123 rx_frame_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 128 125 rx_frame_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 134 129 rx_data_p_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 140 135 rx_data_n_s -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 146 141 rx_data_n -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 158 147 rx_data -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 170 159 rx_data_d -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 171 171 rx_error_r1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 172 172 rx_valid_r1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 184 173 rx_data_i_r1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 196 185 rx_data_q_r1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 197 197 rx_error_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 198 198 rx_valid_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 210 199 rx_data_i1_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 222 211 rx_data_q1_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 234 223 rx_data_i2_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 246 235 rx_data_q2_r2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 247 247 adc_r1_mode -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 248 248 adc_status -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 249 249 adc_valid -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 261 250 adc_data_i1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 273 262 adc_data_q1 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 285 274 adc_data_i2 -adi_ila_probe system_i/axi_ad9361_1_dev_dbg_data 297 286 adc_data_q2 - diff --git a/library/axi_ad9361/axi_ad9361_pnlb.v b/library/axi_ad9361/axi_ad9361_pnlb.v deleted file mode 100755 index f2a56d6f5..000000000 --- a/library/axi_ad9361/axi_ad9361_pnlb.v +++ /dev/null @@ -1,221 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). - -`timescale 1ns/100ps - -module axi_ad9361_pnlb ( - - // interface - inputs - - clk, - adc_valid_in, - adc_data_in_i1, - adc_data_in_q1, - adc_data_in_i2, - adc_data_in_q2, - dac_valid_in, - dac_data_in_i1, - dac_data_in_q1, - dac_data_in_i2, - dac_data_in_q2, - - // interface - outputs - - adc_valid, - adc_data_i1, - adc_data_q1, - adc_data_i2, - adc_data_q2, - dac_valid, - dac_data_i1, - dac_data_q1, - dac_data_i2, - dac_data_q2, - - // control signals - - adc_lb_enb_i1, - dac_lb_enb_i1, - dac_pn_enb_i1, - adc_lb_enb_q1, - dac_lb_enb_q1, - dac_pn_enb_q1, - adc_lb_enb_i2, - dac_lb_enb_i2, - dac_pn_enb_i2, - adc_lb_enb_q2, - dac_lb_enb_q2, - dac_pn_enb_q2, - - // status signals - - adc_pn_oos_i1, - adc_pn_err_i1, - adc_pn_oos_q1, - adc_pn_err_q1, - adc_pn_oos_i2, - adc_pn_err_i2, - adc_pn_oos_q2, - adc_pn_err_q2); - - // device interface - - input clk; - input adc_valid_in; - input [11:0] adc_data_in_i1; - input [11:0] adc_data_in_q1; - input [11:0] adc_data_in_i2; - input [11:0] adc_data_in_q2; - input dac_valid_in; - input [11:0] dac_data_in_i1; - input [11:0] dac_data_in_q1; - input [11:0] dac_data_in_i2; - input [11:0] dac_data_in_q2; - - // dac outputs - - output adc_valid; - output [11:0] adc_data_i1; - output [11:0] adc_data_q1; - output [11:0] adc_data_i2; - output [11:0] adc_data_q2; - output dac_valid; - output [11:0] dac_data_i1; - output [11:0] dac_data_q1; - output [11:0] dac_data_i2; - output [11:0] dac_data_q2; - - // control signals - - input adc_lb_enb_i1; - input dac_lb_enb_i1; - input dac_pn_enb_i1; - input adc_lb_enb_q1; - input dac_lb_enb_q1; - input dac_pn_enb_q1; - input adc_lb_enb_i2; - input dac_lb_enb_i2; - input dac_pn_enb_i2; - input adc_lb_enb_q2; - input dac_lb_enb_q2; - input dac_pn_enb_q2; - - // status signals - - output adc_pn_oos_i1; - output adc_pn_err_i1; - output adc_pn_oos_q1; - output adc_pn_err_q1; - output adc_pn_oos_i2; - output adc_pn_err_i2; - output adc_pn_oos_q2; - output adc_pn_err_q2; - - // instantiations - - axi_ad9361_pnlb_1 #(.PRBS_SEL(0)) i_pnlb_i1 ( - .clk (clk), - .adc_valid_in (adc_valid_in), - .adc_data_in (adc_data_in_i1), - .dac_valid_in (dac_valid_in), - .dac_data_in (dac_data_in_i1), - .adc_valid (adc_valid), - .adc_data (adc_data_i1), - .dac_valid (dac_valid), - .dac_data (dac_data_i1), - .adc_lb_enb (adc_lb_enb_i1), - .dac_lb_enb (dac_lb_enb_i1), - .dac_pn_enb (dac_pn_enb_i1), - .adc_pn_oos (adc_pn_oos_i1), - .adc_pn_err (adc_pn_err_i1)); - - axi_ad9361_pnlb_1 #(.PRBS_SEL(1)) i_pnlb_q1 ( - .clk (clk), - .adc_valid_in (adc_valid_in), - .adc_data_in (adc_data_in_q1), - .dac_valid_in (dac_valid_in), - .dac_data_in (dac_data_in_q1), - .adc_valid (), - .adc_data (adc_data_q1), - .dac_valid (), - .dac_data (dac_data_q1), - .adc_lb_enb (adc_lb_enb_q1), - .dac_lb_enb (dac_lb_enb_q1), - .dac_pn_enb (dac_pn_enb_q1), - .adc_pn_oos (adc_pn_oos_q1), - .adc_pn_err (adc_pn_err_q1)); - - axi_ad9361_pnlb_1 #(.PRBS_SEL(2)) i_pnlb_i2 ( - .clk (clk), - .adc_valid_in (adc_valid_in), - .adc_data_in (adc_data_in_i2), - .dac_valid_in (dac_valid_in), - .dac_data_in (dac_data_in_i2), - .adc_valid (), - .adc_data (adc_data_i2), - .dac_valid (), - .dac_data (dac_data_i2), - .adc_lb_enb (adc_lb_enb_i2), - .dac_lb_enb (dac_lb_enb_i2), - .dac_pn_enb (dac_pn_enb_i2), - .adc_pn_oos (adc_pn_oos_i2), - .adc_pn_err (adc_pn_err_i2)); - - axi_ad9361_pnlb_1 #(.PRBS_SEL(3)) i_pnlb_q2 ( - .clk (clk), - .adc_valid_in (adc_valid_in), - .adc_data_in (adc_data_in_q2), - .dac_valid_in (dac_valid_in), - .dac_data_in (dac_data_in_q2), - .adc_valid (), - .adc_data (adc_data_q2), - .dac_valid (), - .dac_data (dac_data_q2), - .adc_lb_enb (adc_lb_enb_q2), - .dac_lb_enb (dac_lb_enb_q2), - .dac_pn_enb (dac_pn_enb_q2), - .adc_pn_oos (adc_pn_oos_q2), - .adc_pn_err (adc_pn_err_q2)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_pnlb_1.v b/library/axi_ad9361/axi_ad9361_pnlb_1.v deleted file mode 100755 index 84988ced8..000000000 --- a/library/axi_ad9361/axi_ad9361_pnlb_1.v +++ /dev/null @@ -1,354 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// This interface includes both the transmit and receive components - -// They both uses the same clock (sourced from the receiving side). - -`timescale 1ns/100ps - -module axi_ad9361_pnlb_1 ( - - // device interface - - clk, - adc_valid_in, - adc_data_in, - dac_valid_in, - dac_data_in, - - // dac outputs - - adc_valid, - adc_data, - dac_valid, - dac_data, - - // control signals - - adc_lb_enb, - dac_lb_enb, - dac_pn_enb, - - // status signals - - adc_pn_oos, - adc_pn_err); - - // parameters - - parameter PRBS_SEL = 0; - localparam PRBS_P09 = 0; - localparam PRBS_P11 = 1; - localparam PRBS_P15 = 2; - localparam PRBS_P20 = 3; - - // device interface - - input clk; - input adc_valid_in; - input [11:0] adc_data_in; - input dac_valid_in; - input [11:0] dac_data_in; - - // dac outputs - - output adc_valid; - output [11:0] adc_data; - output dac_valid; - output [11:0] dac_data; - - // control signals - - input adc_lb_enb; - input dac_lb_enb; - input dac_pn_enb; - - // status signals - - output adc_pn_oos; - output adc_pn_err; - - // internal registers - - reg dac_valid_t = 'd0; - reg [23:0] dac_pn = 'd0; - reg [11:0] dac_lb = 'd0; - reg dac_valid = 'd0; - reg [11:0] dac_data = 'd0; - reg [11:0] adc_lb = 'd0; - reg adc_valid = 'd0; - reg [11:0] adc_data = 'd0; - reg adc_valid_t = 'd0; - reg [11:0] adc_data_in_d = 'd0; - reg [23:0] adc_pn_data = 'd0; - reg adc_pn_err = 'd0; - reg adc_pn_oos = 'd0; - reg [ 3:0] adc_pn_oos_count = 'd0; - - // internal signals - - wire dac_valid_t_s; - wire adc_valid_t_s; - wire [23:0] adc_data_in_s; - wire adc_pn_err_s; - wire adc_pn_update_s; - wire adc_pn_match_s; - wire adc_pn_match_z_s; - wire adc_pn_match_d_s; - wire [23:0] adc_pn_data_s; - - // prbs functions - - function [23:0] pn; - input [23:0] din; - reg [23:0] dout; - begin - case (PRBS_SEL) - PRBS_P09: begin - dout[23] = din[ 8] ^ din[ 4]; - dout[22] = din[ 7] ^ din[ 3]; - dout[21] = din[ 6] ^ din[ 2]; - dout[20] = din[ 5] ^ din[ 1]; - dout[19] = din[ 4] ^ din[ 0]; - dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; - dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; - dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; - dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; - dout[14] = din[ 8] ^ din[ 0]; - dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; - dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; - dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; - dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; - dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; - dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; - dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; - dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; - dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; - dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; - dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; - dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; - dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; - end - PRBS_P11: begin - dout[23] = din[10] ^ din[ 8]; - dout[22] = din[ 9] ^ din[ 7]; - dout[21] = din[ 8] ^ din[ 6]; - dout[20] = din[ 7] ^ din[ 5]; - dout[19] = din[ 6] ^ din[ 4]; - dout[18] = din[ 5] ^ din[ 3]; - dout[17] = din[ 4] ^ din[ 2]; - dout[16] = din[ 3] ^ din[ 1]; - dout[15] = din[ 2] ^ din[ 0]; - dout[14] = din[ 1] ^ din[10] ^ din[ 8]; - dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; - dout[12] = din[10] ^ din[ 6]; - dout[11] = din[ 9] ^ din[ 5]; - dout[10] = din[ 8] ^ din[ 4]; - dout[ 9] = din[ 7] ^ din[ 3]; - dout[ 8] = din[ 6] ^ din[ 2]; - dout[ 7] = din[ 5] ^ din[ 1]; - dout[ 6] = din[ 4] ^ din[ 0]; - dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; - dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; - dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; - dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; - dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; - dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; - end - PRBS_P15: begin - dout[23] = din[14] ^ din[13]; - dout[22] = din[13] ^ din[12]; - dout[21] = din[12] ^ din[11]; - dout[20] = din[11] ^ din[10]; - dout[19] = din[10] ^ din[ 9]; - dout[18] = din[ 9] ^ din[ 8]; - dout[17] = din[ 8] ^ din[ 7]; - dout[16] = din[ 7] ^ din[ 6]; - dout[15] = din[ 6] ^ din[ 5]; - dout[14] = din[ 5] ^ din[ 4]; - dout[13] = din[ 4] ^ din[ 3]; - dout[12] = din[ 3] ^ din[ 2]; - dout[11] = din[ 2] ^ din[ 1]; - dout[10] = din[ 1] ^ din[ 0]; - dout[ 9] = din[ 0] ^ din[14] ^ din[13]; - dout[ 8] = din[14] ^ din[12]; - dout[ 7] = din[13] ^ din[11]; - dout[ 6] = din[12] ^ din[10]; - dout[ 5] = din[11] ^ din[ 9]; - dout[ 4] = din[10] ^ din[ 8]; - dout[ 3] = din[ 9] ^ din[ 7]; - dout[ 2] = din[ 8] ^ din[ 6]; - dout[ 1] = din[ 7] ^ din[ 5]; - dout[ 0] = din[ 6] ^ din[ 4]; - end - PRBS_P20: begin - dout[23] = din[19] ^ din[ 2]; - dout[22] = din[18] ^ din[ 1]; - dout[21] = din[17] ^ din[ 0]; - dout[20] = din[16] ^ din[19] ^ din[ 2]; - dout[19] = din[15] ^ din[18] ^ din[ 1]; - dout[18] = din[14] ^ din[17] ^ din[ 0]; - dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; - dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; - dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; - dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; - dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; - dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; - dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; - dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; - end - endcase - pn = dout; - end - endfunction - - // prbs generators run at 24bits wide - - assign dac_valid_t_s = dac_valid_in & dac_valid_t; - - always @(posedge clk) begin - if (dac_valid_in == 1'b1) begin - dac_valid_t <= ~dac_valid_t; - end - if (dac_pn_enb == 1'b0) begin - dac_pn <= 24'hffffff; - end else if (dac_valid_t_s == 1'b1) begin - dac_pn <= pn(dac_pn); - end - end - - // hold adc data for loopback, it is assumed that there is a one to one mapping - // of receive and transmit (the rates are the same). - - always @(posedge clk) begin - if (dac_valid_in == 1'b1) begin - dac_lb <= adc_data_in; - end - end - - // dac outputs- - - always @(posedge clk) begin - dac_valid <= dac_valid_in; - if (dac_pn_enb == 1'b1) begin - if (dac_valid_t == 1'b1) begin - dac_data <= dac_pn[11:0]; - end else begin - dac_data <= dac_pn[23:12]; - end - end else if (dac_lb_enb == 1'b1) begin - dac_data <= dac_lb; - end else begin - dac_data <= dac_data_in; - end - end - - // hold dac data for loopback, it is assumed that there is a one to one mapping - // of receive and transmit (the rates are the same). - - always @(posedge clk) begin - if (adc_valid_in == 1'b1) begin - adc_lb <= dac_data_in; - end - end - - // adc outputs- - - always @(posedge clk) begin - adc_valid <= adc_valid_in; - if (adc_lb_enb == 1'b1) begin - adc_data <= adc_lb; - end else begin - adc_data <= adc_data_in; - end - end - - // adc pn monitoring - - assign adc_valid_t_s = adc_valid_in & adc_valid_t; - assign adc_data_in_s = {adc_data_in_d, adc_data_in}; - assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s); - assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s); - assign adc_pn_match_s = adc_pn_match_d_s & adc_pn_match_z_s; - assign adc_pn_match_z_s = (adc_data_in_s == 24'd0) ? 1'b0 : 1'b1; - assign adc_pn_match_d_s = (adc_data_in_s == adc_pn_data) ? 1'b1 : 1'b0; - assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_in_s : adc_pn_data; - - // adc pn running sequence - - always @(posedge clk) begin - if (adc_valid_in == 1'b1) begin - adc_valid_t <= ~adc_valid_t; - adc_data_in_d <= adc_data_in; - end - if (adc_valid_t_s == 1'b1) begin - adc_pn_data <= pn(adc_pn_data_s); - end - end - - // pn oos and counters (16 to clear and set). - - always @(posedge clk) begin - if (adc_valid_t_s == 1'b1) begin - adc_pn_err <= adc_pn_err_s; - if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin - adc_pn_oos <= ~adc_pn_oos; - end - if (adc_pn_update_s == 1'b1) begin - adc_pn_oos_count <= adc_pn_oos_count + 1'b1; - end else begin - adc_pn_oos_count <= 'd0; - end - end - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9361/axi_ad9361_tx_dds.v b/library/axi_ad9361/axi_ad9361_tx_dds.v deleted file mode 100755 index b40474ab8..000000000 --- a/library/axi_ad9361/axi_ad9361_tx_dds.v +++ /dev/null @@ -1,133 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9361_tx_dds ( - - // dac interface - - dac_clk, - dac_rst, - dac_dds_data, - - // processor interface - - dac_dds_enable, - dac_dds_data_enable, - dac_dds_format, - dac_dds_pattenb, - dac_dds_patt_1, - dac_dds_init_1, - dac_dds_incr_1, - dac_dds_scale_1, - dac_dds_patt_2, - dac_dds_init_2, - dac_dds_incr_2, - dac_dds_scale_2); - - // parameters - - parameter DP_DISABLE = 0; - - // dac interface - - input dac_clk; - input dac_rst; - output [15:0] dac_dds_data; - - // processor interface - - input dac_dds_enable; - input dac_dds_data_enable; - input dac_dds_format; - input dac_dds_pattenb; - input [15:0] dac_dds_patt_1; - input [15:0] dac_dds_init_1; - input [15:0] dac_dds_incr_1; - input [15:0] dac_dds_scale_1; - input [15:0] dac_dds_patt_2; - input [15:0] dac_dds_init_2; - input [15:0] dac_dds_incr_2; - input [15:0] dac_dds_scale_2; - - // internal registers - - reg [15:0] dac_dds_phase_0 = 'd0; - reg [15:0] dac_dds_phase_1 = 'd0; - reg dac_dds_datasel = 'd0; - reg [15:0] dac_dds_data = 'd0; - - // internal signals - - wire [15:0] dac_dds_data_s; - - // dds phase counters - - always @(posedge dac_clk) begin - if (dac_dds_enable == 1'b0) begin - dac_dds_phase_0 <= dac_dds_init_1; - dac_dds_phase_1 <= dac_dds_init_2; - end else if (dac_dds_data_enable == 1'b1) begin - dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_1; - dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_2; - end - end - - // output is either 2's complement or offset binary. - - always @(posedge dac_clk) begin - if (dac_dds_data_enable == 1'b1) begin - dac_dds_datasel <= ~dac_dds_datasel; - if (dac_dds_pattenb == 1'b0) begin - dac_dds_data <= dac_dds_data_s; - end else if (dac_dds_datasel == 1'b1) begin - dac_dds_data <= dac_dds_patt_2; - end else begin - dac_dds_data <= dac_dds_patt_1; - end - end - end - - // dds - -endmodule - -// *************************************************************************** -// ***************************************************************************