From 9934cce5d2a8ac214a29acbc041c51260fb39151 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 11 May 2015 12:12:30 +0300 Subject: [PATCH] util_dacfifo: Add CDC logic for dma_lastaddr register. --- library/util_dacfifo/util_dacfifo.v | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/library/util_dacfifo/util_dacfifo.v b/library/util_dacfifo/util_dacfifo.v index b3f44c141..ccd2097b1 100644 --- a/library/util_dacfifo/util_dacfifo.v +++ b/library/util_dacfifo/util_dacfifo.v @@ -86,12 +86,14 @@ module util_dacfifo ( reg [(ADDR_WIDTH-1):0] dma_waddr = 'b0; reg [(ADDR_WIDTH-1):0] dma_lastaddr = 'b0; + reg [(ADDR_WIDTH-1):0] dma_lastaddr_d = 'b0; + reg [(ADDR_WIDTH-1):0] dma_lastaddr_2d = 'b0; reg dma_xfer_req_ff = 1'b0; reg dma_ready = 1'b0; reg [(ADDR_WIDTH-1):0] dac_raddr = 'b0; reg [(DATA_WIDTH-1):0] dac_data = 'b0; - + // internal wires wire dma_wren; wire [(DATA_WIDTH-1):0] dac_data_s; @@ -125,9 +127,17 @@ module util_dacfifo ( assign dma_wren = dma_valid & dma_xfer_req; // read interface + + // sync lastaddr to dac clock domain + always @(posedge dac_clk) begin + dma_lastaddr_d <= dma_lastaddr; + dma_lastaddr_2d <= dma_lastaddr_d; + end + + // generate dac read address always @(posedge dac_clk) begin if(dac_valid == 1'b1) begin - dac_raddr <= (dac_raddr < dma_lastaddr) ? (dac_raddr + 1) : 'b0; + dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0; end dac_data <= dac_data_s; end