From 99d66e758049fa1579a5cd79a2c522d1be9099e9 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 28 Apr 2014 11:02:40 -0400
Subject: [PATCH] a5soc: initial-copy version

---
 projects/common/a5soc/a5soc_system_assign.tcl |  485 +++++
 projects/fmcjesdadc1/a5soc/system_bd.qsys     | 1719 +++++++++++++++++
 projects/fmcjesdadc1/a5soc/system_constr.sdc  |   16 +
 projects/fmcjesdadc1/a5soc/system_project.tcl |   81 +
 projects/fmcjesdadc1/a5soc/system_timing.tcl  |    3 +
 projects/fmcjesdadc1/a5soc/system_top.v       |  524 +++++
 6 files changed, 2828 insertions(+)
 create mode 100755 projects/common/a5soc/a5soc_system_assign.tcl
 create mode 100755 projects/fmcjesdadc1/a5soc/system_bd.qsys
 create mode 100755 projects/fmcjesdadc1/a5soc/system_constr.sdc
 create mode 100755 projects/fmcjesdadc1/a5soc/system_project.tcl
 create mode 100755 projects/fmcjesdadc1/a5soc/system_timing.tcl
 create mode 100755 projects/fmcjesdadc1/a5soc/system_top.v

diff --git a/projects/common/a5soc/a5soc_system_assign.tcl b/projects/common/a5soc/a5soc_system_assign.tcl
new file mode 100755
index 000000000..a39e41360
--- /dev/null
+++ b/projects/common/a5soc/a5soc_system_assign.tcl
@@ -0,0 +1,485 @@
+
+# clocks
+
+set_location_assignment PIN_AU32 -to sys_clk
+set_instance_assignment -name IO_STANDARD "1.5 V" -to sys_clk
+
+# ethernet
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
+
+# qspi
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_ss0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io3
+
+# sdio
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_cmd
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d3
+
+# usb
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d7
+
+# uart
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_rx
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_tx
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart1_rx
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart1_tx
+
+# i2c
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_scl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c0_sda
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c0_scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c0_sda
+
+# trace
+
+set_instance_assignment -name SLEW_RATE 1 -to trace_clk
+set_instance_assignment -name SLEW_RATE 1 -to trace_d0
+set_instance_assignment -name SLEW_RATE 1 -to trace_d1
+set_instance_assignment -name SLEW_RATE 1 -to trace_d2
+set_instance_assignment -name SLEW_RATE 1 -to trace_d3
+set_instance_assignment -name SLEW_RATE 1 -to trace_d4
+set_instance_assignment -name SLEW_RATE 1 -to trace_d5
+set_instance_assignment -name SLEW_RATE 1 -to trace_d6
+set_instance_assignment -name SLEW_RATE 1 -to trace_d7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to trace_d7
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_clk
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d0
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d2
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d3
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d4
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d5
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d6
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to trace_d7
+
+# gpio
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio00
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio17
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio18
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio22
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio24
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio26
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio35
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio40
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio41
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio42
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_gpio43
+
+# gpio
+
+set_location_assignment PIN_AW23 -to fpga_button_pio[3]
+set_location_assignment PIN_AW24 -to fpga_button_pio[2]
+set_location_assignment PIN_AP24 -to fpga_button_pio[1]
+set_location_assignment PIN_AT23 -to fpga_button_pio[0]
+set_location_assignment PIN_AU23 -to fpga_dipsw_pio[3]
+set_location_assignment PIN_AE24 -to fpga_dipsw_pio[2]
+set_location_assignment PIN_AF24 -to fpga_dipsw_pio[1]
+set_location_assignment PIN_AL24 -to fpga_dipsw_pio[0]
+set_location_assignment PIN_AD24 -to fpga_led_pio[3]
+set_location_assignment PIN_AT24 -to fpga_led_pio[2]
+set_location_assignment PIN_AU24 -to fpga_led_pio[1]
+set_location_assignment PIN_AH24 -to fpga_led_pio[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_button_pio[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_button_pio[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_button_pio[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_button_pio[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_dipsw_pio[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_dipsw_pio[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_dipsw_pio[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_dipsw_pio[0]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_led_pio[3]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_led_pio[2]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_led_pio[1]
+set_instance_assignment -name IO_STANDARD "1.5 V" -to fpga_led_pio[0]
+
+# ddr
+
+set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_p
+set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_n
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
+
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n
+set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n
+
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
+set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
+
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_p
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_n
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
+set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4]
+
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39]
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_oct_rzqin
+
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_p
+set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_n
+
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[5]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[6]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[7]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[8]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[9]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[10]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[11]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[12]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[13]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[14]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cas_n
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_p
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_n
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cke
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cs_n
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[5]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[6]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[7]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[8]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[9]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[10]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[11]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[12]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[13]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[14]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[15]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[16]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[17]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[18]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[19]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[20]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[21]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[22]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[23]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[24]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[25]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[26]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[27]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[28]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[29]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[30]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[31]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[32]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[33]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[34]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[35]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[36]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[37]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[38]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[39]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[0]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[1]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[2]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[3]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[4]
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_odt
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ras_n
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_reset_n
+set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
+
+set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
+
+# globals
+
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
+set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name ECO_REGENERATE_REPORT ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
diff --git a/projects/fmcjesdadc1/a5soc/system_bd.qsys b/projects/fmcjesdadc1/a5soc/system_bd.qsys
new file mode 100755
index 000000000..3316de6a9
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_bd.qsys
@@ -0,0 +1,1719 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element sys_uart.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "66576";
+         type = "String";
+      }
+   }
+   element axi_ad9250_0
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element axi_ad9250_1
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element axi_dmac_0
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+   }
+   element axi_dmac_1
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum baseAddress
+      {
+         value = "66584";
+         type = "String";
+      }
+   }
+   element sys_hps.f2h_axi_slave
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_hps.f2h_sdram0_data
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_hps.f2h_sdram1_data
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_jesd204b_s1.jesd204_rx_avs
+   {
+      datum baseAddress
+      {
+         value = "65536";
+         type = "String";
+      }
+   }
+   element sys_gpio.s1
+   {
+      datum baseAddress
+      {
+         value = "66560";
+         type = "String";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_dmac_0.s_axi
+   {
+      datum baseAddress
+      {
+         value = "32768";
+         type = "String";
+      }
+   }
+   element axi_ad9250_0.s_axi
+   {
+      datum baseAddress
+      {
+         value = "49152";
+         type = "String";
+      }
+   }
+   element axi_ad9250_1.s_axi
+   {
+      datum baseAddress
+      {
+         value = "16384";
+         type = "String";
+      }
+   }
+   element axi_dmac_1.s_axi
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element sys_gpio
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+   }
+   element sys_hps
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element sys_jesd204b_s1
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element sys_jesd204b_s1_pll
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sys_jesd204b_s1_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
+   element sys_jesd204b_s1_rx_clk
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element sys_jtag_hps_axi
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sys_jtag_hps_sdram
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element sys_jtag_pl
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5ASTFD5K3F40I3ES" />
+ <parameter name="deviceFamily" value="Arria V" />
+ <parameter name="deviceSpeedGrade" value="3_H3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName">fmcjesdadc1_a5soc.qpf</parameter>
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="memory" internal="sys_hps.memory" type="conduit" dir="end" />
+ <interface name="clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <interface name="reset" internal="sys_clk.clk_in_reset" type="reset" dir="end" />
+ <interface name="hps_0_emac0" internal="sys_hps.emac0" />
+ <interface name="hps_0_emac0_md_clk" internal="sys_hps.emac0_md_clk" />
+ <interface name="hps_0_emac0_rx_clk_in" internal="sys_hps.emac0_rx_clk_in" />
+ <interface name="hps_0_emac0_tx_clk_in" internal="sys_hps.emac0_tx_clk_in" />
+ <interface name="hps_0_emac0_gtx_clk" internal="sys_hps.emac0_gtx_clk" />
+ <interface name="hps_0_emac0_tx_reset" internal="sys_hps.emac0_tx_reset" />
+ <interface name="hps_0_emac0_rx_reset" internal="sys_hps.emac0_rx_reset" />
+ <interface name="hps_0_emac_ptp_ref_clock" internal="sys_hps.emac_ptp_ref_clock" />
+ <interface
+   name="axi_ad9250_0_xcvr_clk"
+   internal="axi_ad9250_0.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9250_0_xcvr_data"
+   internal="axi_ad9250_0.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9250_0_adc_clock"
+   internal="axi_ad9250_0.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9250_0_adc_dma_if"
+   internal="axi_ad9250_0.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9250_0_adc_mon_if"
+   internal="axi_ad9250_0.adc_mon_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_dmac_0_fifo_wr_clock"
+   internal="axi_dmac_0.fifo_wr_clock"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_dmac_0_fifo_wr_if"
+   internal="axi_dmac_0.fifo_wr_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9250_1_xcvr_clk"
+   internal="axi_ad9250_1.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9250_1_xcvr_data"
+   internal="axi_ad9250_1.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9250_1_adc_clock"
+   internal="axi_ad9250_1.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9250_1_adc_dma_if"
+   internal="axi_ad9250_1.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9250_1_adc_mon_if"
+   internal="axi_ad9250_1.adc_mon_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_dmac_1_fifo_wr_clock"
+   internal="axi_dmac_1.fifo_wr_clock"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_dmac_1_fifo_wr_if"
+   internal="axi_dmac_1.fifo_wr_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_ref_clk_in_clk"
+   internal="sys_jesd204b_s1_ref_clk.in_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_clk_out_clk"
+   internal="sys_jesd204b_s1_rx_clk.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_jesd204b_s1_jesd204_rx_link"
+   internal="sys_jesd204b_s1.jesd204_rx_link"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="sys_jesd204b_s1_alldev_lane_aligned"
+   internal="sys_jesd204b_s1.alldev_lane_aligned"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_sysref"
+   internal="sys_jesd204b_s1.sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_jesd204_rx_frame_error"
+   internal="sys_jesd204b_s1.jesd204_rx_frame_error"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_dev_lane_aligned"
+   internal="sys_jesd204b_s1.dev_lane_aligned"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_dev_sync_n"
+   internal="sys_jesd204b_s1.dev_sync_n"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_sof"
+   internal="sys_jesd204b_s1.sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_serial_data"
+   internal="sys_jesd204b_s1.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_analogreset"
+   internal="sys_jesd204b_s1.rx_analogreset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_digitalreset"
+   internal="sys_jesd204b_s1.rx_digitalreset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_islockedtodata"
+   internal="sys_jesd204b_s1.rx_islockedtodata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_cal_busy"
+   internal="sys_jesd204b_s1.rx_cal_busy"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0"
+   internal="sys_hps.spim0"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_pll_locked"
+   internal="sys_jesd204b_s1_pll.locked"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_hps_spim0_sclk_out"
+   internal="sys_hps.spim0_sclk_out"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_hps_f2h_cold_reset_req"
+   internal="sys_hps.f2h_cold_reset_req" />
+ <interface
+   name="sys_hps_f2h_debug_reset_req"
+   internal="sys_hps.f2h_debug_reset_req" />
+ <interface
+   name="sys_hps_f2h_warm_reset_req"
+   internal="sys_hps.f2h_warm_reset_req" />
+ <interface
+   name="sys_hps_f2h_stm_hw_events"
+   internal="sys_hps.f2h_stm_hw_events"
+   type="conduit"
+   dir="end" />
+ <interface name="hps_io" internal="sys_hps.hps_io" type="conduit" dir="end" />
+ <interface
+   name="sys_hps_h2f_reset"
+   internal="sys_hps.h2f_reset"
+   type="reset"
+   dir="start" />
+ <interface
+   name="sys_gpio_external_connection"
+   internal="sys_gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <module kind="altera_hps" version="13.1" enabled="1" name="sys_hps">
+  <parameter name="MEM_VENDOR" value="JEDEC" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="RDIMM_CONFIG" value="0000000000000000" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="40" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/4" />
+  <parameter name="MEM_RTT_WR" value="Dynamic ODT off" />
+  <parameter name="MEM_WTCL" value="6" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_TCL" value="7" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TQHS" value="300" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TDQSCK" value="225" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TDQSH" value="0.35" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="260.0" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="4" />
+  <parameter name="MEM_TFAW_NS" value="35.0" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="AVL_MAX_SIZE" value="4" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="true" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="true" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="MAX_PENDING_WR_CMD" value="8" />
+  <parameter name="MAX_PENDING_RD_CMD" value="16" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="REF_CLK_FREQ" value="25.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="DEFAULT_FAST_SIM_MODEL" value="true" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="RATE" value="Full" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="SPEED_GRADE" value="7" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="HARD_EMIF" value="true" />
+  <parameter name="HHP_HPS" value="true" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DDR3" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="MPU_EVENTS_Enable" value="false" />
+  <parameter name="GP_Enable" value="false" />
+  <parameter name="DEBUGAPB_Enable" value="false" />
+  <parameter name="STM_Enable" value="true" />
+  <parameter name="CTI_Enable" value="false" />
+  <parameter name="TPIUFPGA_Enable" value="false" />
+  <parameter name="BOOTFROMFPGA_Enable" value="false" />
+  <parameter name="TEST_Enable" value="false" />
+  <parameter name="HLGPI_Enable" value="false" />
+  <parameter name="BSEL_EN" value="false" />
+  <parameter name="BSEL" value="1" />
+  <parameter name="CSEL_EN" value="false" />
+  <parameter name="CSEL" value="0" />
+  <parameter name="F2S_Width" value="2" />
+  <parameter name="S2F_Width" value="2" />
+  <parameter name="LWH2F_Enable" value="true" />
+  <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional,Avalon-MM Bidirectional</parameter>
+  <parameter name="F2SDRAM_Width" value="64,64" />
+  <parameter name="BONDING_OUT_ENABLED" value="false" />
+  <parameter name="S2FCLK_COLDRST_Enable" value="false" />
+  <parameter name="S2FCLK_PENDINGRST_Enable" value="false" />
+  <parameter name="F2SCLK_DBGRST_Enable" value="false" />
+  <parameter name="F2SCLK_WARMRST_Enable" value="false" />
+  <parameter name="F2SCLK_COLDRST_Enable" value="false" />
+  <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
+  <parameter name="F2SINTERRUPT_Enable" value="true" />
+  <parameter name="S2FINTERRUPT_CAN_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_UART_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_USB_Enable" value="false" />
+  <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
+  <parameter name="EMAC0_PinMuxing" value="Unused" />
+  <parameter name="EMAC0_Mode" value="N/A" />
+  <parameter name="EMAC1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="EMAC1_Mode" value="RGMII" />
+  <parameter name="NAND_PinMuxing" value="Unused" />
+  <parameter name="NAND_Mode" value="N/A" />
+  <parameter name="QSPI_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="QSPI_Mode" value="1 SS" />
+  <parameter name="SDIO_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="SDIO_Mode" value="4-bit Data" />
+  <parameter name="USB0_PinMuxing" value="Unused" />
+  <parameter name="USB0_Mode" value="N/A" />
+  <parameter name="USB1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="USB1_Mode" value="SDR" />
+  <parameter name="SPIM0_PinMuxing" value="FPGA" />
+  <parameter name="SPIM0_Mode" value="Full" />
+  <parameter name="SPIM1_PinMuxing" value="Unused" />
+  <parameter name="SPIM1_Mode" value="N/A" />
+  <parameter name="SPIS0_PinMuxing" value="Unused" />
+  <parameter name="SPIS0_Mode" value="N/A" />
+  <parameter name="SPIS1_PinMuxing" value="Unused" />
+  <parameter name="SPIS1_Mode" value="N/A" />
+  <parameter name="UART0_PinMuxing" value="HPS I/O Set 1" />
+  <parameter name="UART0_Mode" value="No Flow Control" />
+  <parameter name="UART1_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="UART1_Mode" value="No Flow Control" />
+  <parameter name="I2C0_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="I2C0_Mode" value="I2C" />
+  <parameter name="I2C1_PinMuxing" value="Unused" />
+  <parameter name="I2C1_Mode" value="N/A" />
+  <parameter name="I2C2_PinMuxing" value="Unused" />
+  <parameter name="I2C2_Mode" value="N/A" />
+  <parameter name="I2C3_PinMuxing" value="Unused" />
+  <parameter name="I2C3_Mode" value="N/A" />
+  <parameter name="CAN0_PinMuxing" value="Unused" />
+  <parameter name="CAN0_Mode" value="N/A" />
+  <parameter name="CAN1_PinMuxing" value="Unused" />
+  <parameter name="CAN1_Mode" value="N/A" />
+  <parameter name="TRACE_PinMuxing" value="HPS I/O Set 0" />
+  <parameter name="TRACE_Mode" value="HPS" />
+  <parameter name="GPIO_Enable">Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,Yes,No,No,No,Yes,No,Yes,No,Yes,Yes,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,Yes,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
+  <parameter name="S2FCLK_USER0CLK_Enable" value="true" />
+  <parameter name="S2FCLK_USER0CLK_FREQ" value="200" />
+  <parameter name="S2FCLK_USER1CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER1CLK_FREQ" value="100" />
+  <parameter name="S2FCLK_USER2CLK_Enable" value="false" />
+  <parameter name="S2FCLK_USER2CLK_FREQ" value="100" />
+  <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" />
+  <parameter name="F2SCLK_PERIPHCLK_FREQ" value="100" />
+  <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" />
+  <parameter name="F2SCLK_SDRAMCLK_FREQ" value="100" />
+  <parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
+  <parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
+  <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
+  <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="50000000" />
+  <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="200000000" />
+  <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
+  <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
+  <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
+  <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
+  <parameter
+     name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
+     value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDIO_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="20" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" />
+  <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" />
+  <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" />
+  <parameter name="device_name" value="5ASTFD5K3F40I3ES" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
+     value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
+  <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" />
+  <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" />
+  <parameter
+     name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
+     value="false" />
+  <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" />
+  <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" />
+ </module>
+ <module
+   kind="altera_jtag_avalon_master"
+   version="13.1"
+   enabled="1"
+   name="sys_jtag_hps_axi">
+  <parameter name="USE_PLI" value="0" />
+  <parameter name="PLI_PORT" value="50000" />
+  <parameter name="COMPONENT_CLOCK" value="0" />
+  <parameter name="FAST_VER" value="0" />
+  <parameter name="FIFO_DEPTHS" value="2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
+ </module>
+ <module
+   kind="altera_jtag_avalon_master"
+   version="13.1"
+   enabled="1"
+   name="sys_jtag_hps_sdram">
+  <parameter name="USE_PLI" value="0" />
+  <parameter name="PLI_PORT" value="50000" />
+  <parameter name="COMPONENT_CLOCK" value="0" />
+  <parameter name="FAST_VER" value="0" />
+  <parameter name="FIFO_DEPTHS" value="2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
+ </module>
+ <module
+   kind="altera_avalon_sysid_qsys"
+   version="13.1"
+   enabled="1"
+   name="sys_id">
+  <parameter name="id" value="-1395322095" />
+  <parameter name="timestamp" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_jtag_uart"
+   version="13.1"
+   enabled="1"
+   name="sys_uart">
+  <parameter name="allowMultipleConnections" value="true" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="avalonSpec" value="2.0" />
+ </module>
+ <module kind="altera_avalon_pio" version="13.1" enabled="1" name="sys_gpio">
+  <parameter name="bitClearingEdgeCapReg" value="true" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="true" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="FALLING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="EDGE" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+  <parameter name="clockRate" value="50000000" />
+ </module>
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="13.1"
+   enabled="1"
+   name="sys_int_mem">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="dataWidth" value="64" />
+  <parameter name="dualPort" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_memory2_0" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="65536" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module
+   kind="altera_jtag_avalon_master"
+   version="13.1"
+   enabled="1"
+   name="sys_jtag_pl">
+  <parameter name="USE_PLI" value="0" />
+  <parameter name="PLI_PORT" value="50000" />
+  <parameter name="COMPONENT_CLOCK" value="0" />
+  <parameter name="FAST_VER" value="0" />
+  <parameter name="FIFO_DEPTHS" value="2" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
+ </module>
+ <module kind="clock_source" version="13.1" enabled="1" name="sys_clk">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="axi_ad9250" version="1.0" enabled="1" name="axi_ad9250_0">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="14" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_0">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="14" />
+  <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="C_DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="C_2D_TRANSFER" value="1" />
+  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
+  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
+  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
+  <parameter name="C_AXI_SLICE_DEST" value="0" />
+  <parameter name="C_AXI_SLICE_SRC" value="0" />
+  <parameter name="C_SYNC_TRANSFER_START" value="0" />
+  <parameter name="C_CYCLIC" value="1" />
+  <parameter name="C_DMA_TYPE_DEST" value="0" />
+  <parameter name="C_DMA_TYPE_SRC" value="2" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
+ </module>
+ <module kind="axi_ad9250" version="1.0" enabled="1" name="axi_ad9250_1">
+  <parameter name="PCORE_ID" value="1" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="14" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac_1">
+  <parameter name="PCORE_ID" value="1" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="14" />
+  <parameter name="C_DMA_DATA_WIDTH_SRC" value="64" />
+  <parameter name="C_DMA_DATA_WIDTH_DEST" value="64" />
+  <parameter name="C_DMA_LENGTH_WIDTH" value="14" />
+  <parameter name="C_2D_TRANSFER" value="1" />
+  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
+  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
+  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
+  <parameter name="C_AXI_SLICE_DEST" value="0" />
+  <parameter name="C_AXI_SLICE_SRC" value="0" />
+  <parameter name="C_SYNC_TRANSFER_START" value="0" />
+  <parameter name="C_CYCLIC" value="1" />
+  <parameter name="C_DMA_TYPE_DEST" value="0" />
+  <parameter name="C_DMA_TYPE_SRC" value="2" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+   kind="altera_jesd204"
+   version="13.1"
+   enabled="1"
+   name="sys_jesd204b_s1">
+  <parameter name="wrapper_opt" value="base_phy" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="SUBCLASSV" value="1" />
+  <parameter name="lane_rate" value="5000" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="REFCLK_FREQ" value="250.0" />
+  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="L" value="4" />
+  <parameter name="M" value="4" />
+  <parameter name="N" value="16" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="S" value="1" />
+  <parameter name="K" value="32" />
+  <parameter name="SCR" value="1" />
+  <parameter name="CS" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="HD" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="DID" value="0" />
+  <parameter name="BID" value="0" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="AUTO_DEVICE" value="5ASTFD5K3F40I3ES" />
+ </module>
+ <module
+   kind="altera_clock_bridge"
+   version="13.1"
+   enabled="1"
+   name="sys_jesd204b_s1_ref_clk">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="250000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   kind="altera_pll"
+   version="13.1"
+   enabled="1"
+   name="sys_jesd204b_s1_pll">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="device" value="5ASTFD5K3F40I3ES" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_reference_clock_frequency" value="250.0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_use_locked" value="true" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_number_of_clocks" value="1" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="125.0" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="250000000" />
+ </module>
+ <module
+   kind="altera_clock_bridge"
+   version="13.1"
+   enabled="1"
+   name="sys_jesd204b_s1_rx_clk">
+  <parameter name="DERIVED_CLOCK_RATE" value="125000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="125000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_jtag_pl.clk" />
+ <connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_uart.clk" />
+ <connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_gpio.clk" />
+ <connection kind="clock" version="13.1" start="sys_clk.clk" end="sys_id.clk" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_pl.master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010410" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_pl.master"
+   end="sys_gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_pl.master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010418" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_pl.master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_jtag_hps_axi.clk" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jtag_pl.clk_reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_gpio.reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jtag_hps_axi.clk_reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_hps_axi.master"
+   end="sys_hps.f2h_axi_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_hps.f2h_axi_clock" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_hps.h2f_axi_clock" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_hps.h2f_lw_axi_clock" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_axi_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010418" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010410" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_hps.f2h_sdram0_clock" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_jtag_hps_sdram.clk" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jtag_hps_sdram.clk_reset" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_jtag_hps_sdram.master"
+   end="sys_hps.f2h_sdram0_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="axi_ad9250_0.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_0.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0xc000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="axi_dmac_0.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_dmac_0.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_dmac_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x8000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="axi_dmac_0.m_dest_axi"
+   end="sys_hps.f2h_sdram1_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_hps.h2f_user0_clock"
+   end="sys_hps.f2h_sdram1_clock" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_hps.h2f_user0_clock"
+   end="axi_dmac_0.m_dest_axi_clock" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_dmac_0.m_dest_axi_reset" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="axi_ad9250_1.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_ad9250_1.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_ad9250_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x4000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="axi_dmac_1.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_dmac_1.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="axi_dmac_1.m_dest_axi_reset" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="axi_dmac_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_hps.h2f_user0_clock"
+   end="axi_dmac_1.m_dest_axi_clock" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="axi_dmac_1.m_dest_axi"
+   end="sys_hps.f2h_sdram1_data">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_jesd204b_s1_ref_clk.out_clk"
+   end="sys_jesd204b_s1.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_jesd204b_s1_ref_clk.out_clk"
+   end="sys_jesd204b_s1_pll.refclk" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1_pll.reset" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_jesd204b_s1_pll.outclk0"
+   end="sys_jesd204b_s1.rxlink_clk" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1.rxlink_rst_n" />
+ <connection
+   kind="reset"
+   version="13.1"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1.jesd204_rx_avs_rst_n" />
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_clk.clk"
+   end="sys_jesd204b_s1.jesd204_rx_avs_clk" />
+ <connection
+   kind="avalon"
+   version="13.1"
+   start="sys_hps.h2f_lw_axi_master"
+   end="sys_jesd204b_s1.jesd204_rx_avs">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00010000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.1"
+   start="sys_jesd204b_s1_pll.outclk0"
+   end="sys_jesd204b_s1_rx_clk.in_clk" />
+ <connection
+   kind="interrupt"
+   version="13.1"
+   start="sys_hps.f2h_irq0"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.1"
+   start="sys_hps.f2h_irq0"
+   end="sys_gpio.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.1"
+   start="sys_hps.f2h_irq0"
+   end="axi_dmac_0.interrupt_sender">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.1"
+   start="sys_hps.f2h_irq0"
+   end="axi_dmac_1.interrupt_sender">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+</system>
diff --git a/projects/fmcjesdadc1/a5soc/system_constr.sdc b/projects/fmcjesdadc1/a5soc/system_constr.sdc
new file mode 100755
index 000000000..a0e1fe0a6
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_constr.sdc
@@ -0,0 +1,16 @@
+
+create_clock -period "20.000 ns" -name n_clk_50m [get_ports {sys_clk}]
+create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+#set clk_500m    [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_rxlink  [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
+
+set_false_path -from {sys_resetn} -to *
+#set_false_path -from $clk_50m -to $clk_rxlink
+#set_false_path -from $clk_rxlink -to $clk_50m
+
+
+
diff --git a/projects/fmcjesdadc1/a5soc/system_project.tcl b/projects/fmcjesdadc1/a5soc/system_project.tcl
new file mode 100755
index 000000000..7f0d2e61a
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_project.tcl
@@ -0,0 +1,81 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new fmcjesdadc1_a5soc -overwrite
+
+set_global_assignment -name FAMILY "Arria V"
+set_global_assignment -name DEVICE 5ASTFD5K3F40I3ES
+set_global_assignment -name TOP_LEVEL_ENTITY system_top
+set_global_assignment -name SDC_FILE system_constr.sdc
+#set_global_assignment -name QSYS_FILE system_bd.qsys
+set_global_assignment -name QIP_FILE system_bd/synthesis/system_bd.qip
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
+set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
+set_global_assignment -name VERILOG_FILE system_top.v
+
+source ../../common/a5soc/a5soc_system_assign.tcl
+#source $ad_hdl_dir/projects/common/a5soc/a5soc_system_assign.tcl
+
+# reference clock
+
+set_location_assignment PIN_AC31  -to ref_clk
+set_location_assignment PIN_AC32  -to "ref_clk(n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk
+set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk
+
+# lane data
+
+set_location_assignment PIN_AF39  -to rx_data[0]
+set_location_assignment PIN_AF38  -to "rx_data[0](n)"
+set_location_assignment PIN_AB39  -to rx_data[1]
+set_location_assignment PIN_AB38  -to "rx_data[1](n)"
+set_location_assignment PIN_Y39   -to rx_data[2]
+set_location_assignment PIN_Y38   -to "rx_data[2](n)"
+set_location_assignment PIN_T39   -to rx_data[3]
+set_location_assignment PIN_T38   -to "rx_data[3](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3]
+
+# jesd signals
+
+set_location_assignment PIN_D24   -to rx_sync
+set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sync
+
+set_location_assignment PIN_E24   -to rx_sysref
+set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sysref
+
+# spi
+
+set_location_assignment PIN_E25   -to spi_csn
+set_location_assignment PIN_D25   -to spi_clk
+set_location_assignment PIN_R24   -to spi_sdio
+
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
+
+# globals
+
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+
+#set_global_assignment -name SEARCH_PATH db/ip/system_bd
+#set_global_assignment -name SEARCH_PATH db/ip/system_bd/submodules
+#set_global_assignment -name SEARCH_PATH db/ip/system_bd/submodules/sequencer
+
+execute_flow -compile
+
diff --git a/projects/fmcjesdadc1/a5soc/system_timing.tcl b/projects/fmcjesdadc1/a5soc/system_timing.tcl
new file mode 100755
index 000000000..e1f355d44
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_timing.tcl
@@ -0,0 +1,3 @@
+
+report_timing -detail path_only -npaths 20 -file timing_impl.log
+  
diff --git a/projects/fmcjesdadc1/a5soc/system_top.v b/projects/fmcjesdadc1/a5soc/system_top.v
new file mode 100755
index 000000000..cdc7a7234
--- /dev/null
+++ b/projects/fmcjesdadc1/a5soc/system_top.v
@@ -0,0 +1,524 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+
+  // hps
+
+  ddr3_a,
+  ddr3_ba,
+  ddr3_ck_p,
+  ddr3_ck_n,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_we_n,
+  ddr3_reset_n,
+  ddr3_dq,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_odt,
+  ddr3_dm,
+  ddr3_oct_rzqin,
+  eth1_tx_clk,
+  eth1_tx_ctl,
+  eth1_txd0,
+  eth1_txd1,
+  eth1_txd2,
+  eth1_txd3,
+  eth1_rx_clk,
+  eth1_rx_ctl,
+  eth1_rxd0,
+  eth1_rxd1,
+  eth1_rxd2,
+  eth1_rxd3,
+  eth1_mdc,
+  eth1_mdio,
+  qspi_ss0,
+  qspi_clk,
+  qspi_io0,
+  qspi_io1,
+  qspi_io2,
+  qspi_io3,
+  sdio_clk,
+  sdio_cmd,
+  sdio_d0,
+  sdio_d1,
+  sdio_d2,
+  sdio_d3,
+  usb1_clk,
+  usb1_stp,
+  usb1_dir,
+  usb1_nxt,
+  usb1_d0,
+  usb1_d1,
+  usb1_d2,
+  usb1_d3,
+  usb1_d4,
+  usb1_d5,
+  usb1_d6,
+  usb1_d7,
+  uart0_rx,
+  uart0_tx,
+  uart1_rx,
+  uart1_tx,
+  i2c0_scl,
+  i2c0_sda,
+  trace_clk,
+  trace_d0,
+  trace_d1,
+  trace_d2,
+  trace_d3,
+  trace_d4,
+  trace_d5,
+  trace_d6,
+  trace_d7,
+  gpio_gpio00,
+  gpio_gpio17,
+  gpio_gpio18,
+  gpio_gpio22,
+  gpio_gpio24,
+  gpio_gpio26,
+  gpio_gpio27,
+  gpio_gpio35,
+  gpio_gpio40,
+  gpio_gpio41,
+  gpio_gpio42,
+  gpio_gpio43,
+
+  // board gpio
+
+  led,
+  push_buttons,
+  dip_switches,
+
+  // lane interface
+
+  ref_clk,
+  rx_data,
+  rx_sync,
+  rx_sysref,
+
+  // spi
+
+  spi_csn,
+  spi_clk,
+  spi_sdio);
+
+  // clock and resets
+
+  input             sys_clk;
+
+  // hps
+
+  output  [14:0]  ddr3_a;
+  output  [ 2:0]  ddr3_ba;
+  output          ddr3_ck_p;
+  output          ddr3_ck_n;
+  output          ddr3_cke;
+  output          ddr3_cs_n;
+  output          ddr3_ras_n;
+  output          ddr3_cas_n;
+  output          ddr3_we_n;
+  output          ddr3_reset_n;
+  inout   [39:0]  ddr3_dq;
+  inout   [ 4:0]  ddr3_dqs_p;
+  inout   [ 4:0]  ddr3_dqs_n;
+  output          ddr3_odt;
+  output  [ 4:0]  ddr3_dm;
+  input           ddr3_oct_rzqin;
+  output          eth1_tx_clk;
+  output          eth1_tx_ctl;
+  output          eth1_txd0;
+  output          eth1_txd1;
+  output          eth1_txd2;
+  output          eth1_txd3;
+  input           eth1_rx_clk;
+  input           eth1_rx_ctl;
+  input           eth1_rxd0;
+  input           eth1_rxd1;
+  input           eth1_rxd2;
+  input           eth1_rxd3;
+  output          eth1_mdc;
+  inout           eth1_mdio;
+  output          qspi_ss0;
+  output          qspi_clk;
+  inout           qspi_io0;
+  inout           qspi_io1;
+  inout           qspi_io2;
+  inout           qspi_io3;
+  output          sdio_clk;
+  inout           sdio_cmd;
+  inout           sdio_d0;
+  inout           sdio_d1;
+  inout           sdio_d2;
+  inout           sdio_d3;
+  input           usb1_clk;
+  output          usb1_stp;
+  input           usb1_dir;
+  input           usb1_nxt;
+  inout           usb1_d0;
+  inout           usb1_d1;
+  inout           usb1_d2;
+  inout           usb1_d3;
+  inout           usb1_d4;
+  inout           usb1_d5;
+  inout           usb1_d6;
+  inout           usb1_d7;
+  input           uart0_rx;
+  output          uart0_tx;
+  input           uart1_rx;
+  output          uart1_tx;
+  inout           i2c0_scl;
+  inout           i2c0_sda;
+  output          trace_clk;
+  output          trace_d0;
+  output          trace_d1;
+  output          trace_d2;
+  output          trace_d3;
+  output          trace_d4;
+  output          trace_d5;
+  output          trace_d6;
+  output          trace_d7;
+  inout           gpio_gpio00;
+  inout           gpio_gpio17;
+  inout           gpio_gpio18;
+  inout           gpio_gpio22;
+  inout           gpio_gpio24;
+  inout           gpio_gpio26;
+  inout           gpio_gpio27;
+  inout           gpio_gpio35;
+  inout           gpio_gpio40;
+  inout           gpio_gpio41;
+  inout           gpio_gpio42;
+  inout           gpio_gpio43;
+
+  // board gpio
+
+  output  [  3:0]   led;
+  input   [  3:0]   push_buttons;
+  input   [  3:0]   dip_switches;
+
+  // lane interface
+
+  input             ref_clk;
+  input   [  3:0]   rx_data;
+  output            rx_sync;
+  output            rx_sysref;
+
+  // spi
+
+  output            spi_csn;
+  output            spi_clk;
+  inout             spi_sdio;
+
+  // internal registers
+
+  reg               rx_sysref_m1 = 'd0;
+  reg               rx_sysref_m2 = 'd0;
+  reg               rx_sysref_m3 = 'd0;
+  reg               rx_sysref = 'd0;
+
+  // internal clocks and resets
+
+  wire              sys_resetn;
+  wire              rx_clk;
+  wire              adc0_clk;
+  wire              adc1_clk;
+
+  // internal signals
+
+  wire              sys_pll_locked_s;
+  wire              spi_csn_s;
+  wire              spi_clk_s;
+  wire              spi_mosi_s;
+  wire              spi_miso_s;
+  wire    [ 63:0]   adc0_ddata_s;
+  wire              adc0_dsync_s;
+  wire              adc0_dovf_s;
+  wire              adc0_dwr_s;
+  wire              adc0_mon_valid_s;
+  wire    [ 55:0]   adc0_mon_data_s;
+  wire    [ 63:0]   adc1_ddata_s;
+  wire              adc1_dsync_s;
+  wire              adc1_dovf_s;
+  wire              adc1_dwr_s;
+  wire              adc1_mon_valid_s;
+  wire    [ 55:0]   adc1_mon_data_s;
+  wire    [  3:0]   rx_ip_sof_s;
+  wire    [127:0]   rx_ip_data_s;
+  wire    [127:0]   rx_data_s;
+  wire              rx_sw_rstn_s;
+  wire              rx_sysref_s;
+  wire              rx_err_s;
+  wire              rx_ready_s;
+  wire    [  3:0]   rx_rst_state_s;
+  wire              rx_lane_aligned_s;
+  wire    [  3:0]   rx_analog_reset_s;
+  wire    [  3:0]   rx_digital_reset_s;
+  wire    [  3:0]   rx_cdr_locked_s;
+  wire    [  3:0]   rx_cal_busy_s;
+  wire              rx_pll_locked_s;
+  wire    [ 15:0]   rx_xcvr_status_s;
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= rx_sysref_s;
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_m3 <= rx_sysref_m2;
+    rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
+  end
+
+  sld_signaltap #(
+    .sld_advanced_trigger_entity ("basic,1,"),
+    .sld_data_bits (114),
+    .sld_data_bit_cntr_bits (8),
+    .sld_enable_advanced_trigger (0),
+    .sld_mem_address_bits (10),
+    .sld_node_crc_bits (32),
+    .sld_node_crc_hiword (10311),
+    .sld_node_crc_loword (14297),
+    .sld_node_info (1076736),
+    .sld_ram_block_type ("AUTO"),
+    .sld_sample_depth (1024),
+    .sld_storage_qualifier_gap_record (0),
+    .sld_storage_qualifier_mode ("OFF"),
+    .sld_trigger_bits (2),
+    .sld_trigger_in_enabled (0),
+    .sld_trigger_level (1),
+    .sld_trigger_level_pipeline (1))
+  i_signaltap (
+    .acq_clk (rx_clk),
+    .acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
+    .acq_trigger_in ({rx_sysref, rx_sync}));
+
+  genvar n;
+  generate
+  for (n = 0; n < 4; n = n + 1) begin: g_align_1
+  ad_jesd_align i_jesd_align (
+    .rx_clk (rx_clk),
+    .rx_sof (rx_ip_sof_s),
+    .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
+    .rx_data (rx_data_s[n*32+31:n*32]));
+  end
+  endgenerate
+
+  assign rx_xcvr_status_s[15:15] = 1'd0;
+  assign rx_xcvr_status_s[14:14] = rx_sync;
+  assign rx_xcvr_status_s[13:13] = rx_ready_s;
+  assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
+  assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
+  assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
+  assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
+
+  ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
+    .rx_clk (rx_clk),
+    .rx_rstn (sys_resetn),
+    .rx_sw_rstn (rx_sw_rstn_s),
+    .rx_pll_locked (rx_pll_locked_s),
+    .rx_cal_busy (rx_cal_busy_s),
+    .rx_cdr_locked (rx_cdr_locked_s),
+    .rx_analog_reset (rx_analog_reset_s),
+    .rx_digital_reset (rx_digital_reset_s),
+    .rx_ready (rx_ready_s),
+    .rx_rst_state (rx_rst_state_s));
+
+  fmcjesdadc1_spi i_fmcjesdadc1_spi (
+    .sys_clk (sys_clk),
+    .spi4_csn (spi_csn_s),
+    .spi4_clk (spi_clk_s),
+    .spi4_mosi (spi_mosi_s),
+    .spi4_miso (spi_miso_s),
+    .spi3_csn (spi_csn),
+    .spi3_clk (spi_clk),
+    .spi3_sdio (spi_sdio));
+
+  system_bd i_system_bd (
+    .memory_mem_a (ddr3_a),
+    .memory_mem_ba (ddr3_ba),
+    .memory_mem_ck (ddr3_ck_p),
+    .memory_mem_ck_n (ddr3_ck_n),
+    .memory_mem_cke (ddr3_cke),
+    .memory_mem_cs_n (ddr3_cs_n),
+    .memory_mem_ras_n (ddr3_ras_n),
+    .memory_mem_cas_n (ddr3_cas_n),
+    .memory_mem_we_n (ddr3_we_n),
+    .memory_mem_reset_n (ddr3_reset_n),
+    .memory_mem_dq (ddr3_dq),
+    .memory_mem_dqs (ddr3_dqs_p),
+    .memory_mem_dqs_n (ddr3_dqs_n),
+    .memory_mem_odt (ddr3_odt),
+    .memory_mem_dm (ddr3_dm),
+    .memory_oct_rzqin (ddr3_oct_rzqin),
+    .clk_clk (sys_clk),
+    .reset_reset_n (sys_resetn),
+    .axi_ad9250_0_xcvr_clk_clk (rx_clk),
+    .axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
+    .axi_ad9250_0_adc_clock_clk (adc0_clk),
+    .axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s),
+    .axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s),
+    .axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s),
+    .axi_ad9250_0_adc_dma_if_dunf (1'b0),
+    .axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s),
+    .axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s),
+    .axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s),
+    .axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
+    .axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
+    .axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s),
+    .axi_dmac_0_fifo_wr_if_data (adc0_ddata_s),
+    .axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s),
+    .axi_ad9250_1_xcvr_clk_clk (rx_clk),
+    .axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
+    .axi_ad9250_1_adc_clock_clk (adc1_clk),
+    .axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s),
+    .axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s),
+    .axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s),
+    .axi_ad9250_1_adc_dma_if_dunf (1'b0),
+    .axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s),
+    .axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s),
+    .axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s),
+    .axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
+    .axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
+    .axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s),
+    .axi_dmac_1_fifo_wr_if_data (adc1_ddata_s),
+    .axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s),
+    .sys_jesd204b_s1_ref_clk_in_clk_clk (ref_clk),
+    .sys_jesd204b_s1_rx_clk_out_clk_clk (rx_clk),
+    .sys_jesd204b_s1_jesd204_rx_link_data (rx_ip_data_s),
+    .sys_jesd204b_s1_jesd204_rx_link_valid (),
+    .sys_jesd204b_s1_jesd204_rx_link_ready (1'b1),
+    .sys_jesd204b_s1_alldev_lane_aligned_export (rx_lane_aligned_s),
+    .sys_jesd204b_s1_sysref_export (rx_sysref),
+    .sys_jesd204b_s1_jesd204_rx_frame_error_export (rx_err_s),
+    .sys_jesd204b_s1_dev_lane_aligned_export (rx_lane_aligned_s),
+    .sys_jesd204b_s1_dev_sync_n_export (rx_sync),
+    .sys_jesd204b_s1_sof_export (rx_ip_sof_s),
+    .sys_jesd204b_s1_rx_serial_data_rx_serial_data (rx_data),
+    .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
+    .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
+    .sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s),
+    .sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
+    .sys_hps_spim0_txd (spi_mosi_s),
+    .sys_hps_spim0_rxd (spi_miso_s),
+    .sys_hps_spim0_ss_in_n (1'b1),
+    .sys_hps_spim0_ssi_oe_n (),
+    .sys_hps_spim0_ss_0_n (spi_csn_s),
+    .sys_hps_spim0_ss_1_n (),
+    .sys_hps_spim0_ss_2_n (),
+    .sys_hps_spim0_ss_3_n (),
+    .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
+    .sys_hps_spim0_sclk_out_clk (spi_clk_s),
+    .sys_hps_f2h_stm_hw_events_stm_hwevents ({16'd0, led, push_buttons, dip_switches}),
+    .hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+    .hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0),
+    .hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1),
+    .hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+    .hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0),
+    .hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1),
+    .hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2),
+    .hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3),
+    .hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+    .hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+    .hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+    .hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+    .hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2),
+    .hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3),
+    .hps_io_hps_io_qspi_inst_IO0 (qspi_io0),
+    .hps_io_hps_io_qspi_inst_IO1 (qspi_io1),
+    .hps_io_hps_io_qspi_inst_IO2 (qspi_io2),
+    .hps_io_hps_io_qspi_inst_IO3 (qspi_io3),
+    .hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
+    .hps_io_hps_io_qspi_inst_CLK (qspi_clk),
+    .hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+    .hps_io_hps_io_sdio_inst_D0 (sdio_d0),
+    .hps_io_hps_io_sdio_inst_D1 (sdio_d1),
+    .hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+    .hps_io_hps_io_sdio_inst_D2 (sdio_d2),
+    .hps_io_hps_io_sdio_inst_D3 (sdio_d3),
+    .hps_io_hps_io_usb1_inst_D0 (usb1_d0),
+    .hps_io_hps_io_usb1_inst_D1 (usb1_d1),
+    .hps_io_hps_io_usb1_inst_D2 (usb1_d2),
+    .hps_io_hps_io_usb1_inst_D3 (usb1_d3),
+    .hps_io_hps_io_usb1_inst_D4 (usb1_d4),
+    .hps_io_hps_io_usb1_inst_D5 (usb1_d5),
+    .hps_io_hps_io_usb1_inst_D6 (usb1_d6),
+    .hps_io_hps_io_usb1_inst_D7 (usb1_d7),
+    .hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+    .hps_io_hps_io_usb1_inst_STP (usb1_stp),
+    .hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+    .hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+    .hps_io_hps_io_uart0_inst_RX (uart0_rx),
+    .hps_io_hps_io_uart0_inst_TX (uart0_tx),
+    .hps_io_hps_io_uart1_inst_RX (uart1_rx),
+    .hps_io_hps_io_uart1_inst_TX (uart1_tx),
+    .hps_io_hps_io_i2c0_inst_SDA (i2c0_sda),
+    .hps_io_hps_io_i2c0_inst_SCL (i2c0_scl),
+    .hps_io_hps_io_trace_inst_CLK (trace_clk),
+    .hps_io_hps_io_trace_inst_D0 (trace_d0),
+    .hps_io_hps_io_trace_inst_D1 (trace_d1),
+    .hps_io_hps_io_trace_inst_D2 (trace_d2),
+    .hps_io_hps_io_trace_inst_D3 (trace_d3),
+    .hps_io_hps_io_trace_inst_D4 (trace_d4),
+    .hps_io_hps_io_trace_inst_D5 (trace_d5),
+    .hps_io_hps_io_trace_inst_D6 (trace_d6),
+    .hps_io_hps_io_trace_inst_D7 (trace_d7),
+    .hps_io_hps_io_gpio_inst_GPIO00 (gpio_gpio00),
+    .hps_io_hps_io_gpio_inst_GPIO17 (gpio_gpio17),
+    .hps_io_hps_io_gpio_inst_GPIO18 (gpio_gpio18),
+    .hps_io_hps_io_gpio_inst_GPIO22 (gpio_gpio22),
+    .hps_io_hps_io_gpio_inst_GPIO24 (gpio_gpio24),
+    .hps_io_hps_io_gpio_inst_GPIO26 (gpio_gpio26),
+    .hps_io_hps_io_gpio_inst_GPIO27 (gpio_gpio27),
+    .hps_io_hps_io_gpio_inst_GPIO35 (gpio_gpio35),
+    .hps_io_hps_io_gpio_inst_GPIO40 (gpio_gpio40),
+    .hps_io_hps_io_gpio_inst_GPIO41 (gpio_gpio41),
+    .hps_io_hps_io_gpio_inst_GPIO42 (gpio_gpio42),
+    .hps_io_hps_io_gpio_inst_GPIO43 (gpio_gpio43),
+    .sys_hps_h2f_reset_reset_n (sys_resetn),
+    .sys_gpio_external_connection_in_port ({rx_xcvr_status_s, 4'd0, push_buttons, 4'd0, dip_switches}),
+    .sys_gpio_external_connection_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, 12'd0, led}));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************