From 99e8aa385a1f8187482d43da210db4b25f0d7db6 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Mon, 3 Jul 2017 16:54:40 +0300
Subject: [PATCH] axi_adc_trigger Streaming flag initial commit

If the streaming bit is set, after the trigger condition is met,
data will be continuosly captured by the DMA. The streaming bit
must be set to 0 to reset triggering.
---
 library/axi_adc_trigger/axi_adc_trigger.v     | 25 +++++++++++++++++--
 library/axi_adc_trigger/axi_adc_trigger_reg.v | 15 ++++++++---
 2 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v
index 4a8076b85..b8669a74b 100644
--- a/library/axi_adc_trigger/axi_adc_trigger.v
+++ b/library/axi_adc_trigger/axi_adc_trigger.v
@@ -127,6 +127,7 @@ module axi_adc_trigger(
   wire              trigger_out_a;
   wire              trigger_out_b;
   wire              trigger_out_delayed;
+  wire              streaming;
 
   reg               trigger_a_d1; // synchronization flip flop
   reg               trigger_a_d2; // synchronization flip flop
@@ -174,6 +175,8 @@ module axi_adc_trigger(
   reg     [31:0]    trigger_delay_counter;
   reg               triggered;
 
+  reg               streaming_on;
+
   // signal name changes
 
   assign up_clk = s_axi_aclk;
@@ -193,8 +196,8 @@ module axi_adc_trigger(
   assign limit_a_cmp  = {!limit_a[15],limit_a[14:0]};
   assign limit_b_cmp  = {!limit_b[15],limit_b[14:0]};
 
-  assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed, data_a_r} : {trigger_out_delayed, data_a_r};
-  assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed, data_b_r} : {trigger_out_delayed, data_b_r};
+  assign data_a_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_a_r} : {trigger_out_delayed |streaming_on, data_a_r};
+  assign data_b_trig = trigger_delay == 32'h0 ? {trigger_out_mixed | streaming_on, data_b_r} : {trigger_out_delayed |streaming_on, data_b_r};
   assign data_valid_a_trig = data_valid_a_r;
   assign data_valid_b_trig = data_valid_b_r;
 
@@ -218,6 +221,22 @@ module axi_adc_trigger(
     end
   end
 
+  always @(posedge clk) begin
+    if (trigger_delay == 0) begin
+      if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
+        streaming_on <= 1'b1;
+      end else if (streaming == 1'b0) begin
+        streaming_on <= 1'b0;
+      end
+    end else begin
+      if (streaming == 1'b1 && data_valid_a_r == 1'b1 && trigger_out_delayed == 1'b1) begin
+        streaming_on <= 1'b1;
+      end else if (streaming == 1'b0) begin
+        streaming_on <= 1'b0;
+      end
+    end
+  end
+
   always @(posedge clk) begin
     if (data_valid_a_r == 1'b1 && trigger_out_mixed == 1'b1) begin
       up_triggered_set <= 1'b1;
@@ -412,6 +431,8 @@ module axi_adc_trigger(
   .trigger_delay(trigger_delay),
   .fifo_depth(fifo_depth),
 
+  .streaming(streaming),
+
   // bus interface
 
   .up_rstn(up_rstn),
diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v
index 3d7f689ba..a319a8de6 100644
--- a/library/axi_adc_trigger/axi_adc_trigger_reg.v
+++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v
@@ -62,6 +62,7 @@ module axi_adc_trigger_reg (
   output      [ 2:0]  trigger_out_mix,
   output      [31:0]  fifo_depth,
   output      [31:0]  trigger_delay,
+  output              streaming,
 
  // bus interface
 
@@ -97,6 +98,7 @@ module axi_adc_trigger_reg (
   reg     [31:0]  up_fifo_depth = 32'h0;
   reg     [31:0]  up_trigger_delay = 32'h0;
   reg             up_triggered = 1'h0;
+  reg             up_streaming = 1'h0;
 
   assign low_level  = config_trigger[1:0];
   assign high_level = config_trigger[3:2];
@@ -123,6 +125,7 @@ module axi_adc_trigger_reg (
       up_trigger_l_mix_b <= 'd0;
       up_trigger_out_mix <= 'd0;
       up_triggered <= 1'd0;
+      up_streaming <= 1'd0;
     end else begin
       up_wack <= up_wreq;
       if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@@ -175,6 +178,9 @@ module axi_adc_trigger_reg (
       if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
         up_trigger_delay <= up_wdata;
       end
+      if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
+        up_streaming <= up_wdata[0];
+      end
     end
   end
 
@@ -205,6 +211,7 @@ module axi_adc_trigger_reg (
           5'he: up_rdata <= up_fifo_depth;
           5'hf: up_rdata <= {31'h0,up_triggered};
           5'h10: up_rdata <= up_trigger_delay;
+          5'h11: up_rdata <= {31'h0,up_streaming};
           default: up_rdata <= 0;
         endcase
       end else begin
@@ -213,10 +220,11 @@ module axi_adc_trigger_reg (
     end
   end
 
-   up_xfer_cntrl #(.DATA_WIDTH(185)) i_xfer_cntrl (
+   up_xfer_cntrl #(.DATA_WIDTH(186)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
-    .up_data_cntrl ({ up_config_trigger,    // 10
+    .up_data_cntrl ({ up_streaming,         // 1
+                      up_config_trigger,    // 10
                       up_limit_a,           // 16
                       up_function_a,        // 2
                       up_hysteresis_a,      // 32
@@ -232,7 +240,8 @@ module axi_adc_trigger_reg (
     .up_xfer_done (),
     .d_rst (1'b0),
     .d_clk (clk),
-    .d_data_cntrl ({  config_trigger,     // 10
+    .d_data_cntrl ({  streaming,          // 1
+                      config_trigger,     // 10
                       limit_a,            // 16
                       function_a,         // 2
                       hysteresis_a,       // 32