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Merge branch 'master' of https://github.com/analogdevicesinc/hdl

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ATofan 2014-04-11 18:14:08 +03:00
parent 9d19145713 c73390b6c9
commit 99ef34936f
36 changed files with 3644 additions and 400 deletions
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library/axi_ad9361/axi_ad9361_alt.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_alt (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// delay clock
delay_clk,
// dma interface
clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_dovf,
adc_dunf,
dac_drd,
dac_ddata,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awid,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bid,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arid,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rid,
s_axi_rlast,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// delay clock
input delay_clk;
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_ddata;
output adc_dsync;
input adc_dovf;
input adc_dunf;
output dac_drd;
input [63:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [ 2:0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
input [ 0:0] s_axi_awlock;
input [ 3:0] s_axi_awcache;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
input s_axi_wlast;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [ 2:0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [ 2:0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
input [ 0:0] s_axi_arlock;
input [ 3:0] s_axi_arcache;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [ 2:0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [47:0] adc_mon_data;
// defaults
assign s_axi_bid = 3'd0;
assign s_axi_rid = 3'd0;
assign s_axi_rlast = 1'd0;
// ad9361 lite version
axi_ad9361 #(
.PCORE_ID (PCORE_ID),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
i_ad9361 (
.rx_clk_in_p (rx_clk_in_p),
.rx_clk_in_n (rx_clk_in_n),
.rx_frame_in_p (rx_frame_in_p),
.rx_frame_in_n (rx_frame_in_n),
.rx_data_in_p (rx_data_in_p),
.rx_data_in_n (rx_data_in_n),
.tx_clk_out_p (tx_clk_out_p),
.tx_clk_out_n (tx_clk_out_n),
.tx_frame_out_p (tx_frame_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_data_out_n (tx_data_out_n),
.delay_clk (delay_clk),
.clk (adc_clk),
.adc_dwr (adc_dwr),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.dac_drd (dac_drd),
.dac_ddata (dac_ddata),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9361/axi_ad9361_dev_if_alt.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This interface includes both the transmit and receive components -
// They both uses the same clock (sourced from the receiving side).
`timescale 1ns/100ps
module axi_ad9361_dev_if (
// physical interface (receive)
rx_clk_in_p,
rx_clk_in_n,
rx_frame_in_p,
rx_frame_in_n,
rx_data_in_p,
rx_data_in_n,
// physical interface (transmit)
tx_clk_out_p,
tx_clk_out_n,
tx_frame_out_p,
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
// clock (common to both receive and transmit)
clk,
// receive data path interface
adc_valid,
adc_data_i1,
adc_data_q1,
adc_data_i2,
adc_data_q2,
adc_status,
adc_r1_mode,
// transmit data path interface
dac_valid,
dac_data_i1,
dac_data_q1,
dac_data_i2,
dac_data_q2,
dac_r1_mode,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// chipscope signals
dev_dbg_trigger,
dev_dbg_data);
// this parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
localparam PCORE_CYCLONEV = 0;
localparam PCORE_ARRIAV = 1;
// physical interface (receive)
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
// physical interface (transmit)
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
// clock (common to both receive and transmit)
output clk;
// receive data path interface
output adc_valid;
output [11:0] adc_data_i1;
output [11:0] adc_data_q1;
output [11:0] adc_data_i2;
output [11:0] adc_data_q2;
output adc_status;
input adc_r1_mode;
// transmit data path interface
input dac_valid;
input [11:0] dac_data_i1;
input [11:0] dac_data_q1;
input [11:0] dac_data_i2;
input [11:0] dac_data_q2;
input dac_r1_mode;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// chipscope signals
output [ 3:0] dev_dbg_trigger;
output [297:0] dev_dbg_data;
// internal registers
reg [ 5:0] rx_data_n = 'd0;
reg rx_frame_n = 'd0;
reg [11:0] rx_data = 'd0;
reg [ 1:0] rx_frame = 'd0;
reg [11:0] rx_data_d = 'd0;
reg [ 1:0] rx_frame_d = 'd0;
reg rx_error_r1 = 'd0;
reg rx_valid_r1 = 'd0;
reg [11:0] rx_data_i_r1 = 'd0;
reg [11:0] rx_data_q_r1 = 'd0;
reg rx_error_r2 = 'd0;
reg rx_valid_r2 = 'd0;
reg [11:0] rx_data_i1_r2 = 'd0;
reg [11:0] rx_data_q1_r2 = 'd0;
reg [11:0] rx_data_i2_r2 = 'd0;
reg [11:0] rx_data_q2_r2 = 'd0;
reg adc_valid = 'd0;
reg [11:0] adc_data_i1 = 'd0;
reg [11:0] adc_data_q1 = 'd0;
reg [11:0] adc_data_i2 = 'd0;
reg [11:0] adc_data_q2 = 'd0;
reg adc_status = 'd0;
reg [ 2:0] tx_data_cnt = 'd0;
reg [11:0] tx_data_i1_d = 'd0;
reg [11:0] tx_data_q1_d = 'd0;
reg [11:0] tx_data_i2_d = 'd0;
reg [11:0] tx_data_q2_d = 'd0;
reg tx_frame = 'd0;
reg [ 5:0] tx_data_p = 'd0;
reg [ 5:0] tx_data_n = 'd0;
reg [ 6:0] delay_ld = 'd0;
reg [ 4:0] delay_rdata = 'd0;
reg delay_ack_t = 'd0;
// internal signals
wire [ 3:0] rx_frame_s;
wire [ 3:0] tx_data_sel_s;
wire [ 4:0] delay_rdata_s[6:0];
wire [ 5:0] rx_data_ibuf_s;
wire [ 5:0] rx_data_idelay_s;
wire [ 5:0] rx_data_p_s;
wire [ 5:0] rx_data_n_s;
wire rx_frame_ibuf_s;
wire rx_frame_idelay_s;
wire rx_frame_p_s;
wire rx_frame_n_s;
wire [ 5:0] tx_data_oddr_s;
wire tx_frame_oddr_s;
wire tx_clk_oddr_s;
wire clk_ibuf_s;
genvar l_inst;
// device debug signals
assign dev_dbg_trigger[0] = rx_frame[0];
assign dev_dbg_trigger[1] = rx_frame[1];
assign dev_dbg_trigger[2] = tx_frame;
assign dev_dbg_trigger[3] = adc_status;
assign dev_dbg_data[ 5: 0] = tx_data_n;
assign dev_dbg_data[ 11: 6] = tx_data_p;
assign dev_dbg_data[ 23: 12] = tx_data_i1_d;
assign dev_dbg_data[ 35: 24] = tx_data_q1_d;
assign dev_dbg_data[ 47: 36] = tx_data_i2_d;
assign dev_dbg_data[ 59: 48] = tx_data_q2_d;
assign dev_dbg_data[ 63: 60] = tx_data_sel_s;
assign dev_dbg_data[ 66: 64] = tx_data_cnt;
assign dev_dbg_data[ 67: 67] = tx_frame;
assign dev_dbg_data[ 68: 68] = dac_r1_mode;
assign dev_dbg_data[ 69: 69] = dac_valid;
assign dev_dbg_data[ 81: 70] = dac_data_i1;
assign dev_dbg_data[ 93: 82] = dac_data_q1;
assign dev_dbg_data[105: 94] = dac_data_i2;
assign dev_dbg_data[117:106] = dac_data_q2;
assign dev_dbg_data[118:118] = rx_frame_p_s;
assign dev_dbg_data[119:119] = rx_frame_n_s;
assign dev_dbg_data[120:120] = rx_frame_n;
assign dev_dbg_data[122:121] = rx_frame;
assign dev_dbg_data[124:123] = rx_frame_d;
assign dev_dbg_data[128:125] = rx_frame_s;
assign dev_dbg_data[134:129] = rx_data_p_s;
assign dev_dbg_data[140:135] = rx_data_n_s;
assign dev_dbg_data[146:141] = rx_data_n;
assign dev_dbg_data[158:147] = rx_data;
assign dev_dbg_data[170:159] = rx_data_d;
assign dev_dbg_data[171:171] = rx_error_r1;
assign dev_dbg_data[172:172] = rx_valid_r1;
assign dev_dbg_data[184:173] = rx_data_i_r1;
assign dev_dbg_data[196:185] = rx_data_q_r1;
assign dev_dbg_data[197:197] = rx_error_r2;
assign dev_dbg_data[198:198] = rx_valid_r2;
assign dev_dbg_data[210:199] = rx_data_i1_r2;
assign dev_dbg_data[222:211] = rx_data_q1_r2;
assign dev_dbg_data[234:223] = rx_data_i2_r2;
assign dev_dbg_data[246:235] = rx_data_q2_r2;
assign dev_dbg_data[247:247] = adc_r1_mode;
assign dev_dbg_data[248:248] = adc_status;
assign dev_dbg_data[249:249] = adc_valid;
assign dev_dbg_data[261:250] = adc_data_i1;
assign dev_dbg_data[273:262] = adc_data_q1;
assign dev_dbg_data[285:274] = adc_data_i2;
assign dev_dbg_data[297:286] = adc_data_q2;
// receive data path interface
assign rx_frame_s = {rx_frame_d, rx_frame};
always @(posedge clk) begin
rx_data_n <= rx_data_n_s;
rx_frame_n <= rx_frame_n_s;
rx_data <= {rx_data_n, rx_data_p_s};
rx_frame <= {rx_frame_n, rx_frame_p_s};
rx_data_d <= rx_data;
rx_frame_d <= rx_frame;
end
// receive data path for single rf, frame is expected to qualify i/q msb only
always @(posedge clk) begin
rx_error_r1 <= ((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
rx_valid_r1 <= (rx_frame_s == 4'b1100) ? 1'b1 : 1'b0;
if (rx_frame_s == 4'b1100) begin
rx_data_i_r1 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q_r1 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path for dual rf, frame is expected to qualify i/q msb and lsb for rf-1 only
always @(posedge clk) begin
rx_error_r2 <= ((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)) ? 1'b0 : 1'b1;
rx_valid_r2 <= (rx_frame_s == 4'b0000) ? 1'b1 : 1'b0;
if (rx_frame_s == 4'b1111) begin
rx_data_i1_r2 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q1_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
if (rx_frame_s == 4'b0000) begin
rx_data_i2_r2 <= {rx_data_d[11:6], rx_data[11:6]};
rx_data_q2_r2 <= {rx_data_d[ 5:0], rx_data[ 5:0]};
end
end
// receive data path mux
always @(posedge clk) begin
if (adc_r1_mode == 1'b1) begin
adc_valid <= rx_valid_r1;
adc_data_i1 <= rx_data_i_r1;
adc_data_q1 <= rx_data_q_r1;
adc_data_i2 <= 12'd0;
adc_data_q2 <= 12'd0;
adc_status <= ~rx_error_r1;
end else begin
adc_valid <= rx_valid_r2;
adc_data_i1 <= rx_data_i1_r2;
adc_data_q1 <= rx_data_q1_r2;
adc_data_i2 <= rx_data_i2_r2;
adc_data_q2 <= rx_data_q2_r2;
adc_status <= ~rx_error_r2;
end
end
// transmit data path mux (reverse of what receive does above)
// the count simply selets the data muxing on the ddr outputs
assign tx_data_sel_s = {tx_data_cnt[2], dac_r1_mode, tx_data_cnt[1:0]};
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
tx_data_cnt <= 3'b100;
end else if (tx_data_cnt[2] == 1'b1) begin
tx_data_cnt <= tx_data_cnt + 1'b1;
end
if (dac_valid == 1'b1) begin
tx_data_i1_d <= dac_data_i1;
tx_data_q1_d <= dac_data_q1;
tx_data_i2_d <= dac_data_i2;
tx_data_q2_d <= dac_data_q2;
end
case (tx_data_sel_s)
4'b1111: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1110: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
4'b1101: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1100: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
4'b1011: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i2_d[ 5:0];
tx_data_n <= tx_data_q2_d[ 5:0];
end
4'b1010: begin
tx_frame <= 1'b0;
tx_data_p <= tx_data_i2_d[11:6];
tx_data_n <= tx_data_q2_d[11:6];
end
4'b1001: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[ 5:0];
tx_data_n <= tx_data_q1_d[ 5:0];
end
4'b1000: begin
tx_frame <= 1'b1;
tx_data_p <= tx_data_i1_d[11:6];
tx_data_n <= tx_data_q1_d[11:6];
end
default: begin
tx_frame <= 1'b0;
tx_data_p <= 6'd0;
tx_data_n <= 6'd0;
end
endcase
end
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'h06: delay_ld <= 7'h40;
8'h05: delay_ld <= 7'h20;
8'h04: delay_ld <= 7'h10;
8'h03: delay_ld <= 7'h08;
8'h02: delay_ld <= 7'h04;
8'h01: delay_ld <= 7'h02;
8'h00: delay_ld <= 7'h01;
default: delay_ld <= 7'h00;
endcase
end else begin
delay_ld <= 7'h00;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'h06: delay_rdata <= delay_rdata_s[6];
8'h05: delay_rdata <= delay_rdata_s[5];
8'h04: delay_rdata <= delay_rdata_s[4];
8'h03: delay_rdata <= delay_rdata_s[3];
8'h02: delay_rdata <= delay_rdata_s[2];
8'h01: delay_rdata <= delay_rdata_s[1];
8'h00: delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// delay controller
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
cyclonev_io_config ioconfiga_0
(
.clk(io_config_clk),
.datain(io_config_datain),
.dataout(),
.dutycycledelaysettings(),
.ena(io_config_clkena),
.outputenabledelaysetting(),
.outputfinedelaysetting1(),
.outputfinedelaysetting2(),
.outputhalfratebypass(),
.outputonlydelaysetting2(),
.outputonlyfinedelaysetting2(),
.outputregdelaysetting(),
.padtoinputregisterdelaysetting(wire_ioconfiga_padtoinputregisterdelaysetting[4:0]),
.padtoinputregisterfinedelaysetting(),
.readfifomode(),
.readfiforeadclockselect(),
.update(io_config_update));
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_rx_data
cyclonev_io_ibuf i_rx_data_ibuf (
.i(rx_data_in_p[l_inst]),
.ibar(rx_data_in_n[l_inst]),
.o(rx_data_ibuf_s[l_inst]),
.dynamicterminationcontrol(1'b0)
);
defparam
i_rx_data_ibuf.bus_hold = "false",
i_rx_data_ibuf.differential_mode = "true",
i_rx_data_ibuf.lpm_type = "cyclonev_io_ibuf";
cyclonev_delay_chain i_rx_data_idelay
(
.datain((rx_data_ibuf_s[l_inst]),
.dataout(rx_data_idelay_s[l_inst]),
.delayctrlin({wire_ioconfiga_padtoinputregisterdelaysetting[4:0]}));
altddio_in i_rx_data_iddr (
.datain (rx_data_idelay_s[l_inst]),
.inclock (clk),
.dataout_h (rx_data_p_s[l_inst]),
.dataout_l (rx_data_n_s[l_inst]),
.aclr (1'b0),
.aset (1'b0),
.inclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
i_rx_data_iddr.intended_device_family = "Cyclone V",
i_rx_data_iddr.invert_input_clocks = "OFF",
i_rx_data_iddr.lpm_hint = "UNUSED",
i_rx_data_iddr.lpm_type = "altddio_in",
i_rx_data_iddr.power_up_high = "OFF",
i_rx_data_iddr.width = 1;
end
end
endgenerate
// receive frame interface, ibuf -> idelay -> iddr
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
cyclonev_io_ibuf
#(
i_rx_frame_ibuf(
.i(rx_frame_in_p),
.ibar(rx_frame_in_n),
.o(rx_frame_ibuf_s[0:0]),
.dynamicterminationcontrol(1'b0)
);
defparam
i_rx_frame_ibuf.bus_hold = "false",
i_rx_frame_ibuf.differential_mode = "true",
i_rx_frame_ibuf.lpm_type = "cyclonev_io_ibuf";
cyclonev_delay_chain i_rx_frame_idelay
(
.datain(rx_frame_ibuf_s),
.dataout(rx_frame_idelay_s),
.delayctrlin({wire_ioconfiga_padtoinputregisterdelaysetting[4:0]}));
altddio_in i_rx_frame_iddr (
.datain (rx_frame_idelay_s),
.inclock (clk),
.dataout_h (rx_frame_p_s),
.dataout_l (rx_frame_n_s),
.aclr (1'b0),
.aset (1'b0),
.inclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
i_rx_frame_iddr.intended_device_family = "Cyclone V",
i_rx_frame_iddr.invert_input_clocks = "OFF",
i_rx_frame_iddr.lpm_hint = "UNUSED",
i_rx_frame_iddr.lpm_type = "altddio_in",
i_rx_frame_iddr.power_up_high = "OFF",
i_rx_frame_iddr.width = 1;
end
endgenerate
// transmit data interface, oddr -> obuf
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
for (l_inst = 0; l_inst <= 5; l_inst = l_inst + 1) begin: g_tx_data
ltddio_out i_tx_data_oddr (
.datain_h (tx_data_p[l_inst]),
.datain_l (tx_data_n[l_inst]),
.outclock (clk),
.dataout (tx_data_oddr_s[l_inst]),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
i_tx_frame_oddr.extend_oe_disable = "OFF",
i_tx_frame_oddr.intended_device_family = "Cyclone V",
i_tx_frame_oddr.invert_output = "OFF",
i_tx_frame_oddr.lpm_hint = "UNUSED",
i_tx_frame_oddr.lpm_type = "altddio_out",
i_tx_frame_oddr.oe_reg = "UNREGISTERED",
i_tx_frame_oddr.power_up_high = "OFF",
i_tx_frame_oddr.width = 1;
cyclonev_io_obuf i_tx_data_obuf
(
.i(tx_data_oddr_s[l_inst]),
.o(tx_data_out_p[l_inst]),
.obar(tx_data_out_n[l_inst]),
.oe(1'b1) ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}}) ,
.devoe(1'b1)
);
defparam
i_tx_frame_obuf.bus_hold = "false",
i_tx_frame_obuf.open_drain_output = "false",
i_tx_frame_obuf.lpm_type = "cyclonev_io_obuf";
end
end
endgenerate
// transmit frame interface, oddr -> obuf
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
cyclonev_io_obuf i_tx_frame_obuf
(
.i(tx_frame_oddr_s),
.o(tx_frame_out_p),
.obar(tx_frame_out_n),
.oe(1'b1) ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}}) ,
.devoe(1'b1)
);
defparam
i_tx_frame_obuf.bus_hold = "false",
i_tx_frame_obuf.open_drain_output = "false",
i_tx_frame_obuf.lpm_type = "cyclonev_io_obuf";
altddio_out i_tx_frame_oddr (
.datain_h (tx_frame),
.datain_l (tx_frame),
.outclock (clk),
.dataout (tx_frame_oddr_s),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
i_tx_frame_oddr.extend_oe_disable = "OFF",
i_tx_frame_oddr.intended_device_family = "Cyclone V",
i_tx_frame_oddr.invert_output = "OFF",
i_tx_frame_oddr.lpm_hint = "UNUSED",
i_tx_frame_oddr.lpm_type = "altddio_out",
i_tx_frame_oddr.oe_reg = "UNREGISTERED",
i_tx_frame_oddr.power_up_high = "OFF",
i_tx_frame_oddr.width = 1;
// transmit clock interface, oddr -> obuf
altddio_out i_tx_clk_oddr (
.datain_h (1'b1),
.datain_l (1'b1),
.outclock (clk),
.dataout (tx_clk_oddr_s),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
defparam
i_tx_frame_oddr.extend_oe_disable = "OFF",
i_tx_clk_oddr.intended_device_family = "Cyclone V",
i_tx_clk_oddr.invert_output = "OFF",
i_tx_clk_oddr.lpm_hint = "UNUSED",
i_tx_clk_oddr.lpm_type = "altddio_out",
i_tx_clk_oddr.oe_reg = "UNREGISTERED",
i_tx_clk_oddr.power_up_high = "OFF",
i_tx_clk_oddr.width = 1;
cyclonev_io_obuf i_tx_clk_obuf(
.i(tx_clk_oddr_s),
.o(tx_clk_out_p),
.obar(tx_clk_out_n),
.oe(1'b1) ,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}}) ,
.devoe(1'b1)
);
defparam
i_tx_clk_obuf.bus_hold = "false",
i_tx_clk_obuf.open_drain_output = "false",
i_tx_clk_obuf.lpm_type = "cyclonev_io_obuf";
end
endgenerate
// device clock interface (receive clock)
generate
if (PCORE_BUFTYPE == PCORE_CYCLONEV) begin
cyclonev_io_ibuf i_rx_clk_ibuf (
.i(rx_clk_in_p),
.ibar(rx_clk_in_n),
.o(clk_ibuf_s),
.dynamicterminationcontrol(1'b0)
);
cyclonev_clkena i_clk_gbuf(
.ena(1'b1),
.enaout(),
.inclk(clk_ibuf_s),
.outclk(clk));
defparam
sd1.clock_type = "Auto",
sd1.ena_register_mode = "always enabled",
sd1.lpm_type = "cyclonev_clkena";
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

156
library/axi_ad9361/axi_ad9361_hw.tcl Executable file
View File

@ -0,0 +1,156 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
set_module_property NAME axi_ad9361
set_module_property DESCRIPTION "AXI AD9361 Interface"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME axi_ad9361
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361_alt
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_drp_cntrl.v
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
#new DAC related file
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/common/ad_dcfilter.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
# other differences
add_fileset_file axi_ad9361_dev_if_alt.v VERILOG PATH axi_ad9361_dev_if_alt.v
add_fileset_file axi_ad9361_pnlb.v VERILOG PATH axi_ad9361_pnlb.v
add_fileset_file axi_ad9361_tx_dds.v VERILOG PATH axi_ad9361_tx_dds.v
add_fileset_file axi_ad9361_tx_channel.v VERILOG PATH axi_ad9361_tx_channel.v
add_fileset_file axi_ad9361_tx.v VERILOG PATH axi_ad9361_tx.v
#
add_fileset_file axi_ad9361_rx_pnmon.v VERILOG PATH axi_ad9361_rx_pnmon.v
add_fileset_file axi_ad9361_rx_channel.v VERILOG PATH axi_ad9361_rx_channel.v
add_fileset_file axi_ad9361_rx.v VERILOG PATH axi_ad9361_rx.v
add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v
add_fileset_file axi_ad9361_alt.v VERILOG PATH axi_ad9361_alt.v TOP_LEVEL_FILE
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4 end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 14
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 14
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 3
add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2
add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 3
add_interface_port s_axi s_axi_arid arid Input 3
add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 3
add_interface_port s_axi s_axi_rlast rlast Output 1
# rx interface
add_interface rx_clock clock end
add_interface_port rx_clock rx_clk_in_p clk Input 1
add_interface rx_if conduit end
set_interface_property rx_if associatedClock rx_clock
add_interface_port rx_if rx_frame_in_p rx_frame_p Input 1
add_interface_port rx_if rx_frame_in_n rx_frame_n Input 1
add_interface_port rx_if rx_data_in_p rx_data_p Input 6
add_interface_port rx_if rx_data_in_n rx_data_n Input 6
# tx interface
add_interface tx_clock clock start
add_interface_port tx_clock tx_clk_out_p clk Output 1
add_interface tx_if conduit end
set_interface_property rx_if associatedClock tx_clock
add_interface_port tx_if tx_frame_out_p tx_frame_p Output 1
add_interface_port tx_if tx_frame_out_n tx_frame_n Output 1
add_interface_port tx_if tx_data_out_p tx_data_p Output 6
add_interface_port tx_if tx_data_out_n tx_data_n Output 6
# delay clock
add_interface delay_clock clock end
add_interface_port delay_clock delay_clk clk Input 1
# dma interface
add_interface adc_clock clock start
add_interface_port adc_clock adc_clk clk Output 1
add_interface adc_dma_if conduit end
set_interface_property adc_dma_if associatedClock adc_clock
add_interface_port adc_dma_if adc_ddata ddata Output 64
add_interface_port adc_dma_if adc_dsync dsync Output 1
add_interface_port adc_dma_if adc_dovf dovf Input 1
add_interface_port adc_dma_if adc_dunf dunf Input 1
add_interface_port adc_dma_if adc_dwr dwr Output 1
# signal tap
add_interface adc_mon_if conduit end
set_interface_property adc_mon_if associatedClock adc_clock
add_interface_port adc_mon_if adc_mon_valid valid Output 1
add_interface_port adc_mon_if adc_mon_data data Output 48

1
library/axi_ad9671/axi_ad9671.v
View File

@ -377,7 +377,6 @@ module axi_ad9671 (
.drp_locked (1'd0),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd7),
.dma_bw (32'd128),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),

19
library/axi_dmac/2d_transfer.v
View File

@ -43,8 +43,8 @@ module dmac_2d_transfer (
input req_valid,
output reg req_ready,
input [31:C_ADDR_ALIGN_BITS] req_dest_address,
input [31:C_ADDR_ALIGN_BITS] req_src_address,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_x_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_y_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_dest_stride,
@ -54,18 +54,19 @@ module dmac_2d_transfer (
output reg out_req_valid,
input out_req_ready,
output [31:C_ADDR_ALIGN_BITS] out_req_dest_address,
output [31:C_ADDR_ALIGN_BITS] out_req_src_address,
output [31:C_BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:C_BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [C_DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
);
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH_SRC = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = 3;
reg [31:C_ADDR_ALIGN_BITS] dest_address;
reg [31:C_ADDR_ALIGN_BITS] src_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [C_DMA_LENGTH_WIDTH-1:0] x_length;
reg [C_DMA_LENGTH_WIDTH-1:0] y_length;
reg [C_DMA_LENGTH_WIDTH-1:0] dest_stride;
@ -125,8 +126,8 @@ begin
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_ADDR_ALIGN_BITS];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_ADDR_ALIGN_BITS];
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin

22
library/axi_dmac/address_generator.v
View File

@ -41,7 +41,7 @@ module dmac_address_generator (
input req_valid,
output reg req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
@ -64,11 +64,11 @@ module dmac_address_generator (
output [ 3:0] cache
);
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ID_WIDTH = 3;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
@ -76,12 +76,13 @@ localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
assign burst = 2'b01;
assign prot = 3'b000;
assign cache = 4'b0011;
assign len = eot ? req_last_burst_length : MAX_BEATS_PER_BURST - 1;
assign len = length;
assign size = $clog2(C_DMA_DATA_WIDTH/8);
reg [31-C_ADDR_ALIGN_BITS:0] address = 'h00;
reg [7:0] length = 'h0;
reg [31-C_BYTES_PER_BEAT_WIDTH:0] address = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {C_ADDR_ALIGN_BITS{1'b0}}};
assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}};
// If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator.
@ -96,6 +97,13 @@ always @(posedge clk) begin
end
end
always @(posedge clk) begin
if (eot == 1'b1)
length <= req_last_burst_length;
else
length <= MAX_BEATS_PER_BURST - 1;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
address <= 'h00;

52
library/axi_dmac/axi_dmac.v
View File

@ -140,8 +140,7 @@ parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 14;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_2D_TRANSFER = 1;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
@ -166,11 +165,28 @@ localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam PCORE_VERSION = 'h00040061;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = C_DMA_DATA_WIDTH_DEST > 1024 ? 8 :
C_DMA_DATA_WIDTH_DEST > 512 ? 7 :
C_DMA_DATA_WIDTH_DEST > 256 ? 6 :
C_DMA_DATA_WIDTH_DEST > 128 ? 5 :
C_DMA_DATA_WIDTH_DEST > 64 ? 4 :
C_DMA_DATA_WIDTH_DEST > 32 ? 3 :
C_DMA_DATA_WIDTH_DEST > 16 ? 2 :
C_DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 :
C_DMA_DATA_WIDTH_SRC > 512 ? 7 :
C_DMA_DATA_WIDTH_SRC > 256 ? 6 :
C_DMA_DATA_WIDTH_SRC > 128 ? 5 :
C_DMA_DATA_WIDTH_SRC > 64 ? 4 :
C_DMA_DATA_WIDTH_SRC > 32 ? 3 :
C_DMA_DATA_WIDTH_SRC > 16 ? 2 :
C_DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
// Register interface signals
reg [31:0] up_rdata = 'd0;
reg up_ack = 1'b0;
@ -206,12 +222,13 @@ reg [1:0] up_transfer_id;
reg [1:0] up_transfer_id_eot;
reg [3:0] up_transfer_done_bitmap;
reg [31:C_ADDR_ALIGN_BITS] up_dma_dest_address = 'h00;
reg [31:C_ADDR_ALIGN_BITS] up_dma_src_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00;
reg up_dma_cyclic = C_CYCLIC;
wire up_dma_sync_transfer_start = C_SYNC_TRANSFER_START ? 1'b1 : 1'b0;
// ID signals from the DMAC, just for debugging
@ -313,8 +330,9 @@ begin
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h104: up_dma_dest_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h105: up_dma_src_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h103: if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
@ -339,9 +357,9 @@ begin
12'h100: up_rdata <= {up_pause, up_enable};
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= 'h00; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h103: up_rdata <= {31'h00, up_dma_cyclic}; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00;
@ -380,22 +398,23 @@ end
wire dma_req_valid;
wire dma_req_ready;
wire [31:C_ADDR_ALIGN_BITS] dma_req_dest_address;
wire [31:C_ADDR_ALIGN_BITS] dma_req_src_address;
wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length;
wire dma_req_eot;
wire dma_req_sync_transfer_start;
wire up_req_eot;
assign up_sot = C_CYCLIC ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = C_CYCLIC ? 1'b0 : up_req_eot;
assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
generate if (C_2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS)
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
) i_2d_transfer (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
@ -437,7 +456,8 @@ dmac_request_arb #(
.C_DMA_DATA_WIDTH_SRC(C_DMA_DATA_WIDTH_SRC),
.C_DMA_DATA_WIDTH_DEST(C_DMA_DATA_WIDTH_DEST),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.C_DMA_TYPE_DEST(C_DMA_TYPE_DEST),
.C_DMA_TYPE_SRC(C_DMA_TYPE_SRC),
.C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC),

2
library/axi_dmac/axi_dmac_alt.v
View File

@ -189,7 +189,6 @@ module axi_dmac_alt (
parameter PCORE_ID = 0;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 14;
parameter C_2D_TRANSFER = 1;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
@ -361,7 +360,6 @@ module axi_dmac_alt (
.C_HIGHADDR (32'hffffffff),
.C_DMA_DATA_WIDTH_SRC (C_DMA_DATA_WIDTH_SRC),
.C_DMA_DATA_WIDTH_DEST (C_DMA_DATA_WIDTH_DEST),
.C_ADDR_ALIGN_BITS (C_ADDR_ALIGN_BITS),
.C_DMA_LENGTH_WIDTH (C_DMA_LENGTH_WIDTH),
.C_2D_TRANSFER (C_2D_TRANSFER),
.C_CLKS_ASYNC_REQ_SRC (C_CLKS_ASYNC_REQ_SRC),

22
library/axi_dmac/axi_register_slice.v
View File

@ -71,19 +71,22 @@ wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid;
reg [DATA_WIDTH-1:0] fwd_data;
reg fwd_valid = 1'b0;
reg [DATA_WIDTH-1:0] fwd_data = 'h00;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
@ -100,19 +103,22 @@ endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready;
reg [DATA_WIDTH-1:0] bwd_data;
reg bwd_ready = 1'b1;
reg [DATA_WIDTH-1:0] bwd_data = 'h00;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (bwd_ready)
bwd_data <= s_axi_data;
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)

60
library/axi_dmac/data_mover.v
View File

@ -77,16 +77,15 @@ reg [C_ID_WIDTH-1:0] id_next = 'h00;
reg pending_burst = 1'b0;
reg active = 1'b0;
reg last_eot = 1'b0;
reg last_non_eot = 1'b0;
reg [C_ID_WIDTH-1:0] request_id_d1 = 'h0;
reg eot_d1 = 1'b0;
wire last;
wire last_load;
wire last;
assign response_id = id;
assign last = beat_counter == (eot_d1 ? last_burst_length : MAX_BEATS_PER_BURST - 1);
assign last = eot ? last_eot : last_non_eot;
assign s_axi_ready = m_axi_ready & pending_burst & active;
assign m_axi_valid = s_axi_valid & pending_burst & active;
@ -95,7 +94,7 @@ assign m_axi_last = last;
// If we want to support zero delay between transfers we have to assert
// req_ready on the same cycle on which the last load happens.
assign last_load = s_axi_ready && s_axi_valid && last && eot_d1;
assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
assign req_ready = last_load || ~active;
always @(posedge clk) begin
@ -113,7 +112,7 @@ always @(posedge clk) begin
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id_d1)
if (response_id == request_id)
enabled <= 1'b0;
end
end
@ -121,46 +120,36 @@ always @(posedge clk) begin
end
always @(posedge clk) begin
eot_d1 <= eot;
request_id_d1 <= request_id;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
beat_counter <= 'h0;
end else begin
if (req_ready && req_valid) begin
beat_counter <= 'h0;
end else if (s_axi_ready && s_axi_valid) begin
beat_counter <= beat_counter + 1'b1;
end
if (req_ready) begin
last_eot <= req_last_burst_length == 'h0;
last_non_eot <= 1'b0;
beat_counter <= 'h1;
end else if (s_axi_ready && s_axi_valid) begin
last_eot <= beat_counter == last_burst_length;
last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
beat_counter <= beat_counter + 1;
end
end
always @(posedge clk) begin
if (req_ready && req_valid) begin
if (req_ready)
last_burst_length <= req_last_burst_length;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
if (enabled == 1'b0 || resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid) begin
active <= 1'b1;
end else if (last_load) begin
active <= 1'b0;
end else begin
if (~enabled) begin
active <= 1'b0;
end else if (req_ready && req_valid) begin
active <= 1'b1;
end else if (last_load) begin
active <= 1'b0;
end
end
end
always @(*)
begin
if ((s_axi_ready && s_axi_valid && last) ||
(sync_id && id != request_id))
(sync_id && pending_burst))
id_next <= inc_id(id);
else
id_next <= id;
@ -169,12 +158,13 @@ end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
pending_burst <= 1'b0;
end else begin
id <= id_next;
pending_burst <= id_next != request_id_d1;
end
end
always @(posedge clk) begin
pending_burst <= id_next != request_id;
end
endmodule

9
library/axi_dmac/dest_axi_mm.v
View File

@ -42,7 +42,7 @@ module dmac_dest_mm_axi (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [C_BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
@ -95,9 +95,8 @@ module dmac_dest_mm_axi (
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
reg [(C_DMA_DATA_WIDTH/8)-1:0] wstrb;
@ -132,8 +131,8 @@ splitter #(
dmac_address_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
@ -198,7 +197,7 @@ begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= 8'b11111111;
wstrb <= {(C_DMA_DATA_WIDTH/8){1'b1}};
end
end

40
library/axi_dmac/request_arb.v
View File

@ -42,8 +42,8 @@ module dmac_request_arb (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_dest_address,
input [31:C_ADDR_ALIGN_BITS] req_src_address,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_length,
input req_sync_transfer_start,
@ -137,7 +137,9 @@ module dmac_request_arb (
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8);
parameter C_BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8);
parameter C_DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO;
@ -158,7 +160,8 @@ localparam DMA_TYPE_MM_AXI = 0;
localparam DMA_TYPE_STREAM_AXI = 1;
localparam DMA_TYPE_FIFO = 2;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
localparam DMA_ADDR_WIDTH_DEST = 32 - C_BYTES_PER_BEAT_WIDTH_DEST;
localparam DMA_ADDR_WIDTH_SRC = 32 - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ?
C_DMA_DATA_WIDTH_DEST : C_DMA_DATA_WIDTH_SRC;
@ -169,10 +172,8 @@ localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ?
// differ, so beats per burst may also differ
parameter BYTES_PER_BURST_WIDTH = $clog2(C_MAX_BYTES_PER_BURST);
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8);
parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8);
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_DEST;
localparam BURSTS_PER_TRANSFER_WIDTH = C_DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
@ -211,9 +212,9 @@ wire dest_clk;
wire dest_resetn;
wire dest_req_valid;
wire dest_req_ready;
wire [DMA_ADDR_WIDTH-1:0] dest_req_address;
wire [DMA_ADDR_WIDTH_DEST-1:0] dest_req_address;
wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length;
wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire [C_BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire dest_response_valid;
wire dest_response_ready;
@ -238,7 +239,7 @@ wire src_clk;
wire src_resetn;
wire src_req_valid;
wire src_req_ready;
wire [DMA_ADDR_WIDTH-1:0] src_req_address;
wire [DMA_ADDR_WIDTH_SRC-1:0] src_req_address;
wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
wire src_req_sync_transfer_start;
@ -378,9 +379,8 @@ assign dbg_dest_data_id = dest_data_id;
dmac_dest_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_DEST)
) i_dest_dma_mm (
.m_axi_aclk(m_dest_axi_aclk),
.m_axi_aresetn(m_dest_axi_aresetn),
@ -586,8 +586,8 @@ assign dbg_src_data_id = src_data_id;
dmac_src_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_SRC)
) i_src_dma_mm (
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(m_src_axi_aresetn),
@ -901,7 +901,7 @@ splitter #(
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST),
.C_DATA_WIDTH(DMA_ADDR_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + C_BYTES_PER_BEAT_WIDTH_DEST),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_dest_req_fifo (
@ -912,8 +912,8 @@ axi_fifo #(
.s_axis_empty(req_dest_empty),
.s_axis_data({
req_dest_address,
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0]
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST],
req_length[C_BYTES_PER_BEAT_WIDTH_DEST-1:0]
}),
.m_axis_aclk(dest_clk),
.m_axis_aresetn(dest_resetn),
@ -927,7 +927,7 @@ axi_fifo #(
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + BEATS_PER_BURST_WIDTH_SRC + 1),
.C_DATA_WIDTH(DMA_ADDR_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_src_req_fifo (
@ -938,7 +938,7 @@ axi_fifo #(
.s_axis_empty(req_src_empty),
.s_axis_data({
req_src_address,
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC],
req_sync_transfer_start
}),
.m_axis_aclk(src_clk),

6
library/axi_dmac/src_axi_mm.v
View File

@ -42,7 +42,7 @@ module dmac_src_mm_axi (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
@ -86,7 +86,7 @@ module dmac_src_mm_axi (
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
`include "resp.h"
@ -122,9 +122,9 @@ splitter #(
);
dmac_address_generator #(
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_ID_WIDTH(C_ID_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),

10
library/axi_dmac/src_fifo_inf.v
View File

@ -90,6 +90,14 @@ begin
end
end
always @(posedge clk)
begin
if (en) begin
buffer <= din;
buffer_sync <= sync;
end
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
@ -98,8 +106,6 @@ begin
end else begin
if (enable) begin
if (en) begin
buffer <= din;
buffer_sync <= sync;
valid <= 1'b1;
end else if (ready) begin
valid <= 1'b0;

8
library/axi_fifo/axi_fifo.v
View File

@ -88,13 +88,17 @@ assign m_axis_valid = m_axis_raddr != m_axis_waddr;
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
assign s_axis_empty = s_axis_raddr == s_axis_waddr;
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
ram <= s_axis_data;
end
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
ram <= s_axis_data;
end
end
end
@ -179,7 +183,7 @@ always @(posedge m_axis_aclk) begin
end
always @(posedge m_axis_aclk) begin
if ((~valid || m_axis_ready) && _m_axis_valid)
if (~valid || m_axis_ready)
data <= ram[m_axis_raddr];
end

106
library/common/altera/ad_dcfilter_alt.v Executable file
View File

@ -0,0 +1,106 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter (
// data interface
clk,
valid,
data,
valid_out,
data_out,
// control interface
dcfilt_enb,
dcfilt_coeff,
dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
// internal registers
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// cancelling the dc offset
always @(posedge clk) begin
dc_offset <= 16'h0;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d - dc_offset;
if (dcfilt_enb == 1'b1) begin
valid_out <= valid_2d;
data_out <= data_d; // DC filter not implemented in this version
end else begin
valid_out <= valid_d;
data_out <= data_d;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

112
library/common/altera/ad_mul_u16_alt.v Executable file
View File

@ -0,0 +1,112 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
lpm_mult i_mult_macro (
.clock (clk),
.dataa (data_a),
.datab (data_b),
.result (data_p),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ***************************************************************************
// ***************************************************************************

2
library/common/up_xfer_cntrl.v
View File

@ -107,7 +107,7 @@ module up_xfer_cntrl (
d_xfer_toggle_m1 <= 'd0;
d_xfer_toggle_m2 <= 'd0;
d_xfer_toggle_m3 <= 'd0;
d_data_cntrl <= 'd0;;
d_data_cntrl <= 'd0;
end else begin
d_xfer_toggle_m1 <= up_xfer_toggle;
d_xfer_toggle_m2 <= d_xfer_toggle_m1;

49
library/util_rfifo/util_rfifo.v
View File

@ -42,11 +42,12 @@
module util_rfifo (
rstn,
clk,
m_clk,
m_rd,
m_rdata,
m_runf,
s_clk,
s_rd,
s_rdata,
s_runf,
@ -64,18 +65,18 @@ module util_rfifo (
parameter M_DATA_WIDTH = 32;
parameter S_DATA_WIDTH = 64;
parameter READ_SELECT = 1;
// common clock
input rstn;
input clk;
// master/slave write
input m_clk;
input m_rd;
output [M_DATA_WIDTH-1:0] m_rdata;
output m_runf;
input s_clk;
output s_rd;
input [S_DATA_WIDTH-1:0] s_rdata;
input s_runf;
@ -93,25 +94,28 @@ module util_rfifo (
// internal registers
reg fifo_rst = 'd0;
reg [READ_SELECT-1:0] s_rd_cnt = 'd0;
reg s_rd = 'd0;
reg fifo_wr = 'd0;
reg m_runf_m1 = 'd0;
reg m_runf_m2 = 'd0;
reg m_runf = 'd0;
// internal signals
wire m_runf_s;
// defaults
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
fifo_rst <= 1'b1;
end else begin
fifo_rst <= 1'b0;
end
assign fifo_rst = ~rstn;
// independent clocks and buswidths- simply expect
// user to set a reasonable threshold on the full signal
always @(posedge s_clk) begin
s_rd <= ~fifo_wfull;
fifo_wr <= ~fifo_wfull;
end
// write depends on bus width change
assign s_rd = s_rd_cnt[READ_SELECT-1];
assign fifo_wr = s_rd_cnt[READ_SELECT-1];
genvar s;
generate
for (s = 0; s < S_DATA_WIDTH; s = s + 1) begin: g_wdata
@ -119,18 +123,15 @@ module util_rfifo (
end
endgenerate
always @(posedge clk) begin
if (m_rd == 1'b1) begin
s_rd_cnt <= s_rd_cnt + 1'b1;
end
end
// read is non-destructive
assign fifo_rd = m_rd;
assign m_runf_s = s_runf | fifo_runf | fifo_rempty;
always @(posedge clk) begin
m_runf <= s_runf | fifo_wfull | fifo_runf | fifo_rempty;
always @(posedge m_clk) begin
m_runf_m1 <= m_runf_s;
m_runf_m2 <= m_runf_m1;
m_runf <= m_runf_m2;
end
genvar m;

32
library/util_wfifo/util_wfifo.v
View File

@ -42,11 +42,12 @@
module util_wfifo (
rstn,
clk,
m_clk,
m_wr,
m_wdata,
m_wovf,
s_clk,
s_wr,
s_wdata,
s_wovf,
@ -68,13 +69,14 @@ module util_wfifo (
// common clock
input rstn;
input clk;
// master/slave write
input m_clk;
input m_wr;
input [M_DATA_WIDTH-1:0] m_wdata;
output m_wovf;
input s_clk;
output s_wr;
output [S_DATA_WIDTH-1:0] s_wdata;
input s_wovf;
@ -92,23 +94,23 @@ module util_wfifo (
// internal registers
reg fifo_rst = 'd0;
reg m_wovf_m1 = 'd0;
reg m_wovf_m2 = 'd0;
reg m_wovf = 'd0;
reg s_wr = 'd0;
// internal signals
wire m_wovf_s;
// defaults
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
fifo_rst <= 1'b1;
end else begin
fifo_rst <= 1'b0;
end
end
assign fifo_rst = ~rstn;
// write is pass through (fifo can never become full nor overflow)
// write is pass through
assign fifo_wr = m_wr;
assign m_wovf_s = s_wovf | fifo_wfull | fifo_wovf;
genvar m;
generate
@ -117,15 +119,17 @@ module util_wfifo (
end
endgenerate
always @(posedge clk) begin
m_wovf <= s_wovf | fifo_wfull | fifo_wovf;
always @(posedge m_clk) begin
m_wovf_m1 <= m_wovf_s;
m_wovf_m2 <= m_wovf_m1;
m_wovf <= m_wovf_m2;
end
// read is non-destructive
assign fifo_rd = ~fifo_rempty;
always @(posedge clk) begin
always @(posedge s_clk) begin
s_wr <= fifo_rd;
end

4
projects/fmcomms1/ac701/system_bd.tcl Normal file
View File

@ -0,0 +1,4 @@
source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
source ../common/fmcomms1_bd.tcl

171
projects/fmcomms1/ac701/system_constr.xdc Normal file
View File

@ -0,0 +1,171 @@
# reference
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_p]
set_property DIFF_TERM TRUE [get_ports ref_clk_out_p]
set_property PACKAGE_PIN J21 [get_ports ref_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_out_n]
set_property DIFF_TERM TRUE [get_ports ref_clk_out_n]
# dac
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_p]
set_property DIFF_TERM TRUE [get_ports dac_clk_in_p]
set_property PACKAGE_PIN C19 [get_ports dac_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_in_n]
set_property DIFF_TERM TRUE [get_ports dac_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_p]
set_property PACKAGE_PIN H19 [get_ports dac_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_clk_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_p]
set_property PACKAGE_PIN A19 [get_ports dac_frame_out_n]
set_property IOSTANDARD LVDS_25 [get_ports dac_frame_out_n]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[0]}]
set_property PACKAGE_PIN G26 [get_ports {dac_data_out_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[1]}]
set_property PACKAGE_PIN F25 [get_ports {dac_data_out_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[2]}]
set_property PACKAGE_PIN D25 [get_ports {dac_data_out_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[3]}]
set_property PACKAGE_PIN K23 [get_ports {dac_data_out_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[4]}]
set_property PACKAGE_PIN D26 [get_ports {dac_data_out_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[5]}]
set_property PACKAGE_PIN F24 [get_ports {dac_data_out_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[6]}]
set_property PACKAGE_PIN H18 [get_ports {dac_data_out_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[7]}]
set_property PACKAGE_PIN F22 [get_ports {dac_data_out_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[8]}]
set_property PACKAGE_PIN L18 [get_ports {dac_data_out_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[9]}]
set_property PACKAGE_PIN E23 [get_ports {dac_data_out_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[10]}]
set_property PACKAGE_PIN H24 [get_ports {dac_data_out_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[11]}]
set_property PACKAGE_PIN J20 [get_ports {dac_data_out_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[12]}]
set_property PACKAGE_PIN L14 [get_ports {dac_data_out_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[13]}]
set_property PACKAGE_PIN M17 [get_ports {dac_data_out_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[14]}]
set_property PACKAGE_PIN A22 [get_ports {dac_data_out_n[14]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[14]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_p[15]}]
set_property PACKAGE_PIN D21 [get_ports {dac_data_out_n[15]}]
set_property IOSTANDARD LVDS_25 [get_ports {dac_data_out_n[15]}]
# adc
set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_p]
set_property DIFF_TERM TRUE [get_ports adc_clk_in_p]
set_property PACKAGE_PIN H22 [get_ports adc_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_clk_in_n]
set_property DIFF_TERM TRUE [get_ports adc_clk_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_p]
set_property DIFF_TERM TRUE [get_ports adc_or_in_p]
set_property PACKAGE_PIN C18 [get_ports adc_or_in_n]
set_property IOSTANDARD LVDS_25 [get_ports adc_or_in_n]
set_property DIFF_TERM TRUE [get_ports adc_or_in_n]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[0]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[0]}]
set_property PACKAGE_PIN G21 [get_ports {adc_data_in_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[0]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[1]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[1]}]
set_property PACKAGE_PIN B21 [get_ports {adc_data_in_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[1]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[2]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[2]}]
set_property PACKAGE_PIN A20 [get_ports {adc_data_in_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[2]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[3]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[3]}]
set_property PACKAGE_PIN F17 [get_ports {adc_data_in_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[3]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[4]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[4]}]
set_property PACKAGE_PIN F15 [get_ports {adc_data_in_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[4]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[5]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[5]}]
set_property PACKAGE_PIN A18 [get_ports {adc_data_in_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[5]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[6]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[6]}]
set_property PACKAGE_PIN D20 [get_ports {adc_data_in_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[6]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[7]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[7]}]
set_property PACKAGE_PIN G16 [get_ports {adc_data_in_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[7]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[8]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[8]}]
set_property PACKAGE_PIN H15 [get_ports {adc_data_in_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[8]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[9]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[9]}]
set_property PACKAGE_PIN F19 [get_ports {adc_data_in_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[9]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[10]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[10]}]
set_property PACKAGE_PIN D16 [get_ports {adc_data_in_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[10]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[11]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[11]}]
set_property PACKAGE_PIN B17 [get_ports {adc_data_in_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[11]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[12]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[12]}]
set_property PACKAGE_PIN F20 [get_ports {adc_data_in_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[12]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_p[13]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_p[13]}]
set_property PACKAGE_PIN E18 [get_ports {adc_data_in_n[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_data_in_n[13]}]
set_property DIFF_TERM TRUE [get_ports {adc_data_in_n[13]}]
# clocks
create_clock -period 2.000 -name dac_clk_in [get_ports dac_clk_in_p]
create_clock -period 4.000 -name adc_clk_in [get_ports adc_clk_in_p]
create_clock -period 8.000 -name dac_div_clk [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
create_clock -period 4.000 -name adc_clk [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
create_clock -period 33.33 -name ref_clk [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out2]
create_clock -period 8.000 -name ila_clk [get_pins i_system_wrapper/system_i/ila_clkgen/clk_out1]
set_clock_groups -asynchronous -group dac_div_clk
set_clock_groups -asynchronous -group adc_clk
set_clock_groups -asynchronous -group ref_clk
set_clock_groups -asynchronous -group ila_clk

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projects/fmcomms1/ac701/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms1_ac701
adi_project_files fmcomms1_ac701 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
adi_project_run fmcomms1_ac701

274
projects/fmcomms1/ac701/system_top.v Normal file
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@ -0,0 +1,274 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
phy_reset_n,
phy_mdc,
phy_mdio,
phy_tx_clk,
phy_tx_ctrl,
phy_tx_data,
phy_rx_clk,
phy_rx_ctrl,
phy_rx_data,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
output phy_reset_n;
output phy_mdc;
inout phy_mdio;
output phy_tx_clk;
output phy_tx_ctrl;
output [ 3:0] phy_tx_data;
input phy_rx_clk;
input phy_rx_ctrl;
input [ 3:0] phy_rx_data;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [ 3:0] gpio_led;
inout [ 8:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
wire ref_clk;
wire oddr_ref_clk;
// assignments
assign mgt_clk_sel = 2'd0;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_io (gpio_lcd),
.gpio_led_tri_io (gpio_led),
.gpio_sw_tri_io (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.ref_clk (ref_clk),
.mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),
.phy_rst_n (phy_reset_n),
.rgmii_rd (phy_rx_data),
.rgmii_rx_ctl (phy_rx_ctrl),
.rgmii_rxc (phy_rx_clk),
.rgmii_td (phy_tx_data),
.rgmii_tx_ctl (phy_tx_ctrl),
.rgmii_txc (phy_tx_clk),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.unc_int0 (1'b0),
.unc_int1 (1'b0),
.unc_int4 (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

2
projects/fmcomms1/common/fmcomms1_bd.tcl
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@ -32,7 +32,6 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
if {$sys_zynq == 1} {
@ -61,7 +60,6 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
if {$sys_zynq == 1} {

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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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# reference
set_property -dict {PACKAGE_PIN U37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN U38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN AF39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AF40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN Y42 IOSTANDARD LVDS} [get_ports dac_frame_out_p] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AA42 IOSTANDARD LVDS} [get_ports dac_frame_out_n] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS} [get_ports dac_data_out_p[0]] ; ## FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN P38 IOSTANDARD LVDS} [get_ports dac_data_out_n[0]] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVDS} [get_ports dac_data_out_p[1]] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN R37 IOSTANDARD LVDS} [get_ports dac_data_out_n[1]] ; ## FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN T32 IOSTANDARD LVDS} [get_ports dac_data_out_p[2]] ; ## FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN R32 IOSTANDARD LVDS} [get_ports dac_data_out_n[2]] ; ## FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN V35 IOSTANDARD LVDS} [get_ports dac_data_out_p[3]] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN V36 IOSTANDARD LVDS} [get_ports dac_data_out_n[3]] ; ## FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN V39 IOSTANDARD LVDS} [get_ports dac_data_out_p[4]] ; ## FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN V40 IOSTANDARD LVDS} [get_ports dac_data_out_n[4]] ; ## FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN W36 IOSTANDARD LVDS} [get_ports dac_data_out_p[5]] ; ## FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN W37 IOSTANDARD LVDS} [get_ports dac_data_out_n[5]] ; ## FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN U34 IOSTANDARD LVDS} [get_ports dac_data_out_p[6]] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVDS} [get_ports dac_data_out_n[6]] ; ## FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN R33 IOSTANDARD LVDS} [get_ports dac_data_out_p[7]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVDS} [get_ports dac_data_out_n[7]] ; ## FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVDS} [get_ports dac_data_out_p[8]] ; ## FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN W33 IOSTANDARD LVDS} [get_ports dac_data_out_n[8]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN P32 IOSTANDARD LVDS} [get_ports dac_data_out_p[9]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN P33 IOSTANDARD LVDS} [get_ports dac_data_out_n[9]] ; ## FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVDS} [get_ports dac_data_out_p[10]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVDS} [get_ports dac_data_out_n[10]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN R38 IOSTANDARD LVDS} [get_ports dac_data_out_p[11]] ; ## FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN R39 IOSTANDARD LVDS} [get_ports dac_data_out_n[11]] ; ## FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN U32 IOSTANDARD LVDS} [get_ports dac_data_out_p[12]] ; ## FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVDS} [get_ports dac_data_out_n[12]] ; ## FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS} [get_ports dac_data_out_p[13]] ; ## FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS} [get_ports dac_data_out_n[13]] ; ## FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AC38 IOSTANDARD LVDS} [get_ports dac_data_out_p[14]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AC39 IOSTANDARD LVDS} [get_ports dac_data_out_n[14]] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AJ40 IOSTANDARD LVDS} [get_ports dac_data_out_p[15]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AJ41 IOSTANDARD LVDS} [get_ports dac_data_out_n[15]] ; ## FMC_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN U39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN T39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AD40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AD41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN U36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN T37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AB38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AB39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN W40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN Y40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AJ42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AK42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AF42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AG42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AB42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN Y39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AA39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AC40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AC41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AK39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AL39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AL41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AL42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AJ38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AK38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AD42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AE42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AD38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
create_clock -name ref_clk -period 33.33 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out2]
create_clock -name ila_clk -period 8.00 [get_pins i_system_wrapper/system_i/ila_clkgen/clk_out1]
set_clock_groups -asynchronous -group {dac_div_clk}
set_clock_groups -asynchronous -group {adc_clk}
set_clock_groups -asynchronous -group {ref_clk}
set_clock_groups -asynchronous -group {ila_clk}

15
projects/fmcomms1/vc707/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms1_vc707
adi_project_files fmcomms1_vc707 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
adi_project_run fmcomms1_vc707

273
projects/fmcomms1/vc707/system_top.v Normal file
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@ -0,0 +1,273 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [ 6:0] gpio_lcd;
output [ 7:0] gpio_led;
input [12:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [35:0] hdmi_data;
output spdif;
wire ref_clk;
wire oddr_ref_clk;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_o (gpio_lcd),
.gpio_led_tri_o (gpio_led),
.gpio_sw_tri_i (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.ref_clk (ref_clk),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.unc_int0 (1'b0),
.unc_int1 (1'b0),
.unc_int4 (1'b0));
endmodule
// ***************************************************************************
// ***************************************************************************

470
projects/scripts/adi_board.tcl
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@ -3,167 +3,175 @@
#----------------------------------------------------------------------------
# ensure that in case of a port number less than 10, the number format to be 0X
proc set_num {number} {
# usage: get_numstr 2
proc get_numstr {number} {
if { $number < 10} {
return "0${number}"
} else {
return $number
}
}
# search the first free HP port in case of a Zynq device
proc free_hp_port { sys_ps7 } {
set hp_port_num 0
set hp_port 1
while { $hp_port == 1 } {
set hp_port_num [expr $hp_port_num + 1]
set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" $sys_ps7]
}
return $hp_port_num
}
#----------------------------------------------------------------------------
#------------------------------------------------------------------------------
# Integration processes
#----------------------------------------------------------------------------
# For AXI_LITE interconnect connections
proc adi_interconnect_lite { peripheral_name peripheral_address } {
#------------------------------------------------------------------------------
# usage : adi_interconnect_lite axi_ad9467
#------------------------------------------------------------------------------
proc adi_interconnect_lite { p_name } {
set peripheral_port_name "s_axi"
set peripheral_base_name "axi_lite"
set peripheral_address_range 0x00010000
set interconnect_bd [get_bd_cells axi_cpu_interconnect]
set axi_cpu_interconnect [get_bd_cells axi_cpu_interconnect]
# increment the number of the master ports of the interconnect
set number_of_master [get_property CONFIG.NUM_MI $interconnect_bd]
set number_of_master [expr $number_of_master + 1]
set_property CONFIG.NUM_MI $number_of_master $interconnect_bd
set p_port [get_property CONFIG.NUM_MI $axi_cpu_interconnect]
set i_count [expr $p_port + 1]
set i_str [get_numstr $p_port]
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
set p_seg_fields [split $p_seg "/"]
lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
# connect clk and reset for the peripheral port
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${peripheral_name}/s_axi_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
} else {
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
set_property CONFIG.NUM_MI $i_count [get_bd_cells axi_cpu_interconnect]
# connect clk and reset for the peripheral port
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${peripheral_name}/s_axi_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
}
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "$axi_cpu_interconnect/M${i_str}_ACLK"] \
[get_bd_pins "${p_name}/s_axi_aclk"] \
$::sys_100m_clk_source
# if peripheral is a Xilinx core
if { [regexp "^analog*" [get_property VLNV [get_bd_cells $peripheral_name]]] == 0 } {
set peripheral_base_name "Reg"
if { [regexp "^xilinx.*spi*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
set peripheral_port_name "axi_lite"
} elseif { [regexp "^xilinx.*dma*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
set peripheral_port_name "S_AXI_LITE"
} else {
set peripheral_port_name "s_axi"
}
}
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${axi_cpu_interconnect}/M${i_str}_ARESETN"] \
[get_bd_pins "${p_name}/s_axi_aresetn"] \
$::sys_100m_resetn_source
# make the interface connection
connect_bd_intf_net -intf_net "${p_name}axi_lite" \
[get_bd_intf_pins "${axi_cpu_interconnect}/M${i_str}_AXI"] \
[get_bd_intf_pins "${p_seg_name}/${p_seg_intf}"]
# make the port connection
connect_bd_intf_net -intf_net "axi_cpu_interconnect_m${number_of_master}" \
[get_bd_intf_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_AXI"] \
[get_bd_intf_pins "${peripheral_name}/${peripheral_port_name}"]
# define address space for the peripheral
create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address \
$::sys_addr_cntrl_space \
[get_bd_addr_segs "${peripheral_name}/${peripheral_port_name}/${peripheral_base_name}"] \
"SEG_data_${peripheral_name}_axi_lite"
}
# Set up the SPI core
proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
#------------------------------------------------------------------------------
# usage: adi_assign_base_address 0x74a00000 axi_ad9467
#------------------------------------------------------------------------------
proc adi_assign_base_address {p_addr p_name} {
set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
set p_seg [lsearch -inline -regexp $p_seg (?i)/.*s_axi\/|axi_lite.*/]
set p_seg_fields [split $p_seg "/"]
lassign $p_seg_fields no_use p_seg_name p_seg_intf p_seg_base
set p_seg_range [get_property range $p_seg]
create_bd_addr_seg -range $p_seg_range \
-offset $p_addr $::sys_addr_cntrl_space \
$p_seg "SEG_data_${p_name}"
}
#------------------------------------------------------------------------------
# usage : adi_add_interrupt axi_ad9467_dma/irq
#------------------------------------------------------------------------------
proc adi_add_interrupt { intr_port } {
if { [get_bd_ports unc_int2] != {} } {
delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2]
connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins $intr_port]
} elseif { [get_bd_ports unc_int3] != {} } {
delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3]
connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins $intr_port]
} else {
set p_intr [get_property CONFIG.NUM_PORTS [get_bd_cells sys_concat_intc]]
set i_intr [expr $p_intr + 1]
set_property CONFIG.NUM_PORTS $i_intr [get_bd_cells sys_concat_intc]
connect_bd_net -net "sys_concat_intc_din_${i_intr}" \
[get_bd_pins "sys_concat_intc/In${i_intr}"] \
[get_bd_pins $intr_port]
}
# incrase the auxiliary concat last input port
if { $::sys_zynq == 0 } {
set p_aux_intr [get_property CONFIG.IN9_WIDTH [get_bd_cells sys_concat_aux_intc]]
set i_aux_intr [expr $p_aux_intr + 1]
set_property CONFIG.IN9_WIDTH $i_aux_intr [get_bd_cells sys_concat_aux_intc]
}
}
#------------------------------------------------------------------------------
# usage : adi_spi_core 0x41600000 2 ad9467_spi
#------------------------------------------------------------------------------
proc adi_spi_core { spi_addr spi_ss spi_name } {
# define SPI ports
set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
create_bd_port -dir I "${spi_name}_sclk_i"
create_bd_port -dir O "${spi_name}_sclk_o"
create_bd_port -dir I "${spi_name}_mosi_i"
create_bd_port -dir O "${spi_name}_mosi_o"
create_bd_port -dir I "${spi_name}_miso_i"
create_bd_port -dir I "${spi_name}_csn_i"
create_bd_port -dir O -from [expr $spi_ss - 1] -to 0 "${spi_name}_csn_o"
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
set sys_ps7 [get_bd_cells sys_ps7]
# add SPI interface to ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells sys_ps7]
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] [get_bd_cells sys_ps7]
set i 0
while { $i < $spi_ss_width } {
if { $i == 0 } {
set ps7_cs "sys_ps7/SPI0_SS_O"
} else {
set ps7_cs "sys_ps7/SPI0_SS${i}_O"
}
switch $i {
0
{ set spi_csn0_o [create_bd_port -dir O spi_csn0_o]
connect_bd_net -net "spi_csn${i}" \
[get_bd_pins $ps7_cs] \
[get_bd_ports spi_csn0_o]
}
1
{ set spi_csn1_o [create_bd_port -dir O spi_csn1_o]
connect_bd_net -net "spi_csn${i}" \
[get_bd_pins $ps7_cs] \
[get_bd_ports spi_csn1_o]
}
2
{ set spi_csn2_o [create_bd_port -dir O spi_csn2_o]
connect_bd_net -net "spi_csn${i}" \
[get_bd_pins $ps7_cs] \
[get_bd_ports spi_csn2_o]
}
3
{ set spi_csn3_o [create_bd_port -dir O spi_csn3_o]
connect_bd_net -net "spi_csn${i}" \
[get_bd_pins $ps7_cs] \
[get_bd_ports spi_csn3_o]
}
}
incr i
# add SPI interface to ps7, first check which SPI is free
if { [get_property CONFIG.PCW_SPI0_PERIPHERAL_ENABLE [get_bd_cells sys_ps7]] == 0 } {
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set if_spi "SPI0"
} else {
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_SPI0_IO {EMIO}] $sys_ps7
set if_spi "SPI1"
}
# connect chipselect lines to the ports
if { $spi_ss > 1 } {
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 "${spi_name}_csn_concat"
set_property CONFIG.NUM_PORTS $spi_ss [get_bd_cells "${spi_name}_csn_concat"]
connect_bd_net -net "${spi_name}_csn_o" \
[get_bd_ports "${spi_name}_csn_o"] \
[get_bd_pins "${spi_name}_csn_concat/dout"]
set i 0
set j [expr $spi_ss - 1]
while { $i < $spi_ss } {
if { $j == 0 } {
set ss_number SS
} else {
set ss_number SS${j}
}
connect_bd_net [get_bd_pins "${spi_name}_csn_concat/In${i}"] \
[get_bd_pins "sys_ps7/${if_spi}_${ss_number}_O"]
incr i
incr j -1
}
} else {
connect_bd_net -net "${spi_name}_csn_o" \
[get_bd_ports "${spi_name}_csn_o"] \
[get_bd_pins "sys_ps7/${if_spi}_SS_O"]
}
# connect remaining nets to the ports
connect_bd_net -net spi_csn_i \
[get_bd_ports spi_csn_i] \
[get_bd_pins sys_ps7/SPI0_SS_I]
[get_bd_ports "${spi_name}_csn_i"] \
[get_bd_pins "sys_ps7/${if_spi}_SS_I"]
connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_sclk_i] \
[get_bd_pins sys_ps7/SPI0_SCLK_I]
[get_bd_ports "${spi_name}_sclk_i"] \
[get_bd_pins "sys_ps7/${if_spi}_SCLK_I"]
connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_sclk_o] \
[get_bd_pins sys_ps7/SPI0_SCLK_O]
[get_bd_ports "${spi_name}_sclk_o"] \
[get_bd_pins "sys_ps7/${if_spi}_SCLK_O"]
connect_bd_net -net spi_mosi_i \
[get_bd_ports spi_mosi_i] \
[get_bd_pins sys_ps7/SPI0_MOSI_I]
[get_bd_ports "${spi_name}_mosi_i"] \
[get_bd_pins "sys_ps7/${if_spi}_MOSI_I"]
connect_bd_net -net spi_mosi_o \
[get_bd_ports spi_mosi_o] \
[get_bd_pins sys_ps7/SPI0_MOSI_O]
[get_bd_ports "${spi_name}_mosi_o"] \
[get_bd_pins "sys_ps7/${if_spi}_MOSI_O"]
connect_bd_net -net spi_miso_i \
[get_bd_ports spi_miso_i] \
[get_bd_pins sys_ps7/SPI0_MISO_I]
[get_bd_ports "${spi_name}_miso_i"] \
[get_bd_pins "sys_ps7/${if_spi}_MISO_I"]
} else {
# SPI SS lines
set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
# instanciate AXI_SPI core
set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
@ -171,152 +179,116 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
switch $spi_ss_width {
1
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $spi_name
}
2
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $spi_name
}
3
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $spi_name
}
4
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $spi_name
}
}
set_property CONFIG.C_NUM_SS_BITS $spi_ss $spi_name
adi_interconnect_lite $spi_name $spi_base_addr
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${spi_name}/ext_spi_clk"] \
$::sys_100m_clk_source
# spi external ports
connect_bd_net -net spi_csn_o \
[get_bd_ports spi_csn_o] \
[get_bd_ports "${spi_name}_csn_o"] \
[get_bd_pins "${spi_name}/ss_o"]
connect_bd_net -net spi_csn_i \
[get_bd_ports spi_csn_i] \
[get_bd_ports "${spi_name}_csn_i"] \
[get_bd_pins "${spi_name}/ss_i"]
connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_sclk_o] \
[get_bd_ports "${spi_name}_sclk_o"] \
[get_bd_pins "${spi_name}/sck_o"]
connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_sclk_i] \
[get_bd_ports "${spi_name}_sclk_i"] \
[get_bd_pins "${spi_name}/sck_i"]
connect_bd_net -net spi_mosi_o \
[get_bd_ports spi_mosi_o] \
[get_bd_ports "${spi_name}_mosi_o"] \
[get_bd_pins "${spi_name}/io0_o"]
connect_bd_net -net spi_mosi_i \
[get_bd_ports spi_mosi_i] \
[get_bd_ports "${spi_name}_mosi_i"] \
[get_bd_pins "${spi_name}/io0_i"]
connect_bd_net -net spi_miso_i \
[get_bd_ports spi_miso_i] \
[get_bd_ports "${spi_name}_miso_i"] \
[get_bd_pins "${spi_name}/io1_i"]
}
}
# For AXI interconnect connections between dma and 'ddr controller'/HP port
proc adi_dma_interconnect { dma_name port_name} {
#------------------------------------------------------------------------------
# adi_dma_interconnect axi_ad9467_dma/m_dest_axi sys_200m_clk axi_mem_interconnect
#------------------------------------------------------------------------------
proc adi_dma_interconnect { dma_if dma_clk ic_name } {
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
set dma_atrb [split $dma_if "/"]
lassign $dma_atrb dma_name dma_if_port
set hp_port [free_hp_port [get_bd_cells sys_ps7]]
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
switch $hp_port {
1
{
set axi_dma_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_1]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_1
}
2
{
set axi_dma_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_2]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_2
}
3
{
set axi_dma_interconnect_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_3]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_3
}
# increment the number of the slave ports of the interconnect
set p_port [get_property CONFIG.NUM_SI [get_bd_cells $ic_name]]
if { $p_port == 1} {
if { [get_bd_intf_nets -of_object [get_bd_intf_pins "${ic_name}/S00_AXI"]] eq {} } {
set i_count 1
set i_str [get_numstr 0]
} else {
set i_count [expr $p_port + 1]
set i_str [get_numstr $p_port]
}
# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
connect_bd_net -net sys_100m_clk \
[get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_dma_interconnect_m00_axi \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \
[get_bd_intf_pins sys_ps7/S_AXI_HP1]
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ACLK"] \
$::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ARESETN"] \
$::sys_100m_resetn_source
# connect clk and reset for the peripheral port
puts "${dma_name}/${port_name}_aclk"
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${dma_name}/${port_name}_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
# Connect the interconnect to the dma
connect_bd_intf_net -intf_net "axi_dma_interconnect_${hp_port}_s00_axi" \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \
[get_bd_intf_pins "${dma_name}/${port_name}"]
# Definte address space
create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
[get_bd_addr_spaces "${dma_name}/${port_name}"] \
[get_bd_addr_segs "sys_ps7/S_AXI_HP${hp_port}/HP${hp_port}_DDR_LOWOCM"] \
"SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
} else {
set axi_mem_interconnect [get_bd_cells axi_mem_interconnect]
# increment the number of the master ports of the interconnect
set number_of_slave [get_property CONFIG.NUM_SI $axi_mem_interconnect]
set number_of_slave [expr $number_of_slave + 1]
set_property CONFIG.NUM_SI $number_of_slave $axi_mem_interconnect
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${axi_mem_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
$::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
$::sys_100m_resetn_source
# connect clk and reset for the peripheral port
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${dma_name}/${port_name}_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
# make the port connection
connect_bd_intf_net -intf_net "axi_mem_interconnect_s${number_of_slave}" \
[get_bd_intf_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_AXI"] \
[get_bd_intf_pins "${dma_name}/${port_name}"]
# define address space for the peripheral
create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
[get_bd_addr_spaces "${dma_name}/${port_name}"] \
[get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \
"SEG_data_${dma_name}_2_ddr"
set i_count [expr $p_port + 1]
set i_str [get_numstr $p_port]
}
set_property CONFIG.NUM_SI $i_count [get_bd_cells $ic_name]
# connect clk and reset for the interconnect
connect_bd_net [get_bd_pins "${ic_name}/S${i_str}_ACLK"] \
${dma_clk}
connect_bd_net [get_bd_pins "${ic_name}/S${i_str}_ARESETN"] \
$::sys_100m_resetn_source
# connect clk and reset for the peripheral port
connect_bd_net [get_bd_pins "${dma_name}/${dma_if_port}_aclk"] \
${dma_clk}
connect_bd_net [get_bd_pins "${dma_name}/${dma_if_port}_aresetn"] \
$::sys_100m_resetn_source
# make the port connection
connect_bd_intf_net -intf_net "${dma_name}_${i_str}" \
[get_bd_intf_pins "${ic_name}/S${i_str}_AXI"] \
[get_bd_intf_pins "${dma_name}/${dma_if_port}"]
# define address space for the peripheral
assign_bd_address
}
#------------------------------------------------------------------------------
# usage : adi_hp_assign 1
#------------------------------------------------------------------------------
proc adi_hp_assign { hp_port hp_clk } {
# check is hp port is enabled
if { [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port}" [get_bd_cells sys_ps7]] == 1 } {
#return the interconnect of the hp port
set hp_net [get_bd_intf_nets -of_objects [get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]]
set hp_net_cells [get_bd_cells -of_obkects $hp_net]
set idx [lsearch $hp_net_cells "/sys_ps7"]
set ic_hp [lreplace $hp_net_cells $idx $idx]
} else {
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
set ic_hp "axi_hp${hp_port}_interconnect"
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 $ic_hp
set_property -dict [list CONFIG.NUM_MI {1}] [get_bd_cells $ic_hp]
connect_bd_intf_net -intf_net "${ic_hp}_m00_axi" \
[get_bd_intf_pins "${ic_hp}/M00_AXI"] \
[get_bd_intf_pins "sys_ps7/S_AXI_HP${hp_port}"]
# connect interconnect clock and reset
connect_bd_net [get_bd_pins "${ic_hp}/ACLK"] \
[get_bd_pins "${ic_hp}/M00_ACLK"] \
[get_bd_pins "sys_ps7/S_AXI_HP${hp_port}_ACLK"] \
$hp_clk
connect_bd_net [get_bd_pins "${ic_hp}/ARESETN"] \
[get_bd_pins "${ic_hp}/M00_ARESETN"] \
$::sys_100m_resetn_source
}
return $ic_hp
}

292
projects/usdrx1/common/usdrx1_bd.tcl Executable file
View File

@ -0,0 +1,292 @@
# usdrx1
set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
set rx_sync [create_bd_port -dir O rx_sync]
set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
set mlo_clk [create_bd_port -dir O mlo_clk]
set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data]
set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0]
set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1]
set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2]
set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3]
set adc_dwr_0 [create_bd_port -dir O adc_dwr_0]
set adc_dwr_1 [create_bd_port -dir O adc_dwr_1]
set adc_dwr_2 [create_bd_port -dir O adc_dwr_2]
set adc_dwr_3 [create_bd_port -dir O adc_dwr_3]
set adc_dsync_0 [create_bd_port -dir O adc_dsync_0]
set adc_dsync_1 [create_bd_port -dir O adc_dsync_1]
set adc_dsync_2 [create_bd_port -dir O adc_dsync_2]
set adc_dsync_3 [create_bd_port -dir O adc_dsync_3]
set adc_ddata_0 [create_bd_port -dir O -from 127 -to 0 adc_ddata_0]
set adc_ddata_1 [create_bd_port -dir O -from 127 -to 0 adc_ddata_1]
set adc_ddata_2 [create_bd_port -dir O -from 127 -to 0 adc_ddata_2]
set adc_ddata_3 [create_bd_port -dir O -from 127 -to 0 adc_ddata_3]
set adc_dovf_0 [create_bd_port -dir I adc_dovf_0]
set adc_dovf_1 [create_bd_port -dir I adc_dovf_1]
set adc_dovf_2 [create_bd_port -dir I adc_dovf_2]
set adc_dovf_3 [create_bd_port -dir I adc_dovf_3]
set adc_dwr [create_bd_port -dir I adc_dwr]
set adc_dsync [create_bd_port -dir I adc_dsync]
set adc_ddata [create_bd_port -dir I -from 511 -to 0 adc_ddata]
set adc_dovf [create_bd_port -dir O adc_dovf]
# adc peripherals
set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0]
set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1]
set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2]
set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3]
set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3]
set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_usdrx1_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd
set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] [get_bd_cells axi_usdrx1_gt]
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt
set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {512}] $axi_usdrx1_dma
set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect
set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect
# gpio and spi
set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {15}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7
set_property LEFT 43 [get_bd_ports GPIO_I]
set_property LEFT 43 [get_bd_ports GPIO_O]
set_property LEFT 43 [get_bd_ports GPIO_T]
# connections (spi and gpio)
connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i]
connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o]
connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i]
connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o]
connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i]
connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o]
connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk]
connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3]
# connections (gt)
connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref]
# connections (adc)
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk]
connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset]
connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_jesd/rx_sysref]
connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in]
connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done]
connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out]
connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync]
connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame]
connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata]
connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] [get_bd_ports gt_rx_data]
connect_bd_net -net axi_usdrx1_gt_rx_data_0 [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_ports gt_rx_data_0]
connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_ports gt_rx_data_1]
connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2]
connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3]
connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9671_core_adc_dwr_0 [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_ports adc_dwr_0]
connect_bd_net -net axi_ad9671_core_adc_dwr_1 [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_ports adc_dwr_1]
connect_bd_net -net axi_ad9671_core_adc_dwr_2 [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_ports adc_dwr_2]
connect_bd_net -net axi_ad9671_core_adc_dwr_3 [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_ports adc_dwr_3]
connect_bd_net -net axi_ad9671_core_adc_dsync_0 [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_ports adc_dsync_0]
connect_bd_net -net axi_ad9671_core_adc_dsync_1 [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_ports adc_dsync_1]
connect_bd_net -net axi_ad9671_core_adc_dsync_2 [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_ports adc_dsync_2]
connect_bd_net -net axi_ad9671_core_adc_dsync_3 [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_ports adc_dsync_3]
connect_bd_net -net axi_ad9671_core_adc_ddata_0 [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_ports adc_ddata_0]
connect_bd_net -net axi_ad9671_core_adc_ddata_1 [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_ports adc_ddata_1]
connect_bd_net -net axi_ad9671_core_adc_ddata_2 [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_ports adc_ddata_2]
connect_bd_net -net axi_ad9671_core_adc_ddata_3 [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_ports adc_ddata_3]
connect_bd_net -net axi_ad9671_core_adc_dovf_0 [get_bd_pins axi_ad9671_core_0/adc_dovf] [get_bd_ports adc_dovf_0]
connect_bd_net -net axi_ad9671_core_adc_dovf_1 [get_bd_pins axi_ad9671_core_1/adc_dovf] [get_bd_ports adc_dovf_1]
connect_bd_net -net axi_ad9671_core_adc_dovf_2 [get_bd_pins axi_ad9671_core_2/adc_dovf] [get_bd_ports adc_dovf_2]
connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core_3/adc_dovf] [get_bd_ports adc_dovf_3]
connect_bd_net -net axi_ad9671_dma_adc_dwr [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_dwr]
connect_bd_net -net axi_ad9671_dma_adc_dsync [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
connect_bd_net -net axi_ad9671_dma_adc_ddata [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_ddata]
connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf]
connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn]
# interconnect (gt es)
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi]
connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/m_axi_aresetn]
# interconnect (dma)
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn]
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data]
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger]
connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1
create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm

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projects/usdrx1/common/usdrx1_spi.v Executable file
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@ -0,0 +1,141 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module usdrx1_spi (
spi_fout_csn,
spi_afe_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_fout_sdio,
spi_afe_sdio,
spi_clk_sdio);
// 4 wire
input [ 5:0] spi_fout_csn;
input [ 3:0] spi_afe_csn;
input spi_clk_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_fout_sdio;
inout spi_afe_sdio;
input spi_clk_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire [ 2:0] spi_csn_3_s;
wire spi_csn_s;
wire spi_enable_s;
wire spi_fout_miso_s;
wire spi_afe_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_3_s[2] = & spi_fout_csn;
assign spi_csn_3_s[1] = & spi_afe_csn;
assign spi_csn_3_s[0] = spi_clk_csn;
assign spi_csn_s = & spi_csn_3_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_csn_3_s[1] == 1'b0)) ||
((spi_count == 6'd16) && (spi_csn_3_s[0] == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) |
(spi_afe_miso_s & ~spi_csn_3_s[1]) |
(spi_clk_miso_s & ~spi_csn_3_s[0]));
// io buffers
IOBUF i_iobuf_fout_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_fout_miso_s),
.IO (spi_fout_sdio));
IOBUF i_iobuf_afe_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_afe_miso_s),
.IO (spi_afe_sdio));
IOBUF i_iobuf_clk_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_clk_miso_s),
.IO (spi_clk_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/usdrx1_bd.tcl

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projects/usdrx1/zc706/system_constr.xdc Executable file
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# constraints
# ultrasound
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AH6} [get_ports rx_data_p[4]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5} [get_ports rx_data_n[4]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AG4} [get_ports rx_data_p[5]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3} [get_ports rx_data_n[5]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AF6} [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5} [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AD6} [get_ports rx_data_p[7]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5} [get_ports rx_data_n[7]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D23 FMC_HPC_LA23_P
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D24 FMC_HPC_LA23_N
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports afe_rst_p] ; ## G27 FMC_HPC_LA25_P
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports afe_rst_n] ; ## G28 FMC_HPC_LA25_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25} [get_ports afe_trig_p] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25} [get_ports afe_trig_n] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_clk] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_mlo] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_rst] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sync] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sysref] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_trig] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_fout_clk] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_fout_sdio] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[0]] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[1]] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[2]] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[3]] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_afe_clk] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_afe_sdio] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_pdn] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_stby] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports clk_resetn] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports clk_syncn] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports clk_status] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports amp_disbn] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports prc_sck] ; ## G21 FMC_HPC_LA20_P
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports prc_cnv] ; ## G22 FMC_HPC_LA20_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports prc_sdo_i] ; ## G24 FMC_HPC_LA22_P
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports prc_sdo_q] ; ## G25 FMC_HPC_LA22_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports dac_sleep] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports dac_data[0]] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports dac_data[1]] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports dac_data[2]] ; ## H23 FMC_HPC_LA19_N
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports dac_data[3]] ; ## H22 FMC_HPC_LA19_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports dac_data[4]] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports dac_data[5]] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports dac_data[6]] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports dac_data[7]] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports dac_data[8]] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports dac_data[9]] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports dac_data[10]] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports dac_data[11]] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports dac_data[12]] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data[13]] ; ## H07 FMC_HPC_LA02_P
# clocks
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

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projects/usdrx1/zc706/system_project.tcl Executable file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create usdrx1_zc706
adi_project_files usdrx1_zc706 [list \
"system_top.v" \
"system_constr.xdc" \
"../common/usdrx1_spi.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run usdrx1_zc706

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projects/usdrx1/zc706/system_top.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
spi_fout_enb_clk,
spi_fout_enb_mlo,
spi_fout_enb_rst,
spi_fout_enb_sync,
spi_fout_enb_sysref,
spi_fout_enb_trig,
spi_fout_clk,
spi_fout_sdio,
spi_afe_csn,
spi_afe_clk,
spi_afe_sdio,
spi_clk_csn,
spi_clk_clk,
spi_clk_sdio,
afe_mlo_p,
afe_mlo_n,
afe_rst_p,
afe_rst_n,
afe_trig_p,
afe_trig_n,
dac_sleep,
dac_data,
afe_pdn,
afe_stby,
clk_resetn,
clk_syncn,
clk_status,
amp_disbn,
prc_sck,
prc_cnv,
prc_sdo_i,
prc_sdo_q);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
output spi_fout_enb_clk;
output spi_fout_enb_mlo;
output spi_fout_enb_rst;
output spi_fout_enb_sync;
output spi_fout_enb_sysref;
output spi_fout_enb_trig;
output spi_fout_clk;
inout spi_fout_sdio;
output [ 3:0] spi_afe_csn;
output spi_afe_clk;
inout spi_afe_sdio;
output spi_clk_csn;
output spi_clk_clk;
inout spi_clk_sdio;
output afe_mlo_p;
output afe_mlo_n;
output afe_rst_p;
output afe_rst_n;
output afe_trig_p;
output afe_trig_n;
inout dac_sleep;
inout [13:0] dac_data;
inout afe_pdn;
inout afe_stby;
inout clk_resetn;
inout clk_syncn;
inout clk_status;
inout amp_disbn;
inout prc_sck;
inout prc_cnv;
inout prc_sdo_i;
inout prc_sdo_q;
// internal signals
wire [43:0] gpio_i;
wire [43:0] gpio_o;
wire [43:0] gpio_t;
wire [10:0] spi_csn;
wire afe_mlo;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire [ 1:0] gpio_open;
wire [511:0] adc_ddata;
wire [127:0] adc_ddata_0;
wire [127:0] adc_ddata_1;
wire [127:0] adc_ddata_2;
wire [127:0] adc_ddata_3;
wire adc_dovf;
wire adc_dovf_0;
wire adc_dovf_1;
wire adc_dovf_2;
wire adc_dovf_3;
wire adc_dsync;
wire adc_dsync_0;
wire adc_dsync_1;
wire adc_dsync_2;
wire adc_dsync_3;
wire adc_dwr;
wire adc_dwr_0;
wire adc_dwr_1;
wire adc_dwr_2;
wire adc_dwr_3;
wire [255:0] gt_rx_data;
wire [63:0] gt_rx_data_0;
wire [63:0] gt_rx_data_1;
wire [63:0] gt_rx_data_2;
wire [63:0] gt_rx_data_3;
// spi assignments
assign spi_fout_enb_clk = spi_csn[10:10];
assign spi_fout_enb_mlo = spi_csn[ 9: 9];
assign spi_fout_enb_rst = spi_csn[ 8: 8];
assign spi_fout_enb_sync = spi_csn[ 7: 7];
assign spi_fout_enb_sysref = spi_csn[ 6: 6];
assign spi_fout_enb_trig = spi_csn[ 5: 5];
assign spi_afe_csn = spi_csn[ 4: 1];
assign spi_clk_csn = spi_csn[ 0: 0];
assign spi_fout_clk = spi_clk;
assign spi_afe_clk = spi_clk;
assign spi_clk_clk = spi_clk;
// single dma for all channels
assign gt_rx_data_3 = gt_rx_data[255:192];
assign gt_rx_data_2 = gt_rx_data[191:128];
assign gt_rx_data_1 = gt_rx_data[127: 64];
assign gt_rx_data_0 = gt_rx_data[ 63: 0];
assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0;
assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0;
assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0};
assign adc_dovf_0 = adc_dovf;
assign adc_dovf_1 = adc_dovf;
assign adc_dovf_2 = adc_dovf;
assign adc_dovf_3 = adc_dovf;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_mlo (
.I (afe_mlo),
.O (afe_mlo_p),
.OB (afe_mlo_n));
IOBUF i_iobuf_gpio_prc_sdo_q (
.I (gpio_o[43]),
.O (gpio_i[43]),
.T (gpio_t[43]),
.IO (prc_sdo_q));
IOBUF i_iobuf_gpio_prc_sdo_i (
.I (gpio_o[42]),
.O (gpio_i[42]),
.T (gpio_t[42]),
.IO (prc_sdo_i));
IOBUF i_iobuf_gpio_prc_cnv (
.I (gpio_o[41]),
.O (gpio_i[41]),
.T (gpio_t[41]),
.IO (prc_cnv));
IOBUF i_iobuf_gpio_prc_sck (
.I (gpio_o[40]),
.O (gpio_i[40]),
.T (gpio_t[40]),
.IO (prc_sck));
IOBUF i_iobuf_gpio_amp_disbn (
.I (gpio_o[39]),
.O (gpio_i[39]),
.T (gpio_t[39]),
.IO (amp_disbn));
IOBUF i_iobuf_gpio_clk_status (
.I (gpio_o[38]),
.O (gpio_i[38]),
.T (gpio_t[38]),
.IO (clk_status));
IOBUF i_iobuf_gpio_clk_syncn (
.I (gpio_o[37]),
.O (gpio_i[37]),
.T (gpio_t[37]),
.IO (clk_syncn));
IOBUF i_iobuf_gpio_clk_resetn (
.I (gpio_o[36]),
.O (gpio_i[36]),
.T (gpio_t[36]),
.IO (clk_resetn));
IOBUF i_iobuf_gpio_afe_stby (
.I (gpio_o[35]),
.O (gpio_i[35]),
.T (gpio_t[35]),
.IO (afe_stby));
IOBUF i_iobuf_gpio_afe_pdn (
.I (gpio_o[34]),
.O (gpio_i[34]),
.T (gpio_t[34]),
.IO (afe_pdn));
OBUFDS i_obufds_gpio_afe_trig (
.I (gpio_o[33]),
.O (afe_trig_p),
.OB (afe_trig_n));
OBUFDS i_obufds_gpio_afe_rst (
.I (gpio_o[32]),
.O (afe_rst_p),
.OB (afe_rst_n));
IOBUF i_iobuf_gpio_dac_sleep (
.I (gpio_o[30]),
.O (gpio_i[30]),
.T (gpio_t[30]),
.IO (dac_sleep));
genvar n;
generate
for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data
IOBUF i_iobuf_gpio_dac_data (
.I (gpio_o[16+n]),
.O (gpio_i[16+n]),
.T (gpio_t[16+n]),
.IO (dac_data[n]));
end
for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
usdrx1_spi i_spi (
.spi_fout_csn (spi_csn[10:5]),
.spi_afe_csn (spi_csn[4:1]),
.spi_clk_csn (spi_csn[0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_fout_sdio (spi_fout_sdio),
.spi_afe_sdio (spi_afe_sdio),
.spi_clk_sdio (spi_clk_sdio));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.adc_ddata (adc_ddata),
.adc_ddata_0 (adc_ddata_0),
.adc_ddata_1 (adc_ddata_1),
.adc_ddata_2 (adc_ddata_2),
.adc_ddata_3 (adc_ddata_3),
.adc_dovf (adc_dovf),
.adc_dovf_0 (adc_dovf_0),
.adc_dovf_1 (adc_dovf_1),
.adc_dovf_2 (adc_dovf_2),
.adc_dovf_3 (adc_dovf_3),
.adc_dsync (adc_dsync),
.adc_dsync_0 (adc_dsync_0),
.adc_dsync_1 (adc_dsync_1),
.adc_dsync_2 (adc_dsync_2),
.adc_dsync_3 (adc_dsync_3),
.adc_dwr (adc_dwr),
.adc_dwr_0 (adc_dwr_0),
.adc_dwr_1 (adc_dwr_1),
.adc_dwr_2 (adc_dwr_2),
.adc_dwr_3 (adc_dwr_3),
.gt_rx_data (gt_rx_data),
.gt_rx_data_0 (gt_rx_data_0),
.gt_rx_data_1 (gt_rx_data_1),
.gt_rx_data_2 (gt_rx_data_2),
.gt_rx_data_3 (gt_rx_data_3),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mlo_clk (afe_mlo),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************