diff --git a/library/util_gtlb/Makefile b/library/util_gtlb/Makefile
deleted file mode 100644
index ff750ba99..000000000
--- a/library/util_gtlb/Makefile
+++ /dev/null
@@ -1,59 +0,0 @@
-####################################################################################
-####################################################################################
-## Copyright 2011(c) Analog Devices, Inc.
-## Auto-generated, do not modify!
-####################################################################################
-####################################################################################
-
-M_DEPS += ../common/up_xfer_status.v
-M_DEPS += ../scripts/adi_env.tcl
-M_DEPS += ../scripts/adi_ip.tcl
-M_DEPS += util_gtlb.v
-M_DEPS += util_gtlb_constr.xdc
-M_DEPS += util_gtlb_ip.tcl
-
-M_DEPS += ../interfaces/if_gt_pll.xml
-M_DEPS += ../interfaces/if_gt_pll_rtl.xml
-M_DEPS += ../interfaces/if_gt_qpll.xml
-M_DEPS += ../interfaces/if_gt_qpll_rtl.xml
-M_DEPS += ../interfaces/if_gt_rx.xml
-M_DEPS += ../interfaces/if_gt_rx_rtl.xml
-M_DEPS += ../interfaces/if_gt_tx.xml
-M_DEPS += ../interfaces/if_gt_tx_rtl.xml
-
-M_VIVADO := vivado -mode batch -source
-
-M_FLIST := *.cache
-M_FLIST += *.data
-M_FLIST += *.xpr
-M_FLIST += *.log
-M_FLIST += component.xml
-M_FLIST += *.jou
-M_FLIST +=  xgui
-M_FLIST += *.ip_user_files
-M_FLIST += *.srcs
-M_FLIST += *.hw
-M_FLIST += *.sim
-M_FLIST += .Xil
-
-
-
-.PHONY: all dep clean clean-all
-all: dep util_gtlb.xpr
-
-
-clean:clean-all
-
-
-clean-all:
-	rm -rf $(M_FLIST)
-
-
-util_gtlb.xpr: $(M_DEPS)
-	-rm -rf $(M_FLIST)
-	$(M_VIVADO) util_gtlb_ip.tcl  >> util_gtlb_ip.log 2>&1
-
-dep:
-	make -C ../interfaces
-####################################################################################
-####################################################################################
diff --git a/library/util_gtlb/util_gtlb.v b/library/util_gtlb/util_gtlb.v
deleted file mode 100644
index 1fc9f9591..000000000
--- a/library/util_gtlb/util_gtlb.v
+++ /dev/null
@@ -1,387 +0,0 @@
-// ***************************************************************************
-// ***************************************************************************
-// Copyright 2011(c) Analog Devices, Inc.
-//
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//     - Redistributions of source code must retain the above copyright
-//       notice, this list of conditions and the following disclaimer.
-//     - Redistributions in binary form must reproduce the above copyright
-//       notice, this list of conditions and the following disclaimer in
-//       the documentation and/or other materials provided with the
-//       distribution.
-//     - Neither the name of Analog Devices, Inc. nor the names of its
-//       contributors may be used to endorse or promote products derived
-//       from this software without specific prior written permission.
-//     - The use of this software may or may not infringe the patent rights
-//       of one or more patent holders.  This license does not release you
-//       from the requirement that you obtain separate licenses from these
-//       patent holders to use this software.
-//     - Use of the software either in source or binary form, must be run
-//       on or directly connected to an Analog Devices Inc. component.
-//
-// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED.
-//
-// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// ***************************************************************************
-// ***************************************************************************
-
-`timescale 1ns/100ps
-
-module util_gtlb (
-
-  // pll clocks & resets
-
-  input                 qpll_ref_clk,
-  input                 cpll_ref_clk,
-
-  output                qpll0_rst,
-  output                qpll0_ref_clk_in,
-
-  output                cpll_rst_m_0,
-  output                cpll_ref_clk_in_0,
-
-  // channel interface (rx)
-  
-  input                 rx_p,
-  input                 rx_n,
-
-  output                rx_clk,
-
-  input       [ 3:0]    rx_gt_charisk_0,
-  input       [ 3:0]    rx_gt_disperr_0,
-  input       [ 3:0]    rx_gt_notintable_0,
-  input       [31:0]    rx_gt_data_0,
-  output  reg           rx_gt_comma_align_enb_0,
-
-  output                rx_0_p,
-  output                rx_0_n,
-  input                 rx_rst_0,
-  output                rx_rst_m_0,
-  input                 rx_pll_rst_0,
-  input                 rx_gt_rst_0,
-  output                rx_gt_rst_m_0,
-  input                 rx_pll_locked_0,
-  output                rx_pll_locked_m_0,
-  input                 rx_user_ready_0,
-  output                rx_user_ready_m_0,
-  input                 rx_rst_done_0,
-  output                rx_rst_done_m_0,
-  input                 rx_out_clk_0,
-  output                rx_clk_0,
-  output                rx_sysref_0,
-  input                 rx_sync_0,
-  input                 rx_sof_0,
-  input       [31:0]    rx_data_0,
-  input                 rx_ip_rst_0,
-  output      [ 3:0]    rx_ip_sof_0,
-  output      [31:0]    rx_ip_data_0,
-  input                 rx_ip_sysref_0,
-  output                rx_ip_sync_0,
-  input                 rx_ip_rst_done_0,
-
-  // channel interface (tx)
-
-  output                tx_p,
-  output                tx_n,
-
-  output                tx_clk,
-
-  output      [ 3:0]    tx_gt_charisk_0,
-  output  reg [31:0]    tx_gt_data_0,
-
-  input                 tx_0_p,
-  input                 tx_0_n,
-  input                 tx_rst_0,
-  output                tx_rst_m_0,
-  input                 tx_pll_rst_0,
-  input                 tx_gt_rst_0,
-  output                tx_gt_rst_m_0,
-  input                 tx_pll_locked_0,
-  output                tx_pll_locked_m_0,
-  input                 tx_user_ready_0,
-  output                tx_user_ready_m_0,
-  input                 tx_rst_done_0,
-  output                tx_rst_done_m_0,
-  input                 tx_out_clk_0,
-  output                tx_clk_0,
-  output                tx_sysref_0,
-  output                tx_sync_0,
-  output      [31:0]    tx_data_0,
-  input                 tx_ip_rst_0,
-  input       [31:0]    tx_ip_data_0,
-  input                 tx_ip_sysref_0,
-  input                 tx_ip_sync_0,
-  input                 tx_ip_rst_done_0,
-
-  // up interface
-
-  input                 up_clk,
-  input                 up_rstn,
-  input       [31:0]    up_gp_in,
-  output      [31:0]    up_gp_out);
-
-  // internal registers
-
-  reg                   tx_sync_m1 = 'd0;
-  reg                   tx_sync_m2 = 'd0;
-  reg                   tx_sync = 'd0;
-  reg         [31:0]    tx_pn_data = 'd0;
-  reg                   tx_charisk_1 = 'd0;
-  reg         [ 3:0]    rx_kcount = 'd0;
-  reg                   rx_sync = 'd0;
-  reg         [31:0]    rx_pn_data = 'd0;
-  reg                   rx_pn_match_d = 'd0;
-  reg                   rx_pn_match_z = 'd0;
-  reg                   rx_pn_err = 'd0;
-  reg                   rx_pn_oos = 'd0;
-  reg         [ 3:0]    rx_pn_oos_count = 'd0;
-  reg                   up_pn_err_clr_d = 'd0;
-  reg                   up_pn_oos_clr_d = 'd0;
-  reg                   up_pn_err = 'd0;
-  reg                   up_pn_oos = 'd0;
-    
-  // internal signals
-
-  wire        [31:0]    rx_gt_data_0_s;
-  wire        [31:0]    rx_pn_data_s;
-  wire                  rx_pn_match_d_s;
-  wire                  rx_pn_match_z_s;
-  wire                  rx_pn_match_s;
-  wire                  rx_pn_update_s;
-  wire                  rx_pn_err_s;
-  wire                  up_pn_err_clr_s;
-  wire                  up_pn_oos_clr_s;
-  wire                  up_pn_err_s;
-  wire                  up_pn_oos_s;
-
-  // pn31 function
-
-  function [31:0] pn31;
-    input [31:0] din;
-    reg   [31:0] dout;
-    begin
-      dout[31] = din[31] ^ din[28];
-      dout[30] = din[30] ^ din[27];
-      dout[29] = din[29] ^ din[26];
-      dout[28] = din[28] ^ din[25];
-      dout[27] = din[27] ^ din[24];
-      dout[26] = din[26] ^ din[23];
-      dout[25] = din[25] ^ din[22];
-      dout[24] = din[24] ^ din[21];
-      dout[23] = din[23] ^ din[20];
-      dout[22] = din[22] ^ din[19];
-      dout[21] = din[21] ^ din[18];
-      dout[20] = din[20] ^ din[17];
-      dout[19] = din[19] ^ din[16];
-      dout[18] = din[18] ^ din[15];
-      dout[17] = din[17] ^ din[14];
-      dout[16] = din[16] ^ din[13];
-      dout[15] = din[15] ^ din[12];
-      dout[14] = din[14] ^ din[11];
-      dout[13] = din[13] ^ din[10];
-      dout[12] = din[12] ^ din[ 9];
-      dout[11] = din[11] ^ din[ 8];
-      dout[10] = din[10] ^ din[ 7];
-      dout[ 9] = din[ 9] ^ din[ 6];
-      dout[ 8] = din[ 8] ^ din[ 5];
-      dout[ 7] = din[ 7] ^ din[ 4];
-      dout[ 6] = din[ 6] ^ din[ 3];
-      dout[ 5] = din[ 5] ^ din[ 2];
-      dout[ 4] = din[ 4] ^ din[ 1];
-      dout[ 3] = din[ 3] ^ din[ 0];
-      dout[ 2] = din[ 2] ^ din[31] ^ din[28];
-      dout[ 1] = din[ 1] ^ din[30] ^ din[27];
-      dout[ 0] = din[ 0] ^ din[29] ^ din[26];
-      pn31 = dout;
-    end
-  endfunction
-
-  // defaults
-
-  assign qpll0_rst = tx_pll_rst_0 | rx_pll_rst_0;
-  assign qpll0_ref_clk_in = qpll_ref_clk;
-  assign cpll_rst_m_0 = tx_pll_rst_0 | rx_pll_rst_0;
-  assign cpll_ref_clk_in_0 = cpll_ref_clk;
-
-  assign rx_0_p = rx_p;
-  assign rx_0_n = rx_n;
-  assign rx_rst_m_0 = rx_rst_0;
-  assign rx_gt_rst_m_0 = rx_gt_rst_0;
-  assign rx_pll_locked_m_0 = rx_pll_locked_0;
-  assign rx_user_ready_m_0 = rx_user_ready_0;
-  assign rx_rst_done_m_0 = & rx_rst_done_0;
-  assign rx_clk_0 = rx_out_clk_0;
-  assign rx_sysref_0 = 1'd0;
-  assign rx_ip_sof_0 = 4'hf;
-  assign rx_ip_data_0 = 32'd0;
-  assign rx_ip_sync_0 = rx_sync;
-  assign rx_clk = rx_out_clk_0;
-
-  assign tx_p = tx_0_p;
-  assign tx_n = tx_0_n;
-  assign tx_rst_m_0 = tx_rst_0;
-  assign tx_gt_rst_m_0 = tx_gt_rst_0;
-  assign tx_pll_locked_m_0 = tx_pll_locked_0;
-  assign tx_user_ready_m_0 = tx_user_ready_0;
-  assign tx_rst_done_m_0 = tx_rst_done_0;
-  assign tx_clk_0 = tx_out_clk_0;
-  assign tx_sysref_0 = 1'd0;
-  assign tx_sync_0 = tx_sync;
-  assign tx_data_0 = 32'd0;
-  assign tx_clk = tx_out_clk_0;
-
-  // gt loop back
-
-  assign tx_gt_charisk_0 = {4{tx_charisk_1}};
-
-  always @(posedge tx_out_clk_0 or posedge tx_rst_0) begin
-    if (tx_rst_0 == 1'b1) begin
-      tx_sync_m1 <= 1'd0;
-      tx_sync_m2 <= 1'd0;
-      tx_sync <= 1'd0;
-      tx_pn_data <= 32'hffffffff;
-      tx_charisk_1 <= 1'd0;
-      tx_gt_data_0 <= 32'd0;
-    end else begin
-      tx_sync_m1 <= rx_sync;
-      tx_sync_m2 <= tx_sync_m1;
-      tx_sync <= tx_sync_m2;
-      tx_pn_data <= pn31(tx_pn_data);
-      if (tx_sync == 1'b1) begin
-        tx_charisk_1 <= 1'd0;
-        tx_gt_data_0[31:24] <= tx_pn_data[ 7: 0];
-        tx_gt_data_0[23:16] <= tx_pn_data[15: 8];
-        tx_gt_data_0[15: 8] <= tx_pn_data[23:16];
-        tx_gt_data_0[ 7: 0] <= tx_pn_data[31:24];
-      end else begin
-        tx_charisk_1 <= 1'd1;
-        tx_gt_data_0[31:24] <= 8'hbc;
-        tx_gt_data_0[23:16] <= 8'hbc;
-        tx_gt_data_0[15: 8] <= 8'hbc;
-        tx_gt_data_0[ 7: 0] <= 8'hbc;
-      end
-    end
-  end
-
-  assign rx_gt_data_0_s[31:24] = rx_gt_data_0[ 7: 0];
-  assign rx_gt_data_0_s[23:16] = rx_gt_data_0[15: 8];
-  assign rx_gt_data_0_s[15: 8] = rx_gt_data_0[23:16];
-  assign rx_gt_data_0_s[ 7: 0] = rx_gt_data_0[31:24];
-
-  always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
-    if (rx_rst_0 == 1'b1) begin
-      rx_gt_comma_align_enb_0 <= 1'd0;
-      rx_kcount <= 4'd0;
-      rx_sync <= 1'd0;
-    end else begin
-      rx_gt_comma_align_enb_0 <= ~rx_sync;
-      if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0)) begin
-        if ((rx_gt_charisk_0 == 4'hf) && (rx_gt_data_0_s == 32'hbcbcbcbc)) begin
-          rx_kcount <= rx_kcount + 1'b1;
-          if (rx_kcount == 4'hf) begin
-            rx_sync <= 1'b1;
-          end
-        end else begin
-          rx_kcount <= 4'd0;
-          rx_sync <= rx_sync;
-        end
-      end else begin
-        rx_kcount <= 4'd0;
-        rx_sync <= 1'd0;
-      end
-    end
-  end
-
-  assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_gt_data_0_s : rx_pn_data;
-  assign rx_pn_match_d_s = (rx_gt_data_0_s == rx_pn_data) ? 1'b1 : 1'b0;
-  assign rx_pn_match_z_s = (rx_gt_data_0_s == 'd0) ? 1'b0 : 1'b1;
-  assign rx_pn_match_s = rx_pn_match_d & rx_pn_match_z;
-  assign rx_pn_update_s = ~(rx_pn_oos ^ rx_pn_match_s);
-  assign rx_pn_err_s = ~(rx_pn_oos | rx_pn_match_s);
-
-  always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
-    if (rx_rst_0 == 1'b1) begin
-      rx_pn_data <= 32'd0;
-      rx_pn_match_d <= 'd0;
-      rx_pn_match_z <= 'd0;
-      rx_pn_err <= 'd0;
-      rx_pn_oos <= 'd0;
-      rx_pn_oos_count <= 'd0;
-    end else begin
-      rx_pn_data <= pn31(rx_pn_data_s);
-      rx_pn_match_d <= rx_pn_match_d_s;
-      rx_pn_match_z <= rx_pn_match_z_s;
-      if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0) && (rx_gt_charisk_0 == 0)) begin
-        rx_pn_err <= rx_pn_err_s;
-        if ((rx_pn_update_s == 1'b1) && (rx_pn_oos_count >= 15)) begin
-          rx_pn_oos <= ~rx_pn_oos;
-        end
-        if (rx_pn_update_s == 1'b1) begin
-          rx_pn_oos_count <= rx_pn_oos_count + 1'b1;
-        end else begin
-          rx_pn_oos_count <= 'd0;
-        end
-      end else begin
-        rx_pn_err <= 1'd0;
-        rx_pn_oos <= 1'd1;
-        rx_pn_oos_count <= 'd0;
-      end
-    end
-  end
-
-  // up clock
-
-  assign up_pn_err_clr_s = up_gp_in[1];
-  assign up_pn_oos_clr_s = up_gp_in[0];
-
-  assign up_gp_out[31:2] = 30'd0;
-  assign up_gp_out[1] = up_pn_err;
-  assign up_gp_out[0] = up_pn_oos;
-
-  up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
-    .up_rstn (up_rstn),
-    .up_clk (up_clk),
-    .up_data_status ({up_pn_err_s, up_pn_oos_s}),
-    .d_rst (rx_rst_0),
-    .d_clk (rx_out_clk_0),
-    .d_data_status ({rx_pn_err, rx_pn_oos}));
-
-  always @(posedge up_clk or negedge up_rstn) begin
-    if (up_rstn == 1'b0) begin
-      up_pn_err_clr_d <= 'd0;
-      up_pn_oos_clr_d <= 'd0;
-      up_pn_err <= 'd0;
-      up_pn_oos <= 'd0;
-    end else begin
-      up_pn_err_clr_d <= up_pn_err_clr_s;
-      up_pn_oos_clr_d <= up_pn_oos_clr_s;
-      if (up_pn_err_s == 1'b1) begin
-        up_pn_err <= 1'b1;
-      end else if ((up_pn_err_clr_s == 1'b1) &&
-        (up_pn_err_clr_d == 1'b0)) begin
-        up_pn_err <= 1'b0;
-      end
-      if (up_pn_oos_s == 1'b1) begin
-        up_pn_oos <= 1'b1;
-      end else if ((up_pn_oos_clr_s == 1'b1) &&
-        (up_pn_oos_clr_d == 1'b0)) begin
-        up_pn_oos <= 1'b0;
-      end
-    end
-  end
-
-endmodule
-
-// ***************************************************************************
-// ***************************************************************************
-
diff --git a/library/util_gtlb/util_gtlb_constr.xdc b/library/util_gtlb/util_gtlb_constr.xdc
deleted file mode 100644
index 644f04f85..000000000
--- a/library/util_gtlb/util_gtlb_constr.xdc
+++ /dev/null
@@ -1,9 +0,0 @@
-
-set_property shreg_extract no [get_cells -hier -filter {name =~ *tx_sync*}]
-set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
-
-set_false_path -to [get_cells -hier -filter {name =~ *tx_sync_m1_reg && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg    && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg   && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg  && IS_SEQUENTIAL}]
-set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data*        && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_data_status*        && IS_SEQUENTIAL}]
-
diff --git a/library/util_gtlb/util_gtlb_ip.tcl b/library/util_gtlb/util_gtlb_ip.tcl
deleted file mode 100644
index cf01a575b..000000000
--- a/library/util_gtlb/util_gtlb_ip.tcl
+++ /dev/null
@@ -1,93 +0,0 @@
-# ip
-
-source ../scripts/adi_env.tcl
-source $ad_hdl_dir/library/scripts/adi_ip.tcl
-
-adi_ip_create util_gtlb
-adi_ip_files util_gtlb [list \
-  "$ad_hdl_dir/library/common/up_xfer_status.v" \
-  "util_gtlb_constr.xdc" \
-  "util_gtlb.v" ]
-
-adi_ip_properties_lite util_gtlb
-adi_ip_constraints util_gtlb [list \
-  "util_gtlb_constr.xdc" ]
-
-ipx::remove_all_bus_interface [ipx::current_core]
-
-adi_if_infer_bus ADI:user:if_gt_qpll master gt_qpll_0 [list \
-  "qpll_rst            qpll0_rst              "\
-  "qpll_ref_clk        qpll0_ref_clk_in       "]
-
-for {set n 0} {$n < 1} {incr n} {
-
-  adi_if_infer_bus ADI:user:if_gt_pll master gt_pll_${n} [list \
-    "cpll_rst_m          cpll_rst_m_${n}        "\
-    "cpll_ref_clk_in     cpll_ref_clk_in_${n}   "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_rx_bus slave gt_rx_ip_${n} [list \
-    "rxcharisk           rx_gt_charisk_${n}     "\
-    "rxdisperr           rx_gt_disperr_${n}     "\
-    "rxnotintable        rx_gt_notintable_${n}  "\
-    "rxdata              rx_gt_data_${n}        "]
-
-  adi_if_infer_bus ADI:user:if_gt_rx master gt_rx_${n} [list \
-    "rx_p                rx_${n}_p              "\
-    "rx_n                rx_${n}_n              "\
-    "rx_rst              rx_rst_${n}            "\
-    "rx_rst_m            rx_rst_m_${n}          "\
-    "rx_pll_rst          rx_pll_rst_${n}        "\
-    "rx_gt_rst           rx_gt_rst_${n}         "\
-    "rx_gt_rst_m         rx_gt_rst_m_${n}       "\
-    "rx_pll_locked       rx_pll_locked_${n}     "\
-    "rx_pll_locked_m     rx_pll_locked_m_${n}   "\
-    "rx_user_ready       rx_user_ready_${n}     "\
-    "rx_user_ready_m     rx_user_ready_m_${n}   "\
-    "rx_rst_done         rx_rst_done_${n}       "\
-    "rx_rst_done_m       rx_rst_done_m_${n}     "\
-    "rx_out_clk          rx_out_clk_${n}        "\
-    "rx_clk              rx_clk_${n}            "\
-    "rx_sysref           rx_sysref_${n}         "\
-    "rx_sync             rx_sync_${n}           "\
-    "rx_sof              rx_sof_${n}            "\
-    "rx_data             rx_data_${n}           "\
-    "rx_ip_rst           rx_ip_rst_${n}         "\
-    "rx_ip_sof           rx_ip_sof_${n}         "\
-    "rx_ip_data          rx_ip_data_${n}        "\
-    "rx_ip_sysref        rx_ip_sysref_${n}      "\
-    "rx_ip_sync          rx_ip_sync_${n}        "\
-    "rx_ip_rst_done      rx_ip_rst_done_${n}    "]
-
-  adi_if_infer_bus xilinx.com:display_jesd204:jesd204_tx_bus master gt_tx_ip_${n} [list \
-    "txcharisk           tx_gt_charisk_${n}     "\
-    "txdata              tx_gt_data_${n}        "]
-
-  adi_if_infer_bus ADI:user:if_gt_tx master gt_tx_${n} [list \
-    "tx_p                tx_${n}_p              "\
-    "tx_n                tx_${n}_n              "\
-    "tx_rst              tx_rst_${n}            "\
-    "tx_rst_m            tx_rst_m_${n}          "\
-    "tx_pll_rst          tx_pll_rst_${n}        "\
-    "tx_gt_rst           tx_gt_rst_${n}         "\
-    "tx_gt_rst_m         tx_gt_rst_m_${n}       "\
-    "tx_pll_locked       tx_pll_locked_${n}     "\
-    "tx_pll_locked_m     tx_pll_locked_m_${n}   "\
-    "tx_user_ready       tx_user_ready_${n}     "\
-    "tx_user_ready_m     tx_user_ready_m_${n}   "\
-    "tx_rst_done         tx_rst_done_${n}       "\
-    "tx_rst_done_m       tx_rst_done_m_${n}     "\
-    "tx_out_clk          tx_out_clk_${n}        "\
-    "tx_clk              tx_clk_${n}            "\
-    "tx_sysref           tx_sysref_${n}         "\
-    "tx_sync             tx_sync_${n}           "\
-    "tx_data             tx_data_${n}           "\
-    "tx_ip_rst           tx_ip_rst_${n}         "\
-    "tx_ip_data          tx_ip_data_${n}        "\
-    "tx_ip_sysref        tx_ip_sysref_${n}      "\
-    "tx_ip_sync          tx_ip_sync_${n}        "\
-    "tx_ip_rst_done      tx_ip_rst_done_${n}    "]
-}
-
-ipx::save_core [ipx::current_core]
-
-