axi_adrv9001:rx: Add reset to link layer

Fix random valid signals after resets on the Rx interface.

library/axi_adrv9001/adrv9001_aligner4.v

@@ -37,6 +37,7 @@
 
 module adrv9001_aligner4 (
   input             clk,
+  input             rst,
   input       [3:0] idata,
   input             ivalid,
   input       [3:0] strobe,
@@ -48,7 +49,9 @@ module adrv9001_aligner4 (
   reg       ivalid_d = 'b0;
 
   always @(posedge clk) begin
-    if (ivalid) begin
+    if (rst) begin
+      idata_d <= 'h0;
+    end else if (ivalid) begin
       idata_d <= idata;
     end
     ivalid_d <= ivalid;
@@ -56,7 +59,9 @@ module adrv9001_aligner4 (
 
   reg [1:0] phase = 'h0;
   always @(posedge clk) begin
-    if (ivalid) begin
+    if (rst) begin
+      phase <= 0;
+    end else if (ivalid) begin
       if ((strobe != 'b1111) && (strobe != 'b0000)) begin
         casex (strobe)
           'b1xxx  : phase <= 0;

library/axi_adrv9001/adrv9001_aligner8.v

@@ -37,6 +37,7 @@
 
 module adrv9001_aligner8 (
   input             clk,
+  input             rst,
   input       [7:0] idata,
   input             ivalid,
   input       [7:0] strobe,
@@ -48,7 +49,9 @@ module adrv9001_aligner8 (
   reg       ivalid_d = 'b0;
 
   always @(posedge clk) begin
-    if (ivalid) begin
+    if (rst) begin
+      idata_d <= 'h0;
+    end else if (ivalid) begin
       idata_d <= idata;
     end
     ivalid_d <= ivalid;
@@ -56,7 +59,9 @@ module adrv9001_aligner8 (
 
   reg [2:0] phase = 'h0;
   always @(posedge clk) begin
-    if (ivalid) begin
+    if (rst) begin
+      phase <= 0;
+    end if (ivalid) begin
       if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin
         casex (strobe)
           'b1xxx_xxxx : phase <= 0;

library/axi_adrv9001/adrv9001_pack.v

@@ -53,6 +53,7 @@ module adrv9001_pack #(
   parameter WIDTH = 8
 )(
   input                      clk,    // Input clock
+  input                      rst,
   input                      sof,    // Start of frame indicator marking the MS Beat
   input       [WIDTH-1:0]    idata,  // Input data beat
   input                      ivalid, // Input data qualifier
@@ -73,7 +74,9 @@ module adrv9001_pack #(
   // Use sof_d[2] for frame size of 4 beats
   // Use sof_d[4,6] for frame size of 8 beats
   always @(posedge clk) begin
-    if (ivalid) begin
+    if (rst) begin
+      sof_d <= 7'b0;
+    end else if (ivalid) begin
       sof_d <= {sof_d[5:0],sof};
     end
     if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin

library/axi_adrv9001/adrv9001_rx_link.v

@@ -39,6 +39,7 @@ module adrv9001_rx_link #(
   parameter CMOS_LVDS_N = 0
 ) (
 
+  input         adc_rst,
   input         adc_clk_div,
   input   [7:0] adc_data_0,
   input   [7:0] adc_data_1,
@@ -100,6 +101,7 @@ module adrv9001_rx_link #(
 
     adrv9001_aligner4 i_rx_aligner4_0 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_0),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
@@ -108,6 +110,7 @@ module adrv9001_rx_link #(
 
     adrv9001_aligner4 i_rx_aligner4_1 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_1),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
@@ -116,6 +119,7 @@ module adrv9001_rx_link #(
 
     adrv9001_aligner4 i_rx_aligner4_2 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_2),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
@@ -124,6 +128,7 @@ module adrv9001_rx_link #(
 
     adrv9001_aligner4 i_rx_aligner4_3 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_3),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
@@ -132,6 +137,7 @@ module adrv9001_rx_link #(
 
     adrv9001_aligner4 i_rx_aligner4_strobe (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_strobe),
       .ivalid (adc_valid),
       .strobe (sdr_data_strobe),
@@ -143,6 +149,7 @@ module adrv9001_rx_link #(
       .WIDTH(4)
     ) i_rx_pack_4_to_8_0 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_0_aligned),
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
@@ -154,6 +161,7 @@ module adrv9001_rx_link #(
       .WIDTH(4)
     ) i_rx_pack_4_to_8_1 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_1_aligned),
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
@@ -176,6 +184,7 @@ module adrv9001_rx_link #(
       .WIDTH(4)
     ) i_rx_pack_4_to_8_3 (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_3_aligned),
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
@@ -187,6 +196,7 @@ module adrv9001_rx_link #(
       .WIDTH(4)
     ) i_rx_pack_4_to_8_strobe (
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (sdr_data_strobe_aligned),
       .ivalid (aligner4_ovalid),
       .sof (sdr_data_strobe_aligned[3]),
@@ -229,6 +239,7 @@ module adrv9001_rx_link #(
 
   adrv9001_aligner8 i_rx_aligner8_0(
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .idata (data_0),
     .ivalid (data_valid),
     .strobe (data_strobe),
@@ -238,6 +249,7 @@ module adrv9001_rx_link #(
 
   adrv9001_aligner8 i_rx_aligner8_1(
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .ivalid (data_valid),
     .idata (data_1),
     .strobe (data_strobe),
@@ -248,6 +260,7 @@ module adrv9001_rx_link #(
   generate if (CMOS_LVDS_N) begin : cmos_aligner8
     adrv9001_aligner8 i_rx_aligner8_2(
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (data_2),
       .ivalid (data_valid),
       .strobe (data_strobe),
@@ -255,6 +268,7 @@ module adrv9001_rx_link #(
     );
     adrv9001_aligner8 i_rx_aligner8_3(
       .clk (adc_clk_div),
+      .rst (adc_rst),
       .idata (data_3),
       .ivalid (data_valid),
       .strobe (data_strobe),
@@ -265,6 +279,7 @@ module adrv9001_rx_link #(
 
   adrv9001_aligner8 i_rx_strobe_aligner(
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .idata (data_strobe),
     .ivalid (data_valid),
     .strobe (data_strobe),
@@ -275,6 +290,7 @@ module adrv9001_rx_link #(
     .WIDTH (8)
   ) i_rx_pack_8_to_16_0 (
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .ivalid (rx_data8_0_aligned_valid),
     .idata (rx_data8_0_aligned),
     .sof (rx_data8_strobe_aligned[7]),
@@ -287,6 +303,7 @@ module adrv9001_rx_link #(
     .WIDTH (8)
   ) i_rx_pack_8_to_16_1 (
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .ivalid (rx_data8_1_aligned_valid),
     .idata (rx_data8_1_aligned),
     .sof (rx_data8_strobe_aligned[7]),
@@ -298,6 +315,7 @@ module adrv9001_rx_link #(
     .WIDTH (16)
   ) i_rx_pack_16_to_32_0 (
     .clk (adc_clk_div),
+    .rst (adc_rst),
     .ivalid (rx_data16_0_packed_valid),
     .idata (rx_data16_0_packed),
     .sof (rx_data16_0_packed_osof),

library/axi_adrv9001/axi_adrv9001_if.v

@@ -237,6 +237,7 @@ module axi_adrv9001_if #(
   adrv9001_rx_link #(
     .CMOS_LVDS_N (CMOS_LVDS_N)
   ) i_rx_1_link (
+    .adc_rst (rx1_rst),
     .adc_clk_div (adc_1_clk_div),
     .adc_data_0 (adc_1_data_0),
     .adc_data_1 (adc_1_data_1),
@@ -297,6 +298,7 @@ module axi_adrv9001_if #(
   adrv9001_rx_link #(
     .CMOS_LVDS_N (CMOS_LVDS_N)
   ) i_rx_2_link (
+    .adc_rst (rx2_rst),
     .adc_clk_div (adc_2_clk_div),
     .adc_data_0 (adc_2_data_0),
     .adc_data_1 (adc_2_data_1),