ad40xx: Initial commit
Istvan Csomortani
István Csomortáni
parent
94f8d1b424
commit
9ab88f1200
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@ -42,7 +42,8 @@ module spi_engine_execution #(
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parameter DEFAULT_CLK_DIV = 0,
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parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
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parameter NUM_OF_SDI = 1,
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parameter [0:0] SDO_DEFAULT = 1'b0) (
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parameter [0:0] SDO_DEFAULT = 1'b0,
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parameter [1:0] SDI_DELAY = 2'b00) (
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input clk,
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input resetn,
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@ -123,6 +124,8 @@ reg [7:0] word_length = DATA_WIDTH;
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reg [7:0] left_aligned = 8'b0;
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wire end_of_word;
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reg [7:0] sdi_counter = 8'b0;
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assign first_bit = bit_counter == 'h0;
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assign last_bit = bit_counter == word_length - 1;
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assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
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@ -137,14 +140,15 @@ wire sdo_enabled = cmd_d1[8];
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wire sdi_enabled = cmd_d1[9];
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// supporting max 8 SDI channel
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reg [(DATA_WIDTH):0] data_shift = 'h0;
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reg [(DATA_WIDTH):0] data_shift_1 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_2 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_3 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_4 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_5 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_6 = 'h0;
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reg [(DATA_WIDTH):0] data_shift_7 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_1 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_2 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_3 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_4 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_5 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_6 = 'h0;
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reg [(DATA_WIDTH-1):0] data_sdi_shift_7 = 'h0;
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wire [1:0] inst = cmd[13:12];
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wire [1:0] inst_d1 = cmd_d1[13:12];
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@ -300,8 +304,7 @@ end
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always @(posedge clk) begin
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if (resetn == 1'b0)
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sdi_data_valid <= 1'b0;
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else if (sdi_enabled == 1'b1 && last_bit == 1'b1 && trigger_rx == 1'b1 &&
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transfer_active == 1'b1)
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else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
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sdi_data_valid <= 1'b1;
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else if (sdi_data_ready == 1'b1)
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sdi_data_valid <= 1'b0;
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@ -362,52 +365,74 @@ always @(posedge clk) begin
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if (first_bit == 1'b1)
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data_sdo_shift <= sdo_data << left_aligned;
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else
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data_shift[DATA_WIDTH:1] <= data_shift[(DATA_WIDTH-1):0];
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data_shift_1[DATA_WIDTH:1] <= data_shift_1[(DATA_WIDTH-1):0];
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data_shift_2[DATA_WIDTH:1] <= data_shift_2[(DATA_WIDTH-1):0];
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data_shift_3[DATA_WIDTH:1] <= data_shift_3[(DATA_WIDTH-1):0];
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data_shift_4[DATA_WIDTH:1] <= data_shift_4[(DATA_WIDTH-1):0];
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data_shift_5[DATA_WIDTH:1] <= data_shift_5[(DATA_WIDTH-1):0];
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data_shift_6[DATA_WIDTH:1] <= data_shift_6[(DATA_WIDTH-1):0];
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data_shift_7[DATA_WIDTH:1] <= data_shift_7[(DATA_WIDTH-1):0];
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data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
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end
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end
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assign sdo = ((inst_d1 == CMD_TRANSFER) && (sdo_enabled)) ? data_shift[DATA_WIDTH] : SDO_DEFAULT;
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assign sdo = ((inst_d1 == CMD_TRANSFER) && (sdo_enabled)) ? data_sdo_shift[DATA_WIDTH-1] : SDO_DEFAULT;
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assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[(DATA_WIDTH-1):0] :
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(NUM_OF_SDI == 2) ? {data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 3) ? {data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0],
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data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 4) ? {data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0],
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data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 5) ? {data_shift_4[(DATA_WIDTH-1):0], data_shift_3[(DATA_WIDTH-1):0],
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data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0],
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data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 6) ? {data_shift_5[(DATA_WIDTH-1):0], data_shift_4[(DATA_WIDTH-1):0],
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data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0],
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data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 7) ? {data_shift_6[(DATA_WIDTH-1):0], data_shift_5[(DATA_WIDTH-1):0],
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data_shift_4[(DATA_WIDTH-1):0], data_shift_3[(DATA_WIDTH-1):0],
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data_shift_2[(DATA_WIDTH-1):0], data_shift_1[(DATA_WIDTH-1):0],
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data_shift[(DATA_WIDTH-1):0]} :
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(NUM_OF_SDI == 8) ? {data_shift_7[(DATA_WIDTH-1):0], data_shift_6[(DATA_WIDTH-1):0],
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data_shift_5[(DATA_WIDTH-1):0], data_shift_4[(DATA_WIDTH-1):0],
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data_shift_3[(DATA_WIDTH-1):0], data_shift_2[(DATA_WIDTH-1):0],
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data_shift_1[(DATA_WIDTH-1):0], data_shift[(DATA_WIDTH-1):0]} :
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data_shift[7:0];
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// In case of an interface with high clock rate (SCLK > 50MHz), one of the
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// next SCLK edge must be used to flop the SDI line, to compensate the overall
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// delay of the read path
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reg trigger_rx_d1 = 1'b0;
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reg trigger_rx_d2 = 1'b0;
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reg trigger_rx_d3 = 1'b0;
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always @(posedge clk) begin
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if (trigger_rx == 1'b1) begin
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data_shift[0] <= sdi;
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data_shift_1[0] <= sdi_1;
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data_shift_2[0] <= sdi_2;
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data_shift_3[0] <= sdi_3;
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data_shift_4[0] <= sdi_4;
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data_shift_5[0] <= sdi_5;
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data_shift_6[0] <= sdi_6;
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data_shift_7[0] <= sdi_7;
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end
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trigger_rx_d1 <= trigger_rx;
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trigger_rx_d2 <= trigger_rx_d1;
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trigger_rx_d3 <= trigger_rx_d2;
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end
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wire trigger_rx_s = (SDI_DELAY == 2'b00) ? trigger_rx :
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(SDI_DELAY == 2'b01) ? trigger_rx_d1 :
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(SDI_DELAY == 2'b10) ? trigger_rx_d2 :
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(SDI_DELAY == 2'b11) ? trigger_rx_d3 : trigger_rx;
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always @(posedge clk) begin
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if (trigger_rx_s == 1'b1) begin
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data_sdi_shift <= {data_sdi_shift[(DATA_WIDTH-2):0], sdi};
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data_sdi_shift_1 <= {data_sdi_shift_1[(DATA_WIDTH-2):0], sdi_1};
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data_sdi_shift_2 <= {data_sdi_shift_2[(DATA_WIDTH-2):0], sdi_2};
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data_sdi_shift_3 <= {data_sdi_shift_3[(DATA_WIDTH-2):0], sdi_3};
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data_sdi_shift_4 <= {data_sdi_shift_4[(DATA_WIDTH-2):0], sdi_4};
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data_sdi_shift_5 <= {data_sdi_shift_5[(DATA_WIDTH-2):0], sdi_5};
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data_sdi_shift_6 <= {data_sdi_shift_6[(DATA_WIDTH-2):0], sdi_6};
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data_sdi_shift_7 <= {data_sdi_shift_7[(DATA_WIDTH-2):0], sdi_7};
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end
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end
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assign sdi_data = (NUM_OF_SDI == 1) ? data_sdi_shift :
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(NUM_OF_SDI == 2) ? {data_sdi_shift_1, data_sdi_shift} :
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(NUM_OF_SDI == 3) ? {data_sdi_shift_2, data_sdi_shift_1,
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data_sdi_shift} :
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(NUM_OF_SDI == 4) ? {data_sdi_shift_3, data_sdi_shift_2,
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data_sdi_shift_1, data_sdi_shift} :
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(NUM_OF_SDI == 5) ? {data_sdi_shift_4, data_sdi_shift_3,
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data_sdi_shift_2, data_sdi_shift_1,
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data_sdi_shift} :
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(NUM_OF_SDI == 6) ? {data_sdi_shift_5, data_sdi_shift_4,
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data_sdi_shift_3, data_sdi_shift_2,
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data_sdi_shift_1, data_sdi_shift} :
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(NUM_OF_SDI == 7) ? {data_sdi_shift_6, data_sdi_shift_5,
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data_sdi_shift_4, data_sdi_shift_3,
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data_sdi_shift_2, data_sdi_shift_1,
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data_sdi_shift} :
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(NUM_OF_SDI == 8) ? {data_sdi_shift_7, data_sdi_shift_6,
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data_sdi_shift_5, data_sdi_shift_4,
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data_sdi_shift_3, data_sdi_shift_2,
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data_sdi_shift_1, data_sdi_shift} : data_sdi_shift;
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wire last_sdi_bit = (sdi_counter == word_length-1);
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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sdi_counter <= 8'b0;
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end else begin
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if (trigger_rx_s == 1'b1) begin
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sdi_counter <= last_sdi_bit ? 8'b0 : sdi_counter + 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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@ -0,0 +1,6 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk
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@ -0,0 +1,31 @@
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# HDL Reference Design for EVAL-AD40XXFMCZ evaluation board
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## Product page
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http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD40XX-FMCZ.html
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## Supported parts
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* AD4000
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* AD4001
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* AD4002
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* AD4003
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* AD4004
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* AD4005
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* AD4006
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* AD4007
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* AD4008
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* AD4010
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* AD4011
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* AD4020
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@ -0,0 +1,151 @@
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad40xx_spi
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## To support the 1.8MSPS (SCLK == 100 MHz), set the spi clock to 200 MHz
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set_property -dict [list \
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CONFIG.PCW_EN_CLK2_PORT {1} \
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CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ $spi_clk_ref_frequency] [get_bd_cells sys_ps7]
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# create a SPI Engine architecture
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create_bd_cell -type hier spi_ad40xx
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current_bd_instance /spi_ad40xx
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir I -type clk spi_clk
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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# Master AXI Stream interface
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create_bd_pin -dir O m_axis_tvalid
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create_bd_pin -dir I m_axis_tready
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create_bd_pin -dir O -from 31 -to 0 m_axis_tdata
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ad_ip_instance spi_engine_execution execution
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ad_ip_parameter execution CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter execution CONFIG.NUM_OF_SDI 1
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ad_ip_parameter execution CONFIG.SDO_DEFAULT 1
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ad_ip_parameter execution CONFIG.SDI_DELAY 2
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ad_ip_instance axi_spi_engine axi
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ad_ip_parameter axi CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_ip_parameter axi CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_offload offload
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ad_ip_parameter offload CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_instance util_pulse_gen trigger_gen
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## to setup the sample rate of the system change the PULSE_PERIOD value
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## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
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set sampling_cycle [expr int(ceil(double($spi_clk_ref_frequency * 1000000) / $adc_sampling_rate))]
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ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle
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ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
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if {$adc_resolution != 16} {
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ad_ip_instance util_axis_upscale axis_upscaler
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ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS 1
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ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH $adc_resolution
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ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 32
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ad_connect axis_upscaler/dfmt_enable VCC
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ad_connect axis_upscaler/dfmt_type GND
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ad_connect axis_upscaler/dfmt_se VCC
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}
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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if {$adc_resolution != 16} {
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ad_connect offload/offload_sdi axis_upscaler/s_axis
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ad_connect axis_upscaler/m_axis_valid m_axis_tvalid
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ad_connect axis_upscaler/m_axis_ready m_axis_tready
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ad_connect axis_upscaler/m_axis_data m_axis_tdata
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ad_connect spi_clk axis_upscaler/clk
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ad_connect axi/spi_resetn axis_upscaler/resetn
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} else {
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ad_connect offload/offload_sdi_tready m_axis_tready
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ad_connect offload/offload_sdi_tvalid m_axis_tvalid
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ad_connect offload/offload_sdi_tdata m_axis_tdata
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}
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ad_connect execution/spi m_spi
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ad_connect spi_clk offload/spi_clk
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ad_connect spi_clk offload/ctrl_clk
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ad_connect spi_clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect spi_clk axi/spi_clk
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ad_connect spi_clk interconnect/clk
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ad_connect spi_clk trigger_gen/clk
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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ad_connect axi/spi_resetn trigger_gen/rstn
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ad_connect trigger_gen/load_config GND
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ad_connect trigger_gen/pulse_width GND
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ad_connect trigger_gen/pulse_period GND
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ad_connect trigger_gen/pulse offload/trigger
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ad_connect resetn axi/s_axi_aresetn
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ad_connect irq axi/irq
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current_bd_instance /
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# asynchronous SPI clock, to support higher SCLK
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ad_connect spi_clk sys_ps7/FCLK_CLK2
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# dma to receive data stream
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ad_ip_instance axi_dmac axi_ad40xx_dma
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad40xx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_2D_TRANSFER 0
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if {$adc_resolution != 16} {
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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} else {
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_SRC 16
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}
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ad_ip_parameter axi_ad40xx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi_ad40xx/clk
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ad_connect spi_clk axi_ad40xx_dma/s_axis_aclk
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ad_connect sys_cpu_resetn spi_ad40xx/resetn
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ad_connect sys_cpu_resetn axi_ad40xx_dma/m_dest_axi_aresetn
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ad_connect spi_clk spi_ad40xx/spi_clk
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ad_connect spi_ad40xx/m_spi ad40xx_spi
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## If offload is active and the DMA can not receive data, samples will be dropped
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## to ensure that every sample is the latest
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## We can achieve this by connecting the SPI Engine's AXI stream ready port to VCC
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ad_connect axi_ad40xx_dma/s_axis_valid spi_ad40xx/m_axis_tvalid
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ad_connect axi_ad40xx_dma/s_axis_data spi_ad40xx/m_axis_tdata
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ad_connect spi_ad40xx/m_axis_tready VCC
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ad_cpu_interconnect 0x44a00000 spi_ad40xx/axi
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ad_cpu_interconnect 0x44a30000 axi_ad40xx_dma
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad40xx_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" /spi_ad40xx/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_cpu_clk axi_ad40xx_dma/m_dest_axi
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := ad40xx_zed
|
||||
|
||||
M_DEPS += ../common/ad40xx_bd.tcl
|
||||
M_DEPS += ../../common/zed/zed_system_constr.xdc
|
||||
M_DEPS += ../../common/zed/zed_system_bd.tcl
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
|
||||
LIB_DEPS += axi_clkgen
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
LIB_DEPS += axi_i2s_adi
|
||||
LIB_DEPS += axi_spdif_tx
|
||||
LIB_DEPS += spi_engine/axi_spi_engine
|
||||
LIB_DEPS += spi_engine/spi_engine_execution
|
||||
LIB_DEPS += spi_engine/spi_engine_interconnect
|
||||
LIB_DEPS += spi_engine/spi_engine_offload
|
||||
LIB_DEPS += util_axis_upscale
|
||||
LIB_DEPS += util_i2c_mixer
|
||||
LIB_DEPS += util_pulse_gen
|
||||
|
||||
include ../../scripts/project-xilinx.mk
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
|
||||
# specify the spi reference clock frequency in MHz
|
||||
set spi_clk_ref_frequency 160
|
||||
|
||||
# specify ADC resolution -- supported resolutions 16/18/20 bits
|
||||
set adc_resolution 20
|
||||
|
||||
# specify ADC sampling rate in samples/seconds
|
||||
|
||||
# NOTE: This rate can be set just in turbo mode -- if turbo mode is not used
|
||||
# the max rate should be 1.6 MSPS
|
||||
set adc_sampling_rate 1800000
|
||||
|
||||
source ../common/ad40xx_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
|
||||
# ad40xx_fmc SPI interface
|
||||
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad40xx_spi_sdo] ; ## H07 FMC_LPC_LA02_P
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad40xx_spi_sdi] ; ## D08 FMC_LPC_LA01_CC_P
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad40xx_spi_sclk] ; ## G06 FMC_LPC_LA00_CC_P
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad40xx_spi_cs] ; ## G07 FMC_LPC_LA00_CC_N
|
||||
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad40xx_amp_pd] ; ## G10 FMC_LPC_LA03_N
|
||||
|
||||
# make sure that the sampling/driving flops of SDI/SCLK are near its IO ports
|
||||
|
||||
set_property IOB TRUE [get_cells -hierarchical -filter {name =~ *spi_ad40xx/execution/inst/data_sdi_shift_reg[0]}]
|
||||
set_property IOB TRUE [get_cells -hierarchical -filter {name =~ *spi_ad40xx/execution/inst/sclk_reg}]
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
# adaq400x PMOD SPI interface - the PMOD JA1 is used
|
||||
|
||||
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_sdo] ; ## JA2
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_sdi] ; ## JA3
|
||||
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_sclk] ; ## JA4
|
||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports adaq400x_spi_cs] ; ## JA1
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
## The following HDL projects supports all the devices of EVAL-AD40XX-FMCZ:
|
||||
##
|
||||
## AD4000/AD4001/AD4002/AD4003/AD4004/AD4005/AD4006/AD4007/AD4008/AD4010/AD4011/AD4020
|
||||
##
|
||||
## and also the EVAL-ADAQ400x eval board (with PMOD):
|
||||
##
|
||||
## ADAQ4003
|
||||
##
|
||||
## NOTE: Make sure that you set up your required ADC resolution and sampling rate
|
||||
## in system_bd.tcl
|
||||
|
||||
## Please select which eval board do you want to use
|
||||
##
|
||||
## 1 - EVAL-AD40XX-FMCZ
|
||||
## 0 - EVAL-ADAQ400x
|
||||
##
|
||||
set ad40xx_adaq400x_n 1
|
||||
|
||||
adi_project_xilinx ad40xx_zed
|
||||
|
||||
if {$ad40xx_adaq400x_n == 1} {
|
||||
adi_project_files ad40xx_zed [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"system_top_ad40xx.v" \
|
||||
"system_constr_ad40xx.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
|
||||
} elseif {$ad40xx_adaq400x_n == 0} {
|
||||
adi_project_files ad40xx_zed [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"system_top_adaq400x.v" \
|
||||
"system_constr_adaq400x.xdc" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
|
||||
|
||||
} else {
|
||||
return -code error [format "ERROR: Invalid eval board type! ..."]
|
||||
}
|
||||
|
||||
adi_project_run ad40xx_zed
|
||||
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
// ad400x SPI configuration interface
|
||||
|
||||
input ad40xx_spi_sdi,
|
||||
output ad40xx_spi_sdo,
|
||||
output ad40xx_spi_sclk,
|
||||
output ad40xx_spi_cs,
|
||||
|
||||
inout ad40xx_amp_pd);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:33] = 31'b0;
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(1)
|
||||
) i_admp_pd_iobuf (
|
||||
.dio_t(gpio_t[32]),
|
||||
.dio_i(gpio_o[32]),
|
||||
.dio_o(gpio_i[32]),
|
||||
.dio_p(ad40xx_amp_pd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_iobuf (
|
||||
.dio_t(gpio_t[31:0]),
|
||||
.dio_i(gpio_o[31:0]),
|
||||
.dio_o(gpio_i[31:0]),
|
||||
.dio_p(gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_scl (
|
||||
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i(iic_mux_scl_o_s),
|
||||
.dio_o(iic_mux_scl_i_s),
|
||||
.dio_p(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_sda (
|
||||
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i(iic_mux_sda_o_s),
|
||||
.dio_o(iic_mux_sda_i_s),
|
||||
.dio_p(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (),
|
||||
.spi0_csn_0_o (),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (1'b0),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.ad40xx_spi_sdo (ad40xx_spi_sdo),
|
||||
.ad40xx_spi_sdo_t (),
|
||||
.ad40xx_spi_sdi (ad40xx_spi_sdi),
|
||||
.ad40xx_spi_cs (ad40xx_spi_cs),
|
||||
.ad40xx_spi_sclk (ad40xx_spi_sclk),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
inout [14:0] ddr_addr,
|
||||
inout [ 2:0] ddr_ba,
|
||||
inout ddr_cas_n,
|
||||
inout ddr_ck_n,
|
||||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
inout ddr_we_n,
|
||||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout [31:0] gpio_bd,
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [15:0] hdmi_data,
|
||||
|
||||
output spdif,
|
||||
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
output i2s_sdata_out,
|
||||
input i2s_sdata_in,
|
||||
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
inout [ 1:0] iic_mux_scl,
|
||||
inout [ 1:0] iic_mux_sda,
|
||||
|
||||
input otg_vbusoc,
|
||||
|
||||
// adaq400x SPI configuration interface
|
||||
|
||||
input adaq400x_spi_sdi,
|
||||
output adaq400x_spi_sdo,
|
||||
output adaq400x_spi_sclk,
|
||||
output adaq400x_spi_cs);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
wire [ 1:0] iic_mux_sda_i_s;
|
||||
wire [ 1:0] iic_mux_sda_o_s;
|
||||
wire iic_mux_sda_t_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign gpio_i[63:32] = 31'b0;
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32)
|
||||
) i_iobuf (
|
||||
.dio_t(gpio_t[31:0]),
|
||||
.dio_i(gpio_o[31:0]),
|
||||
.dio_o(gpio_i[31:0]),
|
||||
.dio_p(gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_scl (
|
||||
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
|
||||
.dio_i(iic_mux_scl_o_s),
|
||||
.dio_o(iic_mux_scl_i_s),
|
||||
.dio_p(iic_mux_scl));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(2)
|
||||
) i_iic_mux_sda (
|
||||
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
|
||||
.dio_i(iic_mux_sda_o_s),
|
||||
.dio_o(iic_mux_sda_i_s),
|
||||
.dio_p(iic_mux_sda));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
.i2s_sdata_in (i2s_sdata_in),
|
||||
.i2s_sdata_out (i2s_sdata_out),
|
||||
.iic_fmc_scl_io (iic_scl),
|
||||
.iic_fmc_sda_io (iic_sda),
|
||||
.iic_mux_scl_i (iic_mux_scl_i_s),
|
||||
.iic_mux_scl_o (iic_mux_scl_o_s),
|
||||
.iic_mux_scl_t (iic_mux_scl_t_s),
|
||||
.iic_mux_sda_i (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_o (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_t (iic_mux_sda_t_s),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (),
|
||||
.spi0_csn_0_o (),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (1'b0),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o (),
|
||||
.ad40xx_spi_sdo (adaq400x_spi_sdo),
|
||||
.ad40xx_spi_sdo_t (),
|
||||
.ad40xx_spi_sdi (adaq400x_spi_sdi),
|
||||
.ad40xx_spi_cs (adaq400x_spi_cs),
|
||||
.ad40xx_spi_sclk (adaq400x_spi_sclk),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue