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axi_jesd_gt: changed clock and reset naming to be consistent with the other projects

main
AndreiGrozav 2016-03-15 11:20:31 +02:00
parent 06b7916303
commit 9b2a106aa0
2 changed files with 5 additions and 14 deletions
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8
library/axi_jesd_gt/axi_jesd_gt.v
View File

@ -668,8 +668,8 @@ module axi_jesd_gt #(
// axi - clock & reset
input axi_aclk,
input axi_aresetn,
input s_axi_aclk,
input s_axi_aresetn,
// axi interface
@ -831,8 +831,8 @@ module axi_jesd_gt #(
// signal name changes
assign up_rstn = axi_aresetn;
assign up_clk = axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// pll

11
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
View File

@ -24,16 +24,7 @@ adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \
"axi_jesd_gt_constr.xdc" ]
ipx::remove_bus_interface qpll0_rst [ipx::current_core]
ipx::remove_bus_interface qpll1_rst [ipx::current_core]
set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_aclk \
-of_objects [ipx::current_core]]]
set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \
-of_objects [ipx::get_bus_interfaces axi_aclk \
-of_objects [ipx::current_core]]]
ipx::associate_bus_interfaces -busif m_axi -clock s_axi_aclk [ipx::current_core]
adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
"qpll_rst qpll0_rst "\