fmcjesdadc1: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization that the old util_cpack and util_upack cores. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
Adrian Costina
parent
1d223c19f8
commit
9b919636ca
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@ -20,10 +20,17 @@ ad_ip_parameter data_bsplit CONFIG.NUM_OF_CHANNELS 2
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ad_ip_instance axi_ad9250 axi_ad9250_0_core
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ad_ip_instance axi_ad9250 axi_ad9250_1_core
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ad_ip_instance util_cpack axi_ad9250_0_cpack
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ad_ip_parameter axi_ad9250_0_cpack CONFIG.NUM_OF_CHANNELS 2
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ad_ip_instance util_cpack axi_ad9250_1_cpack
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ad_ip_parameter axi_ad9250_1_cpack CONFIG.NUM_OF_CHANNELS 2
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ad_ip_instance util_cpack2 axi_ad9250_0_cpack { \
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NUM_OF_CHANNELS 2 \
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SAMPLES_PER_CHANNEL 2 \
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SAMPLE_DATA_WIDTH 16 \
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}
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ad_ip_instance util_cpack2 axi_ad9250_1_cpack { \
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NUM_OF_CHANNELS 2 \
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SAMPLES_PER_CHANNEL 2 \
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SAMPLE_DATA_WIDTH 16 \
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}
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ad_ip_instance axi_dmac axi_ad9250_0_dma
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ad_ip_parameter axi_ad9250_0_dma CONFIG.DMA_TYPE_SRC 2
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@ -84,44 +91,28 @@ create_bd_port -dir O rx_core_clk
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# connections (adc)
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ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 rx_core_clk
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ad_connect axi_ad9250_jesd/rx_sof axi_ad9250_0_core/rx_sof
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
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ad_connect axi_ad9250_jesd/rx_sof axi_ad9250_1_core/rx_sof
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ad_connect axi_ad9250_jesd/rx_data_tdata data_bsplit/data
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ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0
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ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk
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ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst
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ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst
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for {set i 0} {$i < 2} {incr i} {
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_${i}_core/rx_clk
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ad_connect axi_ad9250_jesd/rx_sof axi_ad9250_${i}_core/rx_sof
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ad_connect axi_ad9250_${i}_core/rx_data data_bsplit/split_data_${i}
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ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0
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ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0
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ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0
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ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1
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ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1
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ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1
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ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0
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ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0
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ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0
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ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1
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ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1
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ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1
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ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_${i}_cpack/clk
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ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_${i}_cpack/reset
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ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
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ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid
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ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync
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ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data
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ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
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ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
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ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid
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ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync
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ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data
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ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
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ad_connect axi_ad9250_${i}_core/adc_dovf axi_ad9250_${i}_cpack/fifo_wr_overflow
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ad_connect axi_ad9250_${i}_core/adc_valid_a axi_ad9250_${i}_cpack/fifo_wr_en
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ad_connect axi_ad9250_${i}_core/adc_enable_a axi_ad9250_${i}_cpack/enable_0
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ad_connect axi_ad9250_${i}_core/adc_data_a axi_ad9250_${i}_cpack/fifo_wr_data_0
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ad_connect axi_ad9250_${i}_core/adc_enable_b axi_ad9250_${i}_cpack/enable_1
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ad_connect axi_ad9250_${i}_core/adc_data_b axi_ad9250_${i}_cpack/fifo_wr_data_1
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ad_connect axi_ad9250_${i}_core/adc_clk axi_ad9250_${i}_dma/fifo_wr_clk
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ad_connect axi_ad9250_${i}_dma/fifo_wr axi_ad9250_${i}_cpack/packed_fifo_wr
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}
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# interconnect (cpu)
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@ -19,7 +19,7 @@ LIB_DEPS += axi_dmac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += util_bsplit
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LIB_DEPS += util_cpack
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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@ -19,7 +19,7 @@ LIB_DEPS += axi_dmac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += util_bsplit
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LIB_DEPS += util_cpack
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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@ -21,7 +21,7 @@ LIB_DEPS += axi_spdif_tx
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += util_bsplit
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LIB_DEPS += util_cpack
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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