docs: Add ad7768 documentation (#1283)
docs: Add ad7768 documentation Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>main
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.. _ad7768evb:
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AD7768-EVB HDL project
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====================================================================================
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Overview
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------------------------------------------------------------------------------------
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The :adi:`EVAL-AD7768FMCZ` / :adi:`EVAL-AD7768-4FMCZ` evaluation kit features the
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:adi:`AD7768` / :adi:`AD7768-4` 24-bit, 256 kSPS, analog-to-digital converter (ADC).
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A 7 V to 9 V external bench top supply is regulated to 5 V and 3.3 V to supply the
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:adi:`AD7768` / :adi:`AD7768-4` and support components.
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The :adi:`AD7768` / :adi:`AD7768-4` are 8-channel and 4-channel simultaneous
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sampling sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), respectively, with a
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Σ-Δ modulator and digital filter per channel, enabling synchronized sampling of ac
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and dc signals. The :adi:`AD7768` / :adi:`AD7768-4` achieve 108 dB dynamic range at
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a maximum input bandwidth of 110.8 kHz, combined with typical performance of ±2 ppm
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integral nonlinearity (INL), ±50 μV offset error, and ±30 ppm gain error.
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The :adi:`AD7768` / :adi:`AD7768-4` user can trade off input bandwidth, output data
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rate, and power dissipation, and select one of three power modes to optimize for
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noise targets and power consumption. The flexibility of the
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:adi:`AD7768` / :adi:`AD7768-4` allows it to become a reusable platform for low
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power dc and high performance ac measurement module.
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The :adi:`AD7768` / :adi:`AD7768-4` has three modes: fast mode (256 kSPS maximum,
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110.8 kHz input bandwidth, 51.5 mW per channel), median mode (128 kSPS maximum,
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55.4 kHz input bandwidth, 27.5 mW per channel) and low power mode (32 kSPS maximum,
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13.8 kHz input bandwidth, 9.375 mW per channel). The :adi:`AD7768` / :adi:`AD7768-4`
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offers extensive digital filtering capabilities, such as a wideband, low ±0.005 dB
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pass-band ripple, antialiasing low-pass filter with sharp roll-off, and 105 dB
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attenuation at the Nyquist frequency. Frequency domain measurements can use the
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wideband linear phase filter. This filter has a flat pass band (±0.005 dB ripple)
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from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at 128 kSPS, or from dc to
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12.8 kHz at 32 kSPS.
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The :adi:`AD7768` / :adi:`AD7768-4` also offers sinc response via a sinc5 filter,
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a low latency path for low bandwidth, and low noise measurements. The wideband and
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sinc5 filters can be selected and run on a per channel basis. Within these filter
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options, the user can improve the dynamic range by selecting from decimation rates
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of ×32, ×64, ×128, ×256, ×512, and ×1024. The ability to vary the decimation
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filtering optimizes noise performance to the required input bandwidth. Embedded
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analog functionality on each ADC channel makes design easier, such as a precharge
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buffer on each analog input that reduces analog input current and a precharge
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reference buffer per channel reduces input current and glitches on the reference
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input terminals.
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The device operates with a 5 V AVDD1A and AVDD1B supply, a 2.25 V to 5.0 V AVDD2A
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and AVDD2B supply, and a 2.5 V to 3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD
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Operation section for specific requirements for operating at 1.8 V IOVDD).
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The device requires an external reference; the absolute input reference voltage
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range is 1 V to AVDD1 − AVSS. The specified operating temperature range is −40°C
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to +105°C. The device is housed in a 10 mm × 10 mm 64-lead LQFP package with a
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12 mm × 12 mm printed circuit board (PCB) footprint.
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD7768 <EVAL-AD7768>`
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- :adi:`EVAL-AD7768-4 <EVAL-AD7768-4>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD7768`
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- :adi:`AD7768-4`
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Supported carriers
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---------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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AD7768-EVB
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. image:: ad7768evb_fmc_hdl.svg
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:width: 800
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:align: center
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:alt: AD7768-EVB block diagram
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Jumper setup
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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================== ========= ======================================
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Jumper/Solder link Position Description
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================== ========= ======================================
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LK1 B LK1 selects the input voltage source.
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Position B: J1 is selected.
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LK2 B Position B: external power supply from
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either J1 or J3.
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SL4A B Crystal oscillator or LVDS option.
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================== ========= ======================================
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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========================= ===========
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Instance Address
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========================= ===========
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axi_ad7768_adc 0x43C0_0000
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ad7768_dma 0x7C40_0000
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ad7768_dma_2 0x7C48_0000
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========================= ===========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* - PL
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- iic_fmc
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- axi_iic_fmc
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- 0x4162_0000
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- ---
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* - PL
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- iic_main
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- axi_iic_main
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- 0x4160_0000
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- ---
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - gpio_1_mode_3
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- INOUT
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- 51
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- 105
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* - gpio_1_mode_2
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- INOUT
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- 50
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- 104
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* - gpio_1_mode_1
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- INOUT
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- 49
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- 103
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* - gpio_0_mode_0
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- INOUT
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- 48
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- 102
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* - reset_n
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- OUT
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- 32
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- 86
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=============== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=============== === ========== ===========
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ad7768_dma 13 57 89
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ad7768_dma_2 10 54 87
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=============== === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/ad7768evb/zed
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user@analog:~/hdl/projects/ad7768evb/zed$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Resources
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-------------------------------------------------------------------------------
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets:
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- :adi:`AD7768`
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- :adi:`AD7768-4`
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- :adi:`UG-917, Evaluation Board User Guide <media/en/technical-documentation/user-guides/EVAL-AD7768FMCZ_UG-917.pdf>`
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- :adi:`UG-921, Evaluation Board User Guide <media/en/technical-documentation/user-guides/EVAL-AD7768-4FMCZ-UG-921.pdf>`
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD7768-EVB HDL project source code <projects/ad7768evb>`
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- :dokuwiki:`[Wiki] AD7768-EVB Bare Metal Quick Start Guide <resources/eval/user-guides/ad7768-ebz/software/baremetal>`
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- :dokuwiki:`[Wiki] AXI_AD7768 <resources/fpga/docs/ad7768>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_AD7768
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- :git-hdl:`library/axi_ad7768 <library/axi_ad7768>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/ad7768>`
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
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- ---
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* - AXI_SPDIF_TX
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
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- ---
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid <library/axi_sysid>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - SYSID_ROM
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- :git-hdl:`library/sysid_rom <library/sysid_rom>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_I2C_MIXER
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- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
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- ---
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* - UTIL_CPACK2
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- :git-hdl:`library/util_pack/util_cpack2 <library/util_pack/util_cpack2>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/util_cpack>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-linux:`AD7768 Linux driver source code <drivers/iio/adc/ad7768.c>`
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- :git-no-os:`AD7768 No-OS project source code <projects/ad7768-evb>`
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- :dokuwiki:`[Wiki] AD7768 IIO Precision ADC Linux Driver <resources/tools-software/linux-drivers/iio-adc/ad7768>`
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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@ -26,6 +26,7 @@ Contents
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AD719X-ASDZ <ad719x_asdz/index>
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AD738X-FMC <ad738x_fmc/index>
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AD7616-SDZ <ad7616_sdz/index>
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AD7768-EVB <ad7768evb/index>
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AD9081-FMCA-EBZ/AD9082-FMCA-EBZ <ad9081_fmca_ebz/index>
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AD9434-FMC <ad9434_fmc/index>
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AD9783-EBZ <ad9783_ebz/index>
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