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axi_ad7616: Remove serial dependencies

main
Stanca Pop 2022-03-16 13:26:12 +02:00 committed by StancaPop
parent 03c4276a2b
commit 9ba84cf7c0
5 changed files with 29 additions and 434 deletions
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7
library/axi_ad7616/Makefile
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@ -6,18 +6,11 @@
LIBRARY_NAME := axi_ad7616
GENERIC_DEPS += ../common/ad_edge_detect.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += axi_ad7616.v
GENERIC_DEPS += axi_ad7616_control.v
GENERIC_DEPS += axi_ad7616_maxis2wrfifo.v
GENERIC_DEPS += axi_ad7616_pif.v
XILINX_DEPS += axi_ad7616_ip.tcl
XILINX_LIB_DEPS += spi_engine/axi_spi_engine
XILINX_LIB_DEPS += spi_engine/spi_engine_execution
XILINX_LIB_DEPS += spi_engine/spi_engine_interconnect
XILINX_LIB_DEPS += spi_engine/spi_engine_offload
include ../scripts/library.mk

273
library/axi_ad7616/axi_ad7616.v
View File

@ -37,17 +37,12 @@
module axi_ad7616 #(
parameter ID = 0,
parameter IF_TYPE = 1
parameter ID = 0
) (
// physical data interface
output rx_sclk,
output rx_cs_n,
output rx_sdo,
input [ 1:0] rx_sdi,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
@ -56,8 +51,7 @@ module axi_ad7616 #(
// physical control interface
output rx_cnvst,
input rx_busy,
input rx_trigger,
// AXI Slave Memory Map
@ -87,16 +81,9 @@ module axi_ad7616 #(
output adc_valid,
output [15:0] adc_data,
output adc_sync,
output irq
output adc_sync
);
localparam NUM_OF_SDI = 2;
localparam SERIAL = 0;
localparam PARALLEL = 1;
localparam NEG_EDGE = 1;
// internal registers
reg up_wack = 1'b0;
@ -114,9 +101,6 @@ module axi_ad7616 #(
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_if_s;
wire up_rack_if_s;
wire [31:0] up_rdata_if_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
@ -129,10 +113,6 @@ module axi_ad7616 #(
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [ 4:0] burst_length_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
// defaults
@ -148,242 +128,12 @@ module axi_ad7616 #(
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_if_s | up_wack_cntrl_s;
up_rack <= up_rack_if_s | up_rack_cntrl_s;
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
up_wack <= up_wack_cntrl_s;
up_rack <= up_rack_cntrl_s;
up_rdata <= up_rdata_cntrl_s;
end
end
generate if (IF_TYPE == SERIAL) begin
// ground all parallel interface signals
assign rx_db_o = 16'b0;
assign rx_rd_n = 1'b0;
assign rx_wr_n = 1'b0;
// SPI Framework instances and logic
wire spi_resetn_s;
wire s0_cmd_ready_s;
wire s0_cmd_valid_s;
wire [15:0] s0_cmd_data_s;
wire s0_sdo_data_ready_s;
wire s0_sdo_data_valid_s;
wire [ 7:0] s0_sdo_data_s;
wire s0_sdi_data_ready_s;
wire s0_sdi_data_valid_s;
wire [15:0] s0_sdi_data_s;
wire s0_sync_ready_s;
wire s0_sync_valid_s;
wire [ 7:0] s0_sync_s;
wire s1_cmd_ready_s;
wire s1_cmd_valid_s;
wire [15:0] s1_cmd_data_s;
wire s1_sdo_data_ready_s;
wire s1_sdo_data_valid_s;
wire [ 7:0] s1_sdo_data_s;
wire s1_sdi_data_ready_s;
wire s1_sdi_data_valid_s;
wire [15:0] s1_sdi_data_s;
wire s1_sync_ready_s;
wire s1_sync_valid_s;
wire [ 7:0] s1_sync_s;
wire m_cmd_ready_s;
wire m_cmd_valid_s;
wire [15:0] m_cmd_data_s;
wire m_sdo_data_ready_s;
wire m_sdo_data_valid_s;
wire [7:0] m_sdo_data_s;
wire m_sdi_data_ready_s;
wire m_sdi_data_valid_s;
wire [15:0] m_sdi_data_s;
wire m_sync_ready_s;
wire m_sync_valid_s;
wire [ 7:0] m_sync_s;
wire offload0_cmd_wr_en_s;
wire [15:0] offload0_cmd_wr_data_s;
wire offload0_sdo_wr_en_s;
wire [ 7:0] offload0_sdo_wr_data_s;
wire offload0_mem_reset_s;
wire offload0_enable_s;
wire offload0_enabled_s;
wire offload_sync_ready_s;
wire offload_sync_valid_s;
wire [ 7:0] offload_sync_data_s;
axi_spi_engine #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI),
.NUM_OFFLOAD(1),
.MM_IF_TYPE(1)
) i_axi_spi_engine (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_if_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_if_s),
.up_rack (up_rack_if_s),
.irq (irq),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.cmd_ready (s0_cmd_ready_s),
.cmd_valid (s0_cmd_valid_s),
.cmd_data (s0_cmd_data_s),
.sdo_data_ready (s0_sdo_data_ready_s),
.sdo_data_valid (s0_sdo_data_valid_s),
.sdo_data (s0_sdo_data_s),
.sdi_data_ready (s0_sdi_data_ready_s),
.sdi_data_valid (s0_sdi_data_valid_s),
.sdi_data (s0_sdi_data_s),
.sync_ready (s0_sync_ready_s),
.sync_valid (s0_sync_valid_s),
.sync_data (s0_sync_s),
.offload_sync_ready (offload_sync_ready_s),
.offload_sync_valid (offload_sync_valid_s),
.offload_sync_data (offload_sync_data_s),
.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
.offload0_mem_reset (offload0_mem_reset_s),
.offload0_enable (offload0_enable_s),
.offload0_enabled(offload0_enabled_s));
spi_engine_offload #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_offload (
.ctrl_clk (up_clk),
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
.ctrl_enable (offload0_enable_s),
.ctrl_enabled (offload0_enabled_s),
.ctrl_mem_reset (offload0_mem_reset_s),
.spi_clk (up_clk),
.spi_resetn (spi_resetn_s),
.trigger (trigger_s),
.cmd_valid (s1_cmd_valid_s),
.cmd_ready (s1_cmd_ready_s),
.cmd (s1_cmd_data_s),
.sdo_data_valid (s1_sdo_data_valid_s),
.sdo_data_ready (s1_sdo_data_ready_s),
.sdo_data (s1_sdo_data_s),
.sdi_data_valid (s1_sdi_data_valid_s),
.sdi_data_ready (s1_sdi_data_ready_s),
.sdi_data (s1_sdi_data_s),
.sync_valid (s1_sync_valid_s),
.sync_ready (s1_sync_ready_s),
.sync_data (s1_sync_s),
.status_sync_ready (offload_sync_ready_s),
.status_sync_valid (offload_sync_valid_s),
.status_sync_data (offload_sync_data_s),
.offload_sdi_valid (m_axis_valid_s),
.offload_sdi_ready (m_axis_ready_s),
.offload_sdi_data (m_axis_data_s));
spi_engine_interconnect #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_interconnect (
.clk (up_clk),
.resetn (spi_resetn_s),
.m_cmd_valid (m_cmd_valid_s),
.m_cmd_ready (m_cmd_ready_s),
.m_cmd_data (m_cmd_data_s),
.m_sdo_valid (m_sdo_data_valid_s),
.m_sdo_ready (m_sdo_data_ready_s),
.m_sdo_data (m_sdo_data_s),
.m_sdi_valid (m_sdi_data_valid_s),
.m_sdi_ready (m_sdi_data_ready_s),
.m_sdi_data (m_sdi_data_s),
.m_sync_valid (m_sync_valid_s),
.m_sync_ready (m_sync_ready_s),
.m_sync (m_sync_s),
.s0_cmd_valid (s0_cmd_valid_s),
.s0_cmd_ready (s0_cmd_ready_s),
.s0_cmd_data (s0_cmd_data_s),
.s0_sdo_valid (s0_sdo_data_valid_s),
.s0_sdo_ready (s0_sdo_data_ready_s),
.s0_sdo_data (s0_sdo_data_s),
.s0_sdi_valid (s0_sdi_data_valid_s),
.s0_sdi_ready (s0_sdi_data_ready_s),
.s0_sdi_data (s0_sdi_data_s),
.s0_sync_valid (s0_sync_valid_s),
.s0_sync_ready (s0_sync_ready_s),
.s0_sync (s0_sync_s),
.s1_cmd_valid (s1_cmd_valid_s),
.s1_cmd_ready (s1_cmd_ready_s),
.s1_cmd_data (s1_cmd_data_s),
.s1_sdo_valid (s1_sdo_data_valid_s),
.s1_sdo_ready (s1_sdo_data_ready_s),
.s1_sdo_data (s1_sdo_data_s),
.s1_sdi_valid (s1_sdi_data_valid_s),
.s1_sdi_ready (s1_sdi_data_ready_s),
.s1_sdi_data (s1_sdi_data_s),
.s1_sync_valid (s1_sync_valid_s),
.s1_sync_ready (s1_sync_ready_s),
.s1_sync (s1_sync_s));
spi_engine_execution #(
.DATA_WIDTH (8),
.NUM_OF_SDI (NUM_OF_SDI)
) i_spi_engine_execution (
.clk (up_clk),
.resetn (spi_resetn_s),
.active (),
.cmd_ready (m_cmd_ready_s),
.cmd_valid (m_cmd_valid_s),
.cmd (m_cmd_data_s),
.sdo_data_valid (m_sdo_data_valid_s),
.sdo_data_ready (m_sdo_data_ready_s),
.sdo_data (m_sdo_data_s),
.sdi_data_ready (m_sdi_data_ready_s),
.sdi_data_valid (m_sdi_data_valid_s),
.sdi_data (m_sdi_data_s),
.sync_ready (m_sync_ready_s),
.sync_valid (m_sync_valid_s),
.sync (m_sync_s),
.sclk (rx_sclk),
.sdo (rx_sdo),
.sdo_t (),
.sdi (rx_sdi),
.cs (rx_cs_n),
.three_wire ());
axi_ad7616_maxis2wrfifo #(
.DATA_WIDTH(16)
) i_maxis2wrfifo (
.clk(up_clk),
.rstn(up_rstn),
.sync_in(trigger_s),
.m_axis_data(m_axis_data_s),
.m_axis_ready(m_axis_ready_s),
.m_axis_valid(m_axis_valid_s),
.fifo_wr_en(adc_valid),
.fifo_wr_data(adc_data),
.fifo_wr_sync(adc_sync),
.fifo_wr_xfer_req(1'b1));
end
endgenerate
generate if (IF_TYPE == PARALLEL) begin
assign rx_sclk = 1'h0;
assign rx_sdo = 1'h0;
assign irq = 1'h0;
assign up_wack_if_s = 1'h0;
assign up_rack_if_s = 1'h0;
assign up_rdata_if_s = 1'h0;
axi_ad7616_pif i_ad7616_parallel_interface (
.cs_n (rx_cs_n),
.db_o (rx_db_o),
@ -394,7 +144,7 @@ module axi_ad7616 #(
.adc_data (adc_data),
.adc_valid (adc_valid),
.adc_sync (adc_sync),
.end_of_conv (trigger_s),
.end_of_conv (rx_trigger),
.burst_length(burst_length_s),
.clk (up_clk),
.rstn (up_rstn),
@ -404,22 +154,15 @@ module axi_ad7616 #(
.rd_data (rd_data_s),
.rd_valid (rd_valid_s));
end
endgenerate
axi_ad7616_control #(
.ID(ID),
.IF_TYPE(IF_TYPE)
.ID(ID)
) i_ad7616_control (
.cnvst (rx_cnvst),
.busy (rx_busy),
.up_burst_length (burst_length_s),
.up_read_data (rd_data_s),
.up_read_valid (rd_valid_s),
.up_write_data (wr_data_s),
.up_read_req (rd_req_s),
.up_write_req (wr_req_s),
.end_of_conv (trigger_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),

56
library/axi_ad7616/axi_ad7616_control.v
View File

@ -37,15 +37,11 @@
module axi_ad7616_control #(
parameter ID = 0,
parameter IF_TYPE = 0
parameter ID = 0
) (
// control signals
output cnvst,
input busy,
input [15:0] up_read_data,
input up_read_valid,
output reg [15:0] up_write_data,
@ -53,7 +49,6 @@ module axi_ad7616_control #(
output up_write_req,
output reg [ 4:0] up_burst_length,
output end_of_conv,
// bus interface
@ -72,8 +67,6 @@ module axi_ad7616_control #(
localparam PCORE_VERSION = 'h00001002;
localparam POS_EDGE = 0;
localparam NEG_EDGE = 1;
localparam SERIAL = 0;
localparam PARALLEL = 1;
// internal signals
@ -96,8 +89,8 @@ module axi_ad7616_control #(
// the up_[read/write]_data interfaces are valid just in parallel mode
assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
assign up_read_valid_s = up_read_valid;
assign up_read_data_s = {16'h0, up_read_data};
// processor write interface
@ -149,7 +142,6 @@ module axi_ad7616_control #(
9'h100 : up_rdata <= PCORE_VERSION;
9'h101 : up_rdata <= ID;
9'h102 : up_rdata <= up_scratch;
9'h103 : up_rdata <= IF_TYPE;
9'h110 : up_rdata <= {29'b0, up_cnvst_en, up_resetn};
9'h111 : up_rdata <= up_conv_rate;
9'h112 : up_rdata <= {27'b0, up_burst_length};
@ -164,46 +156,4 @@ module axi_ad7616_control #(
assign up_rst = ~up_rstn;
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (up_clk),
.rst (up_rst),
.signal_in (busy),
.signal_out (end_of_conv));
// convertion start generator
// NOTE: + The minimum convertion cycle is 1 us
// + The rate of the cnvst must be defined in a way,
// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
// See the AD7616 datasheet for more information.
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
cnvst_counter <= 32'b0;
end else begin
cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
end
end
always @(cnvst_counter, up_conv_rate) begin
cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
end
always @(posedge up_clk) begin
if(up_resetn == 1'b0) begin
pulse_counter <= 3'b0;
cnvst_buf <= 1'b0;
end else begin
pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
if(cnvst_pulse == 1'b1) begin
cnvst_buf <= 1'b1;
end else if (pulse_counter[2] == 1'b1) begin
cnvst_buf <= 1'b0;
end
end
end
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
endmodule

9
library/axi_ad7616/axi_ad7616_ip.tcl
View File

@ -11,24 +11,15 @@ global VIVADO_IP_LIBRARY
adi_ip_create axi_ad7616
adi_ip_files axi_ad7616 [list \
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad7616_control.v" \
"axi_ad7616_pif.v" \
"axi_ad7616_maxis2wrfifo.v" \
"axi_ad7616.v" ]
adi_ip_properties axi_ad7616
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core]
adi_ip_add_core_dependencies [list \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_execution:1.0 \
analog.com:$VIVADO_IP_LIBRARY:axi_spi_engine:1.0 \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_offload:1.0 \
analog.com:$VIVADO_IP_LIBRARY:spi_engine_interconnect:1.0 \
]
set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
ipx::save_core [ipx::current_core]

82
library/axi_ad7616/axi_ad7616_maxis2wrfifo.v
View File

@ -1,82 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7616_maxis2wrfifo #(
parameter DATA_WIDTH = 16
) (
input clk,
input rstn,
input sync_in,
// m_axis interface
input [DATA_WIDTH-1:0] m_axis_data,
output reg m_axis_ready,
input m_axis_valid,
output reg m_axis_xfer_req,
// write fifo interface
output reg fifo_wr_en,
output reg [DATA_WIDTH-1:0] fifo_wr_data,
output reg fifo_wr_sync,
input fifo_wr_xfer_req
);
always @(posedge clk) begin
if (rstn == 1'b0) begin
m_axis_ready <= 1'b0;
m_axis_xfer_req <= 1'b0;
fifo_wr_data <= 'b0;
fifo_wr_en <= 1'b0;
fifo_wr_sync <= 1'b0;
end else begin
m_axis_ready <= 1'b1;
m_axis_xfer_req <= fifo_wr_xfer_req;
fifo_wr_data <= m_axis_data;
fifo_wr_en <= m_axis_valid;
if (sync_in == 1'b1) begin
fifo_wr_sync <= 1'b1;
end else if ((m_axis_valid == 1'b1) &&
(fifo_wr_sync == 1'b1)) begin
fifo_wr_sync <= 1'b0;
end
end
end
endmodule