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axi_dac_interpolate: Initial commit

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Adrian Costina 2017-01-31 16:22:49 +02:00
parent 4a7232cbcb
commit 9c975211da
7 changed files with 1577 additions and 0 deletions
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53
library/axi_dac_interpolate/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_dac_interpolate.v
M_DEPS += axi_dac_interpolate_constr.xdc
M_DEPS += axi_dac_interpolate_ip.tcl
M_DEPS += axi_dac_interpolate_reg.v
M_DEPS += cic_interp.v
M_DEPS += fir_interp.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_dac_interpolate.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_dac_interpolate.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_dac_interpolate_ip.tcl >> axi_dac_interpolate_ip.log 2>&1
####################################################################################
####################################################################################

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library/axi_dac_interpolate/axi_dac_interpolate.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dac_interpolate(
input dac_clk,
input [15:0] dac_data_a,
input [15:0] dac_data_b,
input dac_valid_a,
input dac_valid_b,
output reg [15:0] dac_int_data_a,
output reg [15:0] dac_int_data_b,
output reg dac_int_valid_a,
output reg dac_int_valid_b,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal signals
wire up_clk;
wire up_rstn;
wire [13:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [13:0] up_raddr;
wire [31:0] interpolation_ratio_a;
wire [31:0] interpolation_ratio_b;
wire [31:0] filter_mask_a;
wire [31:0] filter_mask_b;
wire dac_fir_valid_a;
wire [35:0] dac_fir_data_a;
wire dac_fir_valid_b;
wire [35:0] dac_fir_data_b;
wire dac_cic_valid_a;
wire [109:0] dac_cic_data_a;
wire dac_cic_valid_b;
wire [109:0] dac_cic_data_b;
wire dma_transfer_suspend;
reg dac_filt_int_valid_a;
reg dac_filt_int_valid_b;
reg [15:0] interp_rate_cic_a;
reg [15:0] interp_rate_cic_b;
reg [31:0] filter_mask_a_d1;
reg [31:0] filter_mask_b_d1;
reg cic_change_rate_a;
reg cic_change_rate_b;
reg [31:0] interpolation_counter_a;
reg [31:0] interpolation_counter_b;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(dac_clk), .rst(dac_rst));
fir_interp fir_interpolation_a (
.clk (dac_clk),
.clk_enable (dac_cic_valid_a),
.reset (dac_rst | dma_transfer_suspend),
.filter_in (dac_data_a),
.filter_out (dac_fir_data_a),
.ce_out (dac_fir_valid_a));
fir_interp fir_interpolation_b (
.clk (dac_clk),
.clk_enable (dac_cic_valid_b),
.reset (dac_rst | dma_transfer_suspend),
.filter_in (dac_data_b),
.filter_out (dac_fir_data_b),
.ce_out (dac_fir_valid_b));
cic_interp cic_interpolation_a (
.clk (dac_clk),
.clk_enable (dac_valid_a),
.reset (dac_rst | cic_change_rate_a | dma_transfer_suspend),
.rate (interp_rate_cic_a),
.load_rate (1'b0),
.filter_in (dac_fir_data_a[30:0]),
.filter_out (dac_cic_data_a),
.ce_out (dac_cic_valid_a));
cic_interp cic_interpolation_b (
.clk (dac_clk),
.clk_enable (dac_valid_b),
.reset (dac_rst | cic_change_rate_b | dma_transfer_suspend),
.rate (interp_rate_cic_b),
.load_rate (1'b0),
.filter_in (dac_fir_data_b[30:0]),
.filter_out (dac_cic_data_b),
.ce_out (dac_cic_valid_b));
always @(posedge dac_clk) begin
filter_mask_a_d1 <= filter_mask_a;
filter_mask_b_d1 <= filter_mask_b;
if (filter_mask_a_d1 != filter_mask_a) begin
cic_change_rate_a <= 1'b1;
end else begin
cic_change_rate_a <= 1'b0;
end
if (filter_mask_b_d1 != filter_mask_b) begin
cic_change_rate_b <= 1'b1;
end else begin
cic_change_rate_b <= 1'b0;
end
end
always @(posedge dac_clk) begin
if (interpolation_ratio_a == 0 || interpolation_ratio_a == 1) begin
dac_int_valid_a <= dac_filt_int_valid_a;
end else begin
if (dac_filt_int_valid_a == 1'b1) begin
if (interpolation_counter_a < interpolation_ratio_a) begin
interpolation_counter_a <= interpolation_counter_a + 1;
dac_int_valid_a <= 1'b0;
end else begin
interpolation_counter_a <= 0;
dac_int_valid_a <= 1'b1;
end
end else begin
dac_int_valid_a <= 1'b0;
end
end
end
always @(posedge dac_clk) begin
if (interpolation_ratio_b == 0 || interpolation_ratio_b == 1) begin
dac_int_valid_b <= dac_filt_int_valid_b;
end else begin
if (dac_filt_int_valid_b == 1'b1) begin
if (interpolation_counter_b < interpolation_ratio_b) begin
interpolation_counter_b <= interpolation_counter_b + 1;
dac_int_valid_b <= 1'b0;
end else begin
interpolation_counter_b <= 0;
dac_int_valid_b <= 1'b1;
end
end else begin
dac_int_valid_b <= 1'b0;
end
end
end
always @(*) begin
case (filter_mask_a)
16'h1: dac_int_data_a = dac_cic_data_a[31:16];
16'h2: dac_int_data_a = dac_cic_data_a[31:16];
16'h3: dac_int_data_a = dac_cic_data_a[31:16];
16'h6: dac_int_data_a = dac_cic_data_a[31:16];
16'h7: dac_int_data_a = dac_cic_data_a[31:16];
default: dac_int_data_a = dac_data_a;
endcase
case (filter_mask_a)
16'h1: dac_filt_int_valid_a = dac_fir_valid_a;
16'h2: dac_filt_int_valid_a = dac_fir_valid_a;
16'h3: dac_filt_int_valid_a = dac_fir_valid_a;
16'h6: dac_filt_int_valid_a = dac_fir_valid_a;
16'h7: dac_filt_int_valid_a = dac_fir_valid_a;
default: dac_filt_int_valid_a = dac_valid_a & !dma_transfer_suspend;
endcase
case (filter_mask_b)
16'h1: dac_int_data_b = dac_cic_data_b[31:16];
16'h2: dac_int_data_b = dac_cic_data_b[31:16];
16'h3: dac_int_data_b = dac_cic_data_b[31:16];
16'h6: dac_int_data_b = dac_cic_data_b[31:16];
16'h7: dac_int_data_b = dac_cic_data_b[31:16];
default: dac_int_data_b = dac_data_b;
endcase
case (filter_mask_b)
16'h1: dac_filt_int_valid_b = dac_fir_valid_b;
16'h2: dac_filt_int_valid_b = dac_fir_valid_b;
16'h3: dac_filt_int_valid_b = dac_fir_valid_b;
16'h6: dac_filt_int_valid_b = dac_fir_valid_b;
16'h7: dac_filt_int_valid_b = dac_fir_valid_b;
default: dac_filt_int_valid_b = dac_valid_b & !dma_transfer_suspend;
endcase
case (filter_mask_a)
16'h1: interp_rate_cic_a = 16'd5;
16'h2: interp_rate_cic_a = 16'd50;
16'h3: interp_rate_cic_a = 16'd500;
16'h6: interp_rate_cic_a = 16'd5000;
16'h7: interp_rate_cic_a = 16'd50000;
default: interp_rate_cic_a = 16'd1;
endcase
case (filter_mask_b)
16'h1: interp_rate_cic_b = 16'd5;
16'h2: interp_rate_cic_b = 16'd50;
16'h3: interp_rate_cic_b = 16'd500;
16'h6: interp_rate_cic_b = 16'd5000;
16'h7: interp_rate_cic_b = 16'd50000;
default: interp_rate_cic_b = 16'd1;
endcase
end
axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
.clk (dac_clk),
.dac_interpolation_ratio_a (interpolation_ratio_a),
.dac_filter_mask_a (filter_mask_a),
.dac_interpolation_ratio_b (interpolation_ratio_b),
.dac_filter_mask_b (filter_mask_b),
.dma_transfer_suspend (dma_transfer_suspend),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc Normal file
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

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library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dac_interpolate
adi_ip_files axi_dac_interpolate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_dac_interpolate_constr.xdc" \
"cic_interp.v" \
"fir_interp.v" \
"axi_dac_interpolate_reg.v" \
"axi_dac_interpolate.v" ]
adi_ip_properties axi_dac_interpolate
adi_ip_constraints axi_dac_interpolate [list \
"axi_dac_interpolate_constr.xdc" ]
ipx::remove_bus_interface {clk} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
ipx::save_core [ipx::current_core]

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library/axi_dac_interpolate/axi_dac_interpolate_reg.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dac_interpolate_reg(
input clk,
output [31:0] dac_interpolation_ratio_a,
output [31:0] dac_filter_mask_a,
output [31:0] dac_interpolation_ratio_b,
output [31:0] dac_filter_mask_b,
output dma_transfer_suspend,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// internal registers
reg [31:0] up_version = 32'h00020000;
reg [31:0] up_scratch = 32'h0;
reg [31:0] up_interpolation_ratio_a = 32'h0;
reg [31:0] up_filter_mask_a = 32'h0;
reg [31:0] up_interpolation_ratio_b = 32'h0;
reg [31:0] up_filter_mask_b = 32'h0;
reg [31:0] up_flags = 32'h0;
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_interpolation_ratio_a <= 'd0;
up_filter_mask_a <= 'd0;
up_interpolation_ratio_b <= 'd0;
up_filter_mask_b <= 'd0;
up_flags <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_interpolation_ratio_a <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_filter_mask_a <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_interpolation_ratio_b <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_filter_mask_b <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_flags <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;
5'h10: up_rdata <= up_interpolation_ratio_a;
5'h11: up_rdata <= up_filter_mask_a;
5'h12: up_rdata <= up_interpolation_ratio_b;
5'h13: up_rdata <= up_filter_mask_b;
5'h14: up_rdata <= up_flags;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
up_xfer_cntrl #(.DATA_WIDTH(129)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_flags[0], // 1
up_interpolation_ratio_b, // 32
up_interpolation_ratio_a, // 32
up_filter_mask_b, // 32
up_filter_mask_a}), // 32
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
.d_data_cntrl ({ dma_transfer_suspend, // 1
dac_interpolation_ratio_b, // 32
dac_interpolation_ratio_a, // 32
dac_filter_mask_b, // 32
dac_filter_mask_a})); // 32
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_dac_interpolate/cic_interp.v Normal file
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// -------------------------------------------------------------
//
// Module: cic_interp
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
// Generated on: 2016-07-05 11:08:04
// -------------------------------------------------------------
// -------------------------------------------------------------
// HDL Code Generation Options:
//
// OptimizeForHDL: on
// EDAScriptGeneration: off
// AddPipelineRegisters: on
// Name: cic_interp
// AddRatePort: on
// InputDataType: numerictype(1,31,30)
// TargetLanguage: Verilog
// TestBenchName: cicinterpfilt_copy_tb
// TestBenchStimulus: step ramp chirp noise
// GenerateHDLTestBench: off
// -------------------------------------------------------------
// HDL Implementation : Fully parallel
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Multirate Filter (real)
// -----------------------------------------
// Filter Structure : Cascaded Integrator-Comb Interpolator
// Interpolation Factor : 50000
// Differential Delay : 1
// Number of Sections : 6
// Stable : Yes
// Linear Phase : No
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module cic_interp
(
clk,
clk_enable,
reset,
filter_in,
rate,
load_rate,
filter_out,
ce_out
);
input clk;
input clk_enable;
input reset;
input signed [30:0] filter_in; //sfix31_En30
input [15:0] rate; //ufix16
input load_rate;
output signed [109:0] filter_out; //sfix110_En30
output ce_out;
////////////////////////////////////////////////////////////////
//Module Architecture: cic_interp
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30
// Signals
wire [15:0] rate_unsigned; // ufix16
reg [15:0] cur_count = 0; // ufix16
wire phase_0; // boolean
//
reg signed [30:0] input_register = 0; // sfix31_En30
// -- Section 1 Signals
wire signed [30:0] section_in1; // sfix31_En30
wire signed [31:0] section_cast1; // sfix32_En30
reg signed [31:0] diff1 = 0; // sfix32_En30
wire signed [31:0] section_out1; // sfix32_En30
wire signed [31:0] sub_cast; // sfix32_En30
wire signed [31:0] sub_cast_1; // sfix32_En30
wire signed [32:0] sub_temp; // sfix33_En30
reg signed [31:0] cic_pipeline1 = 0; // sfix32_En30
// -- Section 2 Signals
wire signed [31:0] section_in2; // sfix32_En30
wire signed [32:0] section_cast2; // sfix33_En30
reg signed [32:0] diff2 = 0; // sfix33_En30
wire signed [32:0] section_out2; // sfix33_En30
wire signed [32:0] sub_cast_2; // sfix33_En30
wire signed [32:0] sub_cast_3; // sfix33_En30
wire signed [33:0] sub_temp_1; // sfix34_En30
reg signed [32:0] cic_pipeline2 = 0; // sfix33_En30
// -- Section 3 Signals
wire signed [32:0] section_in3; // sfix33_En30
wire signed [33:0] section_cast3; // sfix34_En30
reg signed [33:0] diff3 = 0; // sfix34_En30
wire signed [33:0] section_out3; // sfix34_En30
wire signed [33:0] sub_cast_4; // sfix34_En30
wire signed [33:0] sub_cast_5; // sfix34_En30
wire signed [34:0] sub_temp_2; // sfix35_En30
reg signed [33:0] cic_pipeline3 = 0; // sfix34_En30
// -- Section 4 Signals
wire signed [33:0] section_in4; // sfix34_En30
wire signed [34:0] section_cast4; // sfix35_En30
reg signed [34:0] diff4 = 0; // sfix35_En30
wire signed [34:0] section_out4; // sfix35_En30
wire signed [34:0] sub_cast_6; // sfix35_En30
wire signed [34:0] sub_cast_7; // sfix35_En30
wire signed [35:0] sub_temp_3; // sfix36_En30
reg signed [34:0] cic_pipeline4 = 0; // sfix35_En30
// -- Section 5 Signals
wire signed [34:0] section_in5; // sfix35_En30
wire signed [35:0] section_cast5; // sfix36_En30
reg signed [35:0] diff5 = 0; // sfix36_En30
wire signed [35:0] section_out5; // sfix36_En30
wire signed [35:0] sub_cast_8; // sfix36_En30
wire signed [35:0] sub_cast_9; // sfix36_En30
wire signed [36:0] sub_temp_4; // sfix37_En30
reg signed [35:0] cic_pipeline5 = 0; // sfix36_En30
// -- Section 6 Signals
wire signed [35:0] section_in6; // sfix36_En30
reg signed [35:0] diff6 = 0; // sfix36_En30
wire signed [35:0] section_out6; // sfix36_En30
wire signed [35:0] sub_cast_10; // sfix36_En30
wire signed [35:0] sub_cast_11; // sfix36_En30
wire signed [36:0] sub_temp_5; // sfix37_En30
reg signed [35:0] cic_pipeline6 = 0; // sfix36_En30
wire signed [35:0] upsampling; // sfix36_En30
// -- Section 7 Signals
wire signed [35:0] section_in7; // sfix36_En30
wire signed [35:0] sum1; // sfix36_En30
reg signed [35:0] section_out7 = 0; // sfix36_En30
wire signed [35:0] add_cast; // sfix36_En30
wire signed [35:0] add_cast_1; // sfix36_En30
wire signed [36:0] add_temp; // sfix37_En30
// -- Section 8 Signals
wire signed [35:0] section_in8; // sfix36_En30
wire signed [50:0] section_cast8; // sfix51_En30
wire signed [50:0] sum2; // sfix51_En30
reg signed [50:0] section_out8 = 0; // sfix51_En30
wire signed [50:0] add_cast_2; // sfix51_En30
wire signed [50:0] add_cast_3; // sfix51_En30
wire signed [51:0] add_temp_1; // sfix52_En30
// -- Section 9 Signals
wire signed [50:0] section_in9; // sfix51_En30
wire signed [65:0] section_cast9; // sfix66_En30
wire signed [65:0] sum3; // sfix66_En30
reg signed [65:0] section_out9 = 0; // sfix66_En30
wire signed [65:0] add_cast_4; // sfix66_En30
wire signed [65:0] add_cast_5; // sfix66_En30
wire signed [66:0] add_temp_2; // sfix67_En30
// -- Section 10 Signals
wire signed [65:0] section_in10; // sfix66_En30
wire signed [79:0] section_cast10; // sfix80_En30
wire signed [79:0] sum4; // sfix80_En30
reg signed [79:0] section_out10 = 0; // sfix80_En30
wire signed [79:0] add_cast_6; // sfix80_En30
wire signed [79:0] add_cast_7; // sfix80_En30
wire signed [80:0] add_temp_3; // sfix81_En30
// -- Section 11 Signals
wire signed [79:0] section_in11; // sfix80_En30
wire signed [94:0] section_cast11; // sfix95_En30
wire signed [94:0] sum5; // sfix95_En30
reg signed [94:0] section_out11 = 0; // sfix95_En30
wire signed [94:0] add_cast_8; // sfix95_En30
wire signed [94:0] add_cast_9; // sfix95_En30
wire signed [95:0] add_temp_4; // sfix96_En30
// -- Section 12 Signals
wire signed [94:0] section_in12; // sfix95_En30
wire signed [109:0] section_cast12; // sfix110_En30
wire signed [109:0] sum6; // sfix110_En30
reg signed [109:0] section_out12 = 0; // sfix110_En30
wire signed [109:0] add_cast_10; // sfix110_En30
wire signed [109:0] add_cast_11; // sfix110_En30
wire signed [110:0] add_temp_5; // sfix111_En30
reg [6:0] bitgain = 0; // ufix7
wire signed [109:0] output_typeconvert; // sfix110_En30
wire signed [109:0] muxinput_14; // sfix110_En16
wire signed [109:0] muxinput_34; // sfix110_E4
wire signed [109:0] muxinput_54; // sfix110_E24
wire signed [109:0] muxinput_74; // sfix110_E44
wire signed [109:0] muxinput_94; // sfix110_E64
//
reg signed [109:0] output_register = 0; // sfix110_En30
// Block Statements
assign rate_unsigned = rate;
always @ (posedge clk or posedge reset)
begin: ce_output
if (reset == 1'b1) begin
cur_count <= 16'b0000000000000000;
end
else begin
if (clk_enable == 1'b1) begin
if (load_rate == 1'b1) begin
cur_count <= 16'b0000000000000001;
end
else if (cur_count == rate_unsigned - 1) begin
cur_count <= 16'b0000000000000000;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // ce_output
assign phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0;
// ------------------ Input Register ------------------
always @ (posedge clk or posedge reset)
begin: input_reg_process
if (reset == 1'b1) begin
input_register <= 0;
end
else begin
if (phase_0 == 1'b1) begin
input_register <= filter_in;
end
end
end // input_reg_process
// ------------------ Section # 1 : Comb ------------------
assign section_in1 = input_register;
assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1});
assign sub_cast = section_cast1;
assign sub_cast_1 = diff1;
assign sub_temp = sub_cast - sub_cast_1;
assign section_out1 = sub_temp[31:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section1
if (reset == 1'b1) begin
diff1 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff1 <= section_cast1;
end
end
end // comb_delay_section1
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section1
if (reset == 1'b1) begin
cic_pipeline1 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline1 <= section_out1;
end
end
end // cic_pipeline_process_section1
// ------------------ Section # 2 : Comb ------------------
assign section_in2 = cic_pipeline1;
assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2});
assign sub_cast_2 = section_cast2;
assign sub_cast_3 = diff2;
assign sub_temp_1 = sub_cast_2 - sub_cast_3;
assign section_out2 = sub_temp_1[32:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section2
if (reset == 1'b1) begin
diff2 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff2 <= section_cast2;
end
end
end // comb_delay_section2
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section2
if (reset == 1'b1) begin
cic_pipeline2 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline2 <= section_out2;
end
end
end // cic_pipeline_process_section2
// ------------------ Section # 3 : Comb ------------------
assign section_in3 = cic_pipeline2;
assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3});
assign sub_cast_4 = section_cast3;
assign sub_cast_5 = diff3;
assign sub_temp_2 = sub_cast_4 - sub_cast_5;
assign section_out3 = sub_temp_2[33:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section3
if (reset == 1'b1) begin
diff3 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff3 <= section_cast3;
end
end
end // comb_delay_section3
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section3
if (reset == 1'b1) begin
cic_pipeline3 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline3 <= section_out3;
end
end
end // cic_pipeline_process_section3
// ------------------ Section # 4 : Comb ------------------
assign section_in4 = cic_pipeline3;
assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4});
assign sub_cast_6 = section_cast4;
assign sub_cast_7 = diff4;
assign sub_temp_3 = sub_cast_6 - sub_cast_7;
assign section_out4 = sub_temp_3[34:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section4
if (reset == 1'b1) begin
diff4 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff4 <= section_cast4;
end
end
end // comb_delay_section4
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section4
if (reset == 1'b1) begin
cic_pipeline4 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline4 <= section_out4;
end
end
end // cic_pipeline_process_section4
// ------------------ Section # 5 : Comb ------------------
assign section_in5 = cic_pipeline4;
assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5});
assign sub_cast_8 = section_cast5;
assign sub_cast_9 = diff5;
assign sub_temp_4 = sub_cast_8 - sub_cast_9;
assign section_out5 = sub_temp_4[35:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section5
if (reset == 1'b1) begin
diff5 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff5 <= section_cast5;
end
end
end // comb_delay_section5
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section5
if (reset == 1'b1) begin
cic_pipeline5 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline5 <= section_out5;
end
end
end // cic_pipeline_process_section5
// ------------------ Section # 6 : Comb ------------------
assign section_in6 = cic_pipeline5;
assign sub_cast_10 = section_in6;
assign sub_cast_11 = diff6;
assign sub_temp_5 = sub_cast_10 - sub_cast_11;
assign section_out6 = sub_temp_5[35:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section6
if (reset == 1'b1) begin
diff6 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff6 <= section_in6;
end
end
end // comb_delay_section6
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section6
if (reset == 1'b1) begin
cic_pipeline6 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline6 <= section_out6;
end
end
end // cic_pipeline_process_section6
assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 :
zeroconst;
// ------------------ Section # 7 : Integrator ------------------
assign section_in7 = upsampling;
assign add_cast = section_in7;
assign add_cast_1 = section_out7;
assign add_temp = add_cast + add_cast_1;
assign sum1 = add_temp[35:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section7
if (reset == 1'b1) begin
section_out7 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out7 <= sum1;
end
end
end // integrator_delay_section7
// ------------------ Section # 8 : Integrator ------------------
assign section_in8 = section_out7;
assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8});
assign add_cast_2 = section_cast8;
assign add_cast_3 = section_out8;
assign add_temp_1 = add_cast_2 + add_cast_3;
assign sum2 = add_temp_1[50:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section8
if (reset == 1'b1) begin
section_out8 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out8 <= sum2;
end
end
end // integrator_delay_section8
// ------------------ Section # 9 : Integrator ------------------
assign section_in9 = section_out8;
assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9});
assign add_cast_4 = section_cast9;
assign add_cast_5 = section_out9;
assign add_temp_2 = add_cast_4 + add_cast_5;
assign sum3 = add_temp_2[65:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section9
if (reset == 1'b1) begin
section_out9 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out9 <= sum3;
end
end
end // integrator_delay_section9
// ------------------ Section # 10 : Integrator ------------------
assign section_in10 = section_out9;
assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10});
assign add_cast_6 = section_cast10;
assign add_cast_7 = section_out10;
assign add_temp_3 = add_cast_6 + add_cast_7;
assign sum4 = add_temp_3[79:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section10
if (reset == 1'b1) begin
section_out10 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out10 <= sum4;
end
end
end // integrator_delay_section10
// ------------------ Section # 11 : Integrator ------------------
assign section_in11 = section_out10;
assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11});
assign add_cast_8 = section_cast11;
assign add_cast_9 = section_out11;
assign add_temp_4 = add_cast_8 + add_cast_9;
assign sum5 = add_temp_4[94:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section11
if (reset == 1'b1) begin
section_out11 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out11 <= sum5;
end
end
end // integrator_delay_section11
// ------------------ Section # 12 : Integrator ------------------
assign section_in12 = section_out11;
assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12});
assign add_cast_10 = section_cast12;
assign add_cast_11 = section_out12;
assign add_temp_5 = add_cast_10 + add_cast_11;
assign sum6 = add_temp_5[109:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section12
if (reset == 1'b1) begin
section_out12 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out12 <= sum6;
end
end
end // integrator_delay_section12
always @(rate_unsigned)
begin
case(rate_unsigned)
16'b0000000000000101 : bitgain = 7'b0001110;
16'b0000000000110010 : bitgain = 7'b0100010;
16'b0000000111110100 : bitgain = 7'b0110110;
16'b0001001110001000 : bitgain = 7'b1001010;
16'b1100001101010000 : bitgain = 7'b1011110;
default : bitgain = 7'b1011110;
endcase
end
assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]});
assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]});
assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]});
assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]});
assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]});
assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
(bitgain == 7'b0100010) ? muxinput_34 :
(bitgain == 7'b0110110) ? muxinput_54 :
(bitgain == 7'b1001010) ? muxinput_74 :
muxinput_94;
// ------------------ Output Register ------------------
always @ (posedge clk or posedge reset)
begin: output_reg_process
if (reset == 1'b1) begin
output_register <= 0;
end
else begin
if (clk_enable == 1'b1) begin
output_register <= output_typeconvert;
end
end
end // output_reg_process
// Assignment Statements
assign ce_out = phase_0;
assign filter_out = output_register;
endmodule // cic_interp

390
library/axi_dac_interpolate/fir_interp.v Normal file
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@ -0,0 +1,390 @@
// -------------------------------------------------------------
//
// Module: fir_interp
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
// Generated on: 2016-07-05 15:54:12
// -------------------------------------------------------------
// -------------------------------------------------------------
// HDL Code Generation Options:
//
// FIRAdderStyle: tree
// OptimizeForHDL: on
// EDAScriptGeneration: off
// AddPipelineRegisters: on
// Name: fir_interp
// TargetLanguage: Verilog
// TestBenchName: fo_copy_tb
// TestBenchStimulus: step ramp chirp noise
// GenerateHDLTestBench: off
// -------------------------------------------------------------
// HDL Implementation : Fully parallel
// Multipliers : 12
// Folding Factor : 1
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Multirate Filter (real)
// -----------------------------------------
// Filter Structure : Direct-Form FIR Polyphase Interpolator
// Interpolation Factor : 2
// Polyphase Length : 12
// Filter Length : 24
// Stable : Yes
// Linear Phase : Yes (Type 2)
//
// Arithmetic : fixed
// Numerator : s16,15 -> [-1 1)
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module fir_interp
(
clk,
clk_enable,
reset,
filter_in,
filter_out,
ce_out
);
input clk;
input clk_enable;
input reset;
input signed [15:0] filter_in; //sfix16_En15
output signed [35:0] filter_out; //sfix36_En30
output ce_out;
////////////////////////////////////////////////////////////////
//Module Architecture: fir_interp
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [15:0] coeffphase1_1 = 16'b1111111110101001; //sfix16_En15
parameter signed [15:0] coeffphase1_2 = 16'b1111111101111010; //sfix16_En15
parameter signed [15:0] coeffphase1_3 = 16'b0000010011111111; //sfix16_En15
parameter signed [15:0] coeffphase1_4 = 16'b1111101010101110; //sfix16_En15
parameter signed [15:0] coeffphase1_5 = 16'b1111001001101000; //sfix16_En15
parameter signed [15:0] coeffphase1_6 = 16'b0011011010110011; //sfix16_En15
parameter signed [15:0] coeffphase1_7 = 16'b0101011100111111; //sfix16_En15
parameter signed [15:0] coeffphase1_8 = 16'b0000110010011010; //sfix16_En15
parameter signed [15:0] coeffphase1_9 = 16'b1111000000000010; //sfix16_En15
parameter signed [15:0] coeffphase1_10 = 16'b0000001110101000; //sfix16_En15
parameter signed [15:0] coeffphase1_11 = 16'b0000000111110010; //sfix16_En15
parameter signed [15:0] coeffphase1_12 = 16'b1111111100011100; //sfix16_En15
parameter signed [15:0] coeffphase2_1 = 16'b1111111100011100; //sfix16_En15
parameter signed [15:0] coeffphase2_2 = 16'b0000000111110010; //sfix16_En15
parameter signed [15:0] coeffphase2_3 = 16'b0000001110101000; //sfix16_En15
parameter signed [15:0] coeffphase2_4 = 16'b1111000000000010; //sfix16_En15
parameter signed [15:0] coeffphase2_5 = 16'b0000110010011010; //sfix16_En15
parameter signed [15:0] coeffphase2_6 = 16'b0101011100111111; //sfix16_En15
parameter signed [15:0] coeffphase2_7 = 16'b0011011010110011; //sfix16_En15
parameter signed [15:0] coeffphase2_8 = 16'b1111001001101000; //sfix16_En15
parameter signed [15:0] coeffphase2_9 = 16'b1111101010101110; //sfix16_En15
parameter signed [15:0] coeffphase2_10 = 16'b0000010011111111; //sfix16_En15
parameter signed [15:0] coeffphase2_11 = 16'b1111111101111010; //sfix16_En15
parameter signed [15:0] coeffphase2_12 = 16'b1111111110101001; //sfix16_En15
// Signals
reg [1:0] cur_count = 0; // ufix2
wire phase_1; // boolean
reg signed [15:0] delay_pipeline [0:11]; // sfix16_En15
wire signed [31:0] product; // sfix32_En30
wire signed [15:0] product_mux; // sfix16_En15
wire signed [31:0] product_1; // sfix32_En30
wire signed [15:0] product_mux_1; // sfix16_En15
wire signed [31:0] product_2; // sfix32_En30
wire signed [15:0] product_mux_2; // sfix16_En15
wire signed [31:0] product_3; // sfix32_En30
wire signed [15:0] product_mux_3; // sfix16_En15
wire signed [31:0] product_4; // sfix32_En30
wire signed [15:0] product_mux_4; // sfix16_En15
wire signed [31:0] product_5; // sfix32_En30
wire signed [15:0] product_mux_5; // sfix16_En15
wire signed [31:0] product_6; // sfix32_En30
wire signed [15:0] product_mux_6; // sfix16_En15
wire signed [31:0] product_7; // sfix32_En30
wire signed [15:0] product_mux_7; // sfix16_En15
wire signed [31:0] product_8; // sfix32_En30
wire signed [15:0] product_mux_8; // sfix16_En15
wire signed [31:0] product_9; // sfix32_En30
wire signed [15:0] product_mux_9; // sfix16_En15
wire signed [31:0] product_10; // sfix32_En30
wire signed [15:0] product_mux_10; // sfix16_En15
wire signed [31:0] product_11; // sfix32_En30
wire signed [15:0] product_mux_11; // sfix16_En15
wire signed [35:0] sumvector1 [0:5] ; // sfix36_En30
wire signed [31:0] add_signext; // sfix32_En30
wire signed [31:0] add_signext_1; // sfix32_En30
wire signed [32:0] add_temp; // sfix33_En30
wire signed [31:0] add_signext_2; // sfix32_En30
wire signed [31:0] add_signext_3; // sfix32_En30
wire signed [32:0] add_temp_1; // sfix33_En30
wire signed [31:0] add_signext_4; // sfix32_En30
wire signed [31:0] add_signext_5; // sfix32_En30
wire signed [32:0] add_temp_2; // sfix33_En30
wire signed [31:0] add_signext_6; // sfix32_En30
wire signed [31:0] add_signext_7; // sfix32_En30
wire signed [32:0] add_temp_3; // sfix33_En30
wire signed [31:0] add_signext_8; // sfix32_En30
wire signed [31:0] add_signext_9; // sfix32_En30
wire signed [32:0] add_temp_4; // sfix33_En30
wire signed [31:0] add_signext_10; // sfix32_En30
wire signed [31:0] add_signext_11; // sfix32_En30
wire signed [32:0] add_temp_5; // sfix33_En30
reg signed [35:0] sumdelay_pipeline1 [0:5]; // sfix36_En30
wire signed [35:0] sumvector2 [0:2] ; // sfix36_En30
wire signed [35:0] add_signext_12; // sfix36_En30
wire signed [35:0] add_signext_13; // sfix36_En30
wire signed [36:0] add_temp_6; // sfix37_En30
wire signed [35:0] add_signext_14; // sfix36_En30
wire signed [35:0] add_signext_15; // sfix36_En30
wire signed [36:0] add_temp_7; // sfix37_En30
wire signed [35:0] add_signext_16; // sfix36_En30
wire signed [35:0] add_signext_17; // sfix36_En30
wire signed [36:0] add_temp_8; // sfix37_En30
reg signed [35:0] sumdelay_pipeline2 [0:2]; // sfix36_En30
wire signed [35:0] sumvector3 [0:1] ; // sfix36_En30
wire signed [35:0] add_signext_18; // sfix36_En30
wire signed [35:0] add_signext_19; // sfix36_En30
wire signed [36:0] add_temp_9; // sfix37_En30
reg signed [35:0] sumdelay_pipeline3 [0:1]; // sfix36_En30
wire signed [35:0] sum4; // sfix36_En30
wire signed [35:0] add_signext_20; // sfix36_En30
wire signed [35:0] add_signext_21; // sfix36_En30
wire signed [36:0] add_temp_10; // sfix37_En30
reg signed [35:0] output_register = 0; // sfix36_En30
// Block Statements
always @ (posedge clk or posedge reset)
begin: ce_output
if (reset == 1'b1) begin
cur_count <= 2'b00;
end
else begin
if (clk_enable == 1'b1) begin
if (cur_count == 2'b01) begin
cur_count <= 2'b00;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // ce_output
assign phase_1 = (cur_count == 2'b01 && clk_enable == 1'b1)? 1 : 0;
// ---------------- Delay Registers ----------------
always @( posedge clk or posedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b1) begin
delay_pipeline[0] <= 0;
delay_pipeline[1] <= 0;
delay_pipeline[2] <= 0;
delay_pipeline[3] <= 0;
delay_pipeline[4] <= 0;
delay_pipeline[5] <= 0;
delay_pipeline[6] <= 0;
delay_pipeline[7] <= 0;
delay_pipeline[8] <= 0;
delay_pipeline[9] <= 0;
delay_pipeline[10] <= 0;
delay_pipeline[11] <= 0;
end
else begin
if (phase_1 == 1'b1) begin
delay_pipeline[0] <= filter_in;
delay_pipeline[1] <= delay_pipeline[0];
delay_pipeline[2] <= delay_pipeline[1];
delay_pipeline[3] <= delay_pipeline[2];
delay_pipeline[4] <= delay_pipeline[3];
delay_pipeline[5] <= delay_pipeline[4];
delay_pipeline[6] <= delay_pipeline[5];
delay_pipeline[7] <= delay_pipeline[6];
delay_pipeline[8] <= delay_pipeline[7];
delay_pipeline[9] <= delay_pipeline[8];
delay_pipeline[10] <= delay_pipeline[9];
delay_pipeline[11] <= delay_pipeline[10];
end
end
end // Delay_Pipeline_process
assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 :
coeffphase2_12;
assign product = delay_pipeline[11] * product_mux;
assign product_mux_1 = (cur_count == 2'b00) ? coeffphase1_11 :
coeffphase2_11;
assign product_1 = delay_pipeline[10] * product_mux_1;
assign product_mux_2 = (cur_count == 2'b00) ? coeffphase1_10 :
coeffphase2_10;
assign product_2 = delay_pipeline[9] * product_mux_2;
assign product_mux_3 = (cur_count == 2'b00) ? coeffphase1_9 :
coeffphase2_9;
assign product_3 = delay_pipeline[8] * product_mux_3;
assign product_mux_4 = (cur_count == 2'b00) ? coeffphase1_8 :
coeffphase2_8;
assign product_4 = delay_pipeline[7] * product_mux_4;
assign product_mux_5 = (cur_count == 2'b00) ? coeffphase1_7 :
coeffphase2_7;
assign product_5 = delay_pipeline[6] * product_mux_5;
assign product_mux_6 = (cur_count == 2'b00) ? coeffphase1_6 :
coeffphase2_6;
assign product_6 = delay_pipeline[5] * product_mux_6;
assign product_mux_7 = (cur_count == 2'b00) ? coeffphase1_5 :
coeffphase2_5;
assign product_7 = delay_pipeline[4] * product_mux_7;
assign product_mux_8 = (cur_count == 2'b00) ? coeffphase1_4 :
coeffphase2_4;
assign product_8 = delay_pipeline[3] * product_mux_8;
assign product_mux_9 = (cur_count == 2'b00) ? coeffphase1_3 :
coeffphase2_3;
assign product_9 = delay_pipeline[2] * product_mux_9;
assign product_mux_10 = (cur_count == 2'b00) ? coeffphase1_2 :
coeffphase2_2;
assign product_10 = delay_pipeline[1] * product_mux_10;
assign product_mux_11 = (cur_count == 2'b00) ? coeffphase1_1 :
coeffphase2_1;
assign product_11 = delay_pipeline[0] * product_mux_11;
assign add_signext = product;
assign add_signext_1 = product_1;
assign add_temp = add_signext + add_signext_1;
assign sumvector1[0] = $signed({{3{add_temp[32]}}, add_temp});
assign add_signext_2 = product_2;
assign add_signext_3 = product_3;
assign add_temp_1 = add_signext_2 + add_signext_3;
assign sumvector1[1] = $signed({{3{add_temp_1[32]}}, add_temp_1});
assign add_signext_4 = product_4;
assign add_signext_5 = product_5;
assign add_temp_2 = add_signext_4 + add_signext_5;
assign sumvector1[2] = $signed({{3{add_temp_2[32]}}, add_temp_2});
assign add_signext_6 = product_6;
assign add_signext_7 = product_7;
assign add_temp_3 = add_signext_6 + add_signext_7;
assign sumvector1[3] = $signed({{3{add_temp_3[32]}}, add_temp_3});
assign add_signext_8 = product_8;
assign add_signext_9 = product_9;
assign add_temp_4 = add_signext_8 + add_signext_9;
assign sumvector1[4] = $signed({{3{add_temp_4[32]}}, add_temp_4});
assign add_signext_10 = product_10;
assign add_signext_11 = product_11;
assign add_temp_5 = add_signext_10 + add_signext_11;
assign sumvector1[5] = $signed({{3{add_temp_5[32]}}, add_temp_5});
always @ (posedge clk or posedge reset)
begin: sumdelay_pipeline_process1
if (reset == 1'b1) begin
sumdelay_pipeline1[0] <= 0;
sumdelay_pipeline1[1] <= 0;
sumdelay_pipeline1[2] <= 0;
sumdelay_pipeline1[3] <= 0;
sumdelay_pipeline1[4] <= 0;
sumdelay_pipeline1[5] <= 0;
end
else begin
if (clk_enable == 1'b1) begin
sumdelay_pipeline1[0] <= sumvector1[0];
sumdelay_pipeline1[1] <= sumvector1[1];
sumdelay_pipeline1[2] <= sumvector1[2];
sumdelay_pipeline1[3] <= sumvector1[3];
sumdelay_pipeline1[4] <= sumvector1[4];
sumdelay_pipeline1[5] <= sumvector1[5];
end
end
end // sumdelay_pipeline_process1
assign add_signext_12 = sumdelay_pipeline1[0];
assign add_signext_13 = sumdelay_pipeline1[1];
assign add_temp_6 = add_signext_12 + add_signext_13;
assign sumvector2[0] = add_temp_6[35:0];
assign add_signext_14 = sumdelay_pipeline1[2];
assign add_signext_15 = sumdelay_pipeline1[3];
assign add_temp_7 = add_signext_14 + add_signext_15;
assign sumvector2[1] = add_temp_7[35:0];
assign add_signext_16 = sumdelay_pipeline1[4];
assign add_signext_17 = sumdelay_pipeline1[5];
assign add_temp_8 = add_signext_16 + add_signext_17;
assign sumvector2[2] = add_temp_8[35:0];
always @ (posedge clk or posedge reset)
begin: sumdelay_pipeline_process2
if (reset == 1'b1) begin
sumdelay_pipeline2[0] <= 0;
sumdelay_pipeline2[1] <= 0;
sumdelay_pipeline2[2] <= 0;
end
else begin
if (clk_enable == 1'b1) begin
sumdelay_pipeline2[0] <= sumvector2[0];
sumdelay_pipeline2[1] <= sumvector2[1];
sumdelay_pipeline2[2] <= sumvector2[2];
end
end
end // sumdelay_pipeline_process2
assign add_signext_18 = sumdelay_pipeline2[0];
assign add_signext_19 = sumdelay_pipeline2[1];
assign add_temp_9 = add_signext_18 + add_signext_19;
assign sumvector3[0] = add_temp_9[35:0];
assign sumvector3[1] = sumdelay_pipeline2[2];
always @ (posedge clk or posedge reset)
begin: sumdelay_pipeline_process3
if (reset == 1'b1) begin
sumdelay_pipeline3[0] <= 0;
sumdelay_pipeline3[1] <= 0;
end
else begin
if (clk_enable == 1'b1) begin
sumdelay_pipeline3[0] <= sumvector3[0];
sumdelay_pipeline3[1] <= sumvector3[1];
end
end
end // sumdelay_pipeline_process3
assign add_signext_20 = sumdelay_pipeline3[0];
assign add_signext_21 = sumdelay_pipeline3[1];
assign add_temp_10 = add_signext_20 + add_signext_21;
assign sum4 = add_temp_10[35:0];
always @ (posedge clk or posedge reset)
begin: Output_Register_process
if (reset == 1'b1) begin
output_register <= 0;
end
else begin
if (clk_enable == 1'b1) begin
output_register <= sum4;
end
end
end // Output_Register_process
// Assignment Statements
assign ce_out = phase_1;
assign filter_out = output_register;
endmodule // fir_interp