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up_dac_common: Increase datawidth of dac_datarate 

In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.

Therefor increasing to 16 bit.
main
Istvan Csomortani 2016-11-11 11:43:06 +02:00
parent a6146393be
commit 9cd218eb90
2 changed files with 7 additions and 7 deletions
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4
library/axi_ad5766/axi_ad5766.v
View File

@ -121,7 +121,7 @@ module axi_ad5766 #(
wire up_wack_s[0:1]; wire up_wack_s[0:1];
wire trigger_s; wire trigger_s;
wire [31:0] pulse_period_s; wire [31:0] pulse_period_s;
wire [ 7:0] dac_datarate_s; wire [15:0] dac_datarate_s;
wire spi_reset; wire spi_reset;
wire spi_enable_s; wire spi_enable_s;
wire [ 3:0] sequencer[15:0]; wire [ 3:0] sequencer[15:0];
@ -324,7 +324,7 @@ module axi_ad5766 #(
// DAC common registermap // DAC common registermap
assign pulse_period_s = {24'h0, dac_datarate_s}; assign pulse_period_s = {16'h0, dac_datarate_s};
up_ad5766_sequencer #( up_ad5766_sequencer #(
.SEQ_ID(4)) .SEQ_ID(4))

10
library/common/up_dac_common.v
View File

@ -63,7 +63,7 @@ module up_dac_common #(
output dac_par_enb, output dac_par_enb,
output dac_r1_mode, output dac_r1_mode,
output dac_datafmt, output dac_datafmt,
output [ 7:0] dac_datarate, output [15:0] dac_datarate,
input dac_status, input dac_status,
input dac_status_ovf, input dac_status_ovf,
input dac_status_unf, input dac_status_unf,
@ -118,7 +118,7 @@ module up_dac_common #(
reg up_dac_par_enb = 'd0; reg up_dac_par_enb = 'd0;
reg up_dac_r1_mode = 'd0; reg up_dac_r1_mode = 'd0;
reg up_dac_datafmt = 'd0; reg up_dac_datafmt = 'd0;
reg [ 7:0] up_dac_datarate = 'd0; reg [15:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0; reg up_dac_frame = 'd0;
reg up_dac_clksel = 'd0; reg up_dac_clksel = 'd0;
reg up_drp_sel_int = 'd0; reg up_drp_sel_int = 'd0;
@ -209,7 +209,7 @@ module up_dac_common #(
up_dac_datafmt <= up_wdata[4]; up_dac_datafmt <= up_wdata[4];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_dac_datarate <= up_wdata[7:0]; up_dac_datarate <= up_wdata[15:0];
end end
if (up_dac_frame == 1'b1) begin if (up_dac_frame == 1'b1) begin
if (up_xfer_done_s == 1'b1) begin if (up_xfer_done_s == 1'b1) begin
@ -357,7 +357,7 @@ module up_dac_common #(
8'h11: up_rdata_int <= {31'd0, up_dac_sync}; 8'h11: up_rdata_int <= {31'd0, up_dac_sync};
8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, 8'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
up_dac_datafmt, 4'd0}; up_dac_datafmt, 4'd0};
8'h13: up_rdata_int <= {24'd0, up_dac_datarate}; 8'h13: up_rdata_int <= {16'd0, up_dac_datarate};
8'h14: up_rdata_int <= {31'd0, up_dac_frame}; 8'h14: up_rdata_int <= {31'd0, up_dac_frame};
8'h15: up_rdata_int <= up_dac_clk_count_s; 8'h15: up_rdata_int <= up_dac_clk_count_s;
8'h16: up_rdata_int <= dac_clk_ratio; 8'h16: up_rdata_int <= dac_clk_ratio;
@ -386,7 +386,7 @@ module up_dac_common #(
// dac control & status // dac control & status
up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(23)) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_dac_sync, .up_data_cntrl ({ up_dac_sync,