quartus-mess- altddio direct instantiation

main
Rejeesh Kutty 2016-05-09 13:49:13 -04:00
parent 726ddb6e93
commit 9cd6e2da51
4 changed files with 80 additions and 0 deletions

View File

@ -93,10 +93,29 @@ module ad_cmos_in (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in),
.dout ({rx_data_p, rx_data_n}));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in),
.dataout_h (rx_data_p),
.dataout_l (rx_data_n),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule

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@ -94,10 +94,31 @@ module ad_cmos_out (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_out i_tx_data_oddr (
.ck (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule

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@ -95,10 +95,29 @@ module ad_lvds_in (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in_p),
.dout ({rx_data_p, rx_data_n}));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in_p),
.dataout_h (rx_data_p),
.dataout_l (rx_data_n),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule

View File

@ -96,10 +96,31 @@ module ad_lvds_out (
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_out i_tx_data_oddr (
.ck (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out_p));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out_p),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule