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ATofan 2014-04-10 10:50:53 +03:00
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5
README.md
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@ -3,7 +3,8 @@ hdl
Analog Devices HDL libraries and projects
http://wiki.analog.com/resources/fpga/docs/hdl/github
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
http://wiki.analog.com/resources/fpga/docs/hdl/regmap

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library/axi_ad9250/axi_ad9250.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9250 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_ddata;
output adc_dsync;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [55:0] adc_mon_data;
// internal registers
reg adc_data_cnt = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [27:0] adc_data_a_s;
wire [27:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
wire adc_enable_a_s;
wire [31:0] adc_channel_data_a_s;
wire adc_enable_b_s;
wire [31:0] adc_channel_data_b_s;
wire up_adc_pn_err_a_s;
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[ 27: 0] = adc_data_a_s;
assign adc_mon_data[ 55: 28] = adc_data_b_s;
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {adc_channel_data_b_s[31:16], adc_channel_data_a_s[31:16],
adc_channel_data_b_s[15: 0], adc_channel_data_a_s[15: 0]};
end
2'b10: begin // Q only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_b_s, adc_ddata[63:32]};
end
2'b01: begin // I only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_a_s, adc_ddata[63:32]};
end
default: begin // no channels
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {4{16'hdead}};
end
endcase
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s;
end
end
// main (device interface)
axi_ad9250_if i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s));
// channel
axi_ad9250_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_channel_data_a_s),
.adc_enable (adc_enable_a_s),
.up_adc_pn_err (up_adc_pn_err_a_s),
.up_adc_pn_oos (up_adc_pn_oos_a_s),
.up_adc_or (up_adc_or_a_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s),
.up_ack (up_adc_channel_ack_a_s));
// channel
axi_ad9250_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_channel_data_b_s),
.adc_enable (adc_enable_b_s),
.up_adc_pn_err (up_adc_pn_err_b_s),
.up_adc_pn_oos (up_adc_pn_oos_b_s),
.up_adc_or (up_adc_or_b_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s),
.up_ack (up_adc_channel_ack_b_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b0),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9250_alt (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awid,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bid,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arid,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rid,
s_axi_rlast,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_ddata;
output adc_dsync;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [ 2:0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
input [ 0:0] s_axi_awlock;
input [ 3:0] s_axi_awcache;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
input s_axi_wlast;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [ 2:0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [ 2:0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
input [ 0:0] s_axi_arlock;
input [ 3:0] s_axi_arcache;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [ 2:0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [119:0] adc_mon_data;
// defaults
assign s_axi_bid = 3'd0;
assign s_axi_rid = 3'd0;
assign s_axi_rlast = 1'd0;
// ad9250 lite version
axi_ad9250 #(
.PCORE_ID (PCORE_ID),
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
.C_S_AXI_MIN_SIZE (32'hffff),
.C_BASEADDR (32'h00000000),
.C_HIGHADDR (32'hffffffff))
i_ad9250 (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_dwr (adc_dwr),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awaddr ({18'd0, s_axi_awaddr}),
.s_axi_awready (s_axi_awready),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wready (s_axi_wready),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bready (s_axi_bready),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_araddr ({18'd0, s_axi_araddr}),
.s_axi_arready (s_axi_arready),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9250_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [27:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_pn_type_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
// instantiations
axi_ad9250_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*14+13:n*14]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_pn_sel (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9250/axi_ad9250_hw.tcl Executable file
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package require -exact qsys 13.0
source ../scripts/adi_env.tcl
set_module_property NAME axi_ad9250
set_module_property DESCRIPTION "AXI AD9250 Interface"
set_module_property VERSION 1.0
set_module_property DISPLAY_NAME axi_ad9250
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_drp_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_drp_cntrl.v
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v
add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v
add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v
add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v
add_fileset_file axi_ad9250_alt.v VERILOG PATH axi_ad9250_alt.v TOP_LEVEL_FILE
# parameters
add_parameter PCORE_ID INTEGER 0
set_parameter_property PCORE_ID DEFAULT_VALUE 0
set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
set_parameter_property PCORE_ID TYPE INTEGER
set_parameter_property PCORE_ID UNITS None
set_parameter_property PCORE_ID HDL_PARAMETER true
add_parameter PCORE_DEVICE_TYPE INTEGER 0
set_parameter_property PCORE_DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property PCORE_DEVICE_TYPE DISPLAY_NAME PCORE_DEVICE_TYPE
set_parameter_property PCORE_DEVICE_TYPE TYPE INTEGER
set_parameter_property PCORE_DEVICE_TYPE UNITS None
set_parameter_property PCORE_DEVICE_TYPE HDL_PARAMETER true
# axi4 slave
add_interface s_axi_clock clock end
add_interface_port s_axi_clock s_axi_aclk clk Input 1
add_interface s_axi_reset reset end
set_interface_property s_axi_reset associatedClock s_axi_clock
add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
add_interface s_axi axi4 end
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 14
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
add_interface_port s_axi s_axi_wdata wdata Input 32
add_interface_port s_axi s_axi_wstrb wstrb Input 4
add_interface_port s_axi s_axi_wready wready Output 1
add_interface_port s_axi s_axi_bvalid bvalid Output 1
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 14
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 3
add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2
add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 3
add_interface_port s_axi s_axi_arid arid Input 3
add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 3
add_interface_port s_axi s_axi_rlast rlast Output 1
# transceiver interface
add_interface xcvr_clk clock end
add_interface_port xcvr_clk rx_clk clk Input 1
add_interface xcvr_data conduit end
set_interface_property xcvr_data associatedClock xcvr_clk
add_interface_port xcvr_data rx_data data Input 64
# dma interface
add_interface adc_clock clock start
add_interface_port adc_clock adc_clk clk Output 1
add_interface adc_dma_if conduit end
set_interface_property adc_dma_if associatedClock adc_clock
add_interface_port adc_dma_if adc_ddata ddata Output 64
add_interface_port adc_dma_if adc_dsync dsync Output 1
add_interface_port adc_dma_if adc_dovf dovf Input 1
add_interface_port adc_dma_if adc_dunf dunf Input 1
add_interface_port adc_dma_if adc_dwr dwr Output 1
# signal tap
add_interface adc_mon_if conduit end
set_interface_property adc_mon_if associatedClock adc_clock
add_interface_port adc_mon_if adc_mon_valid valid Output 1
add_interface_port adc_mon_if adc_mon_data data Output 56

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library/axi_ad9250/axi_ad9250_if.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9250_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status);
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output [27:0] adc_data_a;
output [27:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// internal registers
reg adc_status = 'd0;
// internal signals
wire [15:0] adc_data_a_s1_s;
wire [15:0] adc_data_a_s0_s;
wire [15:0] adc_data_b_s1_s;
wire [15:0] adc_data_b_s0_s;
// adc clock is the reference clock
assign adc_clk = rx_clk;
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
// adc channels
assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]};
assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]};
assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]};
assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]};
// status
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9250/axi_ad9250_ip.tcl Executable file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9250
adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9250_pnmon.v" \
"axi_ad9250_channel.v" \
"axi_ad9250_if.v" \
"axi_ad9250.v" ]
adi_ip_properties axi_ad9250
ipx::save_core [ipx::current_core]

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library/axi_ad9250/axi_ad9250_pnmon.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9250_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input [27:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg [27:0] adc_pn_data = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [27:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [27:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [27:0] pn23;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[22] ^ din[17];
dout[26] = din[21] ^ din[16];
dout[25] = din[20] ^ din[15];
dout[24] = din[19] ^ din[14];
dout[23] = din[18] ^ din[13];
dout[22] = din[17] ^ din[12];
dout[21] = din[16] ^ din[11];
dout[20] = din[15] ^ din[10];
dout[19] = din[14] ^ din[ 9];
dout[18] = din[13] ^ din[ 8];
dout[17] = din[12] ^ din[ 7];
dout[16] = din[11] ^ din[ 6];
dout[15] = din[10] ^ din[ 5];
dout[14] = din[ 9] ^ din[ 4];
dout[13] = din[ 8] ^ din[ 3];
dout[12] = din[ 7] ^ din[ 2];
dout[11] = din[ 6] ^ din[ 1];
dout[10] = din[ 5] ^ din[ 0];
dout[ 9] = din[ 4] ^ din[22] ^ din[17];
dout[ 8] = din[ 3] ^ din[21] ^ din[16];
dout[ 7] = din[ 2] ^ din[20] ^ din[15];
dout[ 6] = din[ 1] ^ din[19] ^ din[14];
dout[ 5] = din[ 0] ^ din[18] ^ din[13];
dout[ 4] = din[22] ^ din[12];
dout[ 3] = din[21] ^ din[11];
dout[ 2] = din[20] ^ din[10];
dout[ 1] = din[19] ^ din[ 9];
dout[ 0] = din[18] ^ din[ 8];
pn23 = dout;
end
endfunction
// PN9 function
function [27:0] pn9;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[ 8] ^ din[ 4];
dout[26] = din[ 7] ^ din[ 3];
dout[25] = din[ 6] ^ din[ 2];
dout[24] = din[ 5] ^ din[ 1];
dout[23] = din[ 4] ^ din[ 0];
dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 8] ^ din[ 0];
dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_in_s = {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[27:14] == adc_pn_data[27:14]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13: 0] == adc_pn_data[13: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 28'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_err_s;
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module axi_ad9467(
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// delay_clock
delay_clk,
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_doverflow,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready
);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
// delay clk
input delay_clk;
// dma interface
output adc_clk;
output adc_dwr;
output [15:0] adc_ddata;
input adc_doverflow;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg [31:0] up_rdata = 32'b0;
reg up_ack = 1'b0;
// internal clock and resets
wire up_clk;
wire up_rstn;
wire adc_rst;
wire adc_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [15:0] adc_data_if_s;
wire adc_or_s;
wire up_adc_or_s;
wire adc_ddr_edgesel_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire delay_rst;
wire delay_ack_s;
wire [ 4:0] delay_rdata_s;
wire delay_locked_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [31:0] up_rdata_common;
wire [31:0] up_rdata_channel;
wire up_ack_common;
wire up_ack_channel;
wire adc_pn_type_s;
wire [15:0] adc_channel_data_s;
wire adc_enable_s;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_dwr = 1'b1;
assign adc_ddata = adc_data_if_s;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 32'd0;
up_ack <= 1'd0;
end else begin
up_rdata <= up_rdata_channel | up_rdata_common;
up_ack <= up_ack_channel | up_ack_common;
end
end
// ADC data interface
axi_ad9467_if #(
.PCORE_BUFTYPE (PCORE_BUFTYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.adc_clk (adc_clk),
.adc_data (adc_data_if_s),
.adc_or (adc_or_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_clk (delay_clk),
.delay_ack (delay_ack_s),
.delay_rst (delay_rst),
.delay_rdata (delay_rdata_s),
.delay_locked (delay_locked_s));
// channel
axi_ad9467_channel #(.CHID(0)) i_channel (
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_data(adc_data_if_s),
.adc_or(adc_or_s),
.adc_dfmt_data(adc_channel_data_s),
.adc_enable(adc_enable_s),
.up_adc_pn_err(adc_pn_err_s),
.up_adc_pn_oos(adc_pn_oos_s),
.up_adc_or(up_adc_or_s),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_channel),
.up_ack(up_ack_channel));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID))
i_up_adc_common(
.mmcm_rst(),
.delay_clk(delay_clk),
.delay_ack_t(delay_ack_s),
.delay_locked(delay_locked_s),
.delay_rst(delay_rst),
.delay_sel(delay_sel_s),
.delay_rwn(delay_rwn_s),
.delay_addr(delay_addr_s),
.delay_wdata(delay_wdata_s),
.delay_rdata(delay_rdata_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(adc_ddr_edgesel_s),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_status_pn_err(adc_pn_err_s),
.adc_status_pn_oos(adc_pn_oos_s),
.adc_status_or(up_adc_or_s),
.adc_clk_ratio(32'b1),
.adc_status_ovf(adc_doverflow),
.adc_status_unf(1'b0),
.drp_clk(1'b0),
.drp_rdata(16'b0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.drp_ready(1'b0),
.drp_locked(1'b1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_rdata_common),
.up_ack(up_ack_common),
.up_usr_chanmax(),
.adc_usr_chanmax(8'b0));
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module axi_ad9467_channel(
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// core parameter
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [15:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire adc_pn_type_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
// PN sequence monitor
axi_ad9467_pnmon i_axi_ad9467_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.up_pn_type (adc_pn_type_s));
ad_datafmt #(.DATA_WIDTH(16)) i_datafmt (
.clk(adc_clk),
.valid(1'b1),
.data(adc_data),
.valid_out(),
.data_out(adc_dfmt_data),
.dfmt_enable(adc_dfmt_enable_s),
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
// adc channel control
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_pn_sel (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9467_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
adc_ddr_edgesel,
// delay control signals
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_clk,
delay_ack,
delay_rst,
delay_rdata,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter C_DEVICE_7SERIES = 0;
parameter C_DEVICE_VIRTEX6 = 1;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
input adc_ddr_edgesel;
// delay control signals
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
input delay_clk;
input delay_rst;
output delay_ack;
output [ 4:0] delay_rdata;
output delay_locked;
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg [ 7:0] adc_data_n_d = 'd0;
reg [ 7:0] adc_dmux_a = 'd0;
reg [ 7:0] adc_dmux_b = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or = 'd0;
reg [ 8:0] delay_ld = 'd0;
reg delay_ack = 'd0;
reg [ 4:0] delay_rdata = 'd0;
wire [ 4:0] delay_rdata_s[8:0];
wire [ 7:0] adc_data_ibuf_s;
wire [ 7:0] adc_data_idelay_s;
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_ibuf_s;
wire adc_or_idelay_s;
wire adc_or_p_s;
wire adc_or_n_s;
wire adc_clk_ibuf_s;
genvar l_inst;
// The adc data is 8bits ddr, and here it is demuxed to 16bits.
// The samples may be selected to be either positive first,
// or negative first.
always @(posedge adc_clk) begin
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_n_d <= adc_data_n;
adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p;
adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p : adc_data_n_d;
adc_data[15] <= adc_dmux_b[7];
adc_data[14] <= adc_dmux_a[7];
adc_data[13] <= adc_dmux_b[6];
adc_data[12] <= adc_dmux_a[6];
adc_data[11] <= adc_dmux_b[5];
adc_data[10] <= adc_dmux_a[5];
adc_data[ 9] <= adc_dmux_b[4];
adc_data[ 8] <= adc_dmux_a[4];
adc_data[ 7] <= adc_dmux_b[3];
adc_data[ 6] <= adc_dmux_a[3];
adc_data[ 5] <= adc_dmux_b[2];
adc_data[ 4] <= adc_dmux_a[2];
adc_data[ 3] <= adc_dmux_b[1];
adc_data[ 2] <= adc_dmux_a[1];
adc_data[ 1] <= adc_dmux_b[0];
adc_data[ 0] <= adc_dmux_a[0];
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin
adc_or <= 1'b1;
end else begin
adc_or <= 1'b0;
end
end
// The delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'd8 : delay_ld <= 9'h100;
8'd7 : delay_ld <= 9'h080;
8'd6 : delay_ld <= 9'h040;
8'd5 : delay_ld <= 9'h020;
8'd4 : delay_ld <= 9'h010;
8'd3 : delay_ld <= 9'h008;
8'd2 : delay_ld <= 9'h004;
8'd1 : delay_ld <= 9'h002;
8'd0 : delay_ld <= 9'h001;
default: delay_ld <= 9'h000;
endcase
end else begin
delay_ld <= 9'h000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'd8 : delay_rdata <= delay_rdata_s[8];
8'd7 : delay_rdata <= delay_rdata_s[7];
8'd6 : delay_rdata <= delay_rdata_s[6];
8'd5 : delay_rdata <= delay_rdata_s[5];
8'd4 : delay_rdata <= delay_rdata_s[4];
8'd3 : delay_rdata <= delay_rdata_s[3];
8'd2 : delay_rdata <= delay_rdata_s[2];
8'd1 : delay_rdata <= delay_rdata_s[1];
8'd0 : delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack <= ~delay_ack;
end
end
// The data interface, data signals goes through a LVDS input buffer, then
// a delay element (1/32th of a 200MHz clock) and finally an input DDR demux.
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
IBUFDS i_data_ibuf (
.I (adc_data_in_p[l_inst]),
.IB (adc_data_in_n[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.RST (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_data_ibuf_s[l_inst]),
.DATAOUT (adc_data_idelay_s[l_inst]),
.LD (delay_ld[l_inst]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[l_inst]));
end
IDDR #(
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.SRTYPE ("ASYNC"))
i_data_ddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (adc_clk),
.D (adc_data_idelay_s[l_inst]),
.Q1 (adc_data_p_s[l_inst]),
.Q2 (adc_data_n_s[l_inst]));
end
endgenerate
// The over-range interface, it follows a similar path as the data signals.
IBUFDS i_or_ibuf (
.I (adc_data_or_p),
.IB (adc_data_or_n),
.O (adc_or_ibuf_s));
generate
if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.RST (delay_ld[8]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[8]));
end else begin
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_or_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (delay_clk),
.IDATAIN (adc_or_ibuf_s),
.DATAOUT (adc_or_idelay_s),
.LD (delay_ld[8]),
.CNTVALUEIN (delay_wdata),
.CNTVALUEOUT (delay_rdata_s[8]));
end
endgenerate
IDDR #(
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.SRTYPE ("ASYNC"))
i_or_ddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (adc_clk),
.D (adc_or_idelay_s),
.Q1 (adc_or_p_s),
.Q2 (adc_or_n_s));
// The clock path is a simple clock buffer after a LVDS input buffer.
// It is possible for this logic to be replaced with a OSERDES based data capture.
// The reason for such a simple interface here is because this reference design
// is used for various boards (native fmc and/or evaluation boards). The pinouts
// of the FPGA - ADC interface is probably do not allow a OSERDES placement.
IBUFGDS i_clk_ibuf (
.I (adc_clk_in_p),
.IB (adc_clk_in_n),
.O (adc_clk_ibuf_s));
generate
if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
BUFR #(.BUFR_DIVIDE ("BYPASS")) i_clk_gbuf (
.CLR (1'b0),
.CE (1'b1),
.I (adc_clk_ibuf_s),
.O (adc_clk));
end else begin
BUFG i_clk_gbuf (
.I (adc_clk_ibuf_s),
.O (adc_clk));
end
endgenerate
// The delay controller. Refer to Xilinx doc. for details.
// The GROUP directive controls which delay elements this is associated with.
(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9467
adi_ip_files axi_ad9467 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad9467_pnmon.v" \
"axi_ad9467_if.v" \
"axi_ad9467_channel.v" \
"axi_ad9467.v"]
adi_ip_properties axi_ad9467
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9467_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
up_pn_type);
// adc interface
input adc_clk;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input up_pn_type;
reg adc_pn_type_m1 = 'd0;
reg adc_pn_type_m2 = 'd0;
reg adc_pn_type = 'd0;
reg adc_pn_en = 'd0;
reg [15:0] adc_data_d = 'd0;
reg [31:0] adc_pn_data = 'd0;
reg adc_pn_en_d = 'd0;
reg adc_pn_match = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
reg [ 4:0] adc_pn_err_count = 'd0;
reg adc_pn_err = 'd0;
wire [31:0] adc_pn_data_in_s;
wire adc_pn_match0_s;
wire adc_pn_match1_s;
wire adc_pn_match2_s;
wire adc_pn_match_s;
wire [31:0] adc_pn_data_s;
wire adc_pn_err_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// This PN sequence checking algorithm is commonly used is most applications.
// It is a simple function generated based on the OOS status.
// If OOS is asserted (PN is OUT of sync):
// The next sequence is generated from the incoming data.
// If 16 sequences match CONSECUTIVELY, OOS is cleared (de-asserted).
// If OOS is de-asserted (PN is IN sync)
// The next sequence is generated from the current sequence.
// If 64 sequences mismatch CONSECUTIVELY, OOS is set (asserted).
// If OOS is de-asserted, any spurious mismatches sets the ERROR register.
// Ideally, processor should make sure both OOS == 0x0 AND ERR == 0x0.
assign adc_pn_data_in_s[31:16] = {~adc_data_d[15], adc_data_d[14:0]};
assign adc_pn_data_in_s[15:0] = {~adc_data[15], adc_data[14:0]};
assign adc_pn_match0_s = (adc_pn_data_in_s[31:16] == adc_pn_data[31:16]) ? 1'b1 : 1'b0;
assign adc_pn_match1_s = (adc_pn_data_in_s[15:0] == adc_pn_data[15:0]) ? 1'b1 : 1'b0;
assign adc_pn_match2_s = ((adc_data == 16'd0) && (adc_data_d == 16'd0)) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match0_s & adc_pn_match1_s & adc_pn_match2_s;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match);
// PN running sequence
always @(posedge adc_clk) begin
adc_pn_type_m1 <= up_pn_type;
adc_pn_type_m2 <= adc_pn_type_m1;
adc_pn_type <= adc_pn_type_m2;
adc_pn_en <= ~adc_pn_en;
adc_data_d <= adc_data;
if (adc_pn_en == 1'b1) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
end
// PN OOS and counters (16 to clear, 64 to set). These numbers are actually determined
// based on BER parameters set by the system (usually in network applications).
always @(posedge adc_clk) begin
adc_pn_en_d <= adc_pn_en;
adc_pn_match <= adc_pn_match_s;
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_oos == 1'b1) begin
if (adc_pn_match == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd0;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= 'd1;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd1;
end
end else begin
if (adc_pn_match == 1'b0) begin
if (adc_pn_oos_count >= 64) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd1;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= 'd0;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= 'd0;
end
end
end
end
// The error state is streched to multiple adc clocks such that processor
// has enough time to sample the error condition.
always @(posedge adc_clk) begin
if (adc_pn_en_d == 1'b1) begin
if (adc_pn_err_s == 1'b1) begin
adc_pn_err_count <= 5'h10;
end else if (adc_pn_err_count[4] == 1'b1) begin
adc_pn_err_count <= adc_pn_err_count + 1'b1;
end
end
adc_pn_err <= adc_pn_err_count[4];
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9671 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_4L_2L_N = 1;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// dma interface
output adc_clk;
output adc_dwr;
output [127:0] adc_ddata;
output adc_dsync;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [127:0] adc_mon_data;
// internal registers
reg [ 2:0] adc_data_cnt = 'd0;
reg adc_dwr = 'd0;
reg adc_dsync = 'd0;
reg [127:0] adc_ddata = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg up_ack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire adc_status_s;
wire adc_valid_s;
wire [ 15:0] adc_data_s[7:0];
wire [ 7:0] adc_or_s;
wire [ 7:0] adc_dfmt_valid_s;
wire [ 15:0] adc_dfmt_data_s[7:0];
wire [ 7:0] adc_enable_s;
wire [ 7:0] up_adc_pn_err_s;
wire [ 7:0] up_adc_pn_oos_s;
wire [ 7:0] up_adc_or_s;
wire [ 31:0] up_adc_channel_rdata_s[7:0];
wire [ 7:0] up_adc_channel_ack_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire [ 31:0] up_wdata_s;
wire [ 31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[ 15: 0] = adc_dfmt_data_s[0];
assign adc_mon_data[ 31: 16] = adc_dfmt_data_s[1];
assign adc_mon_data[ 47: 32] = adc_dfmt_data_s[2];
assign adc_mon_data[ 63: 48] = adc_dfmt_data_s[3];
assign adc_mon_data[ 79: 64] = adc_dfmt_data_s[4];
assign adc_mon_data[ 95: 80] = adc_dfmt_data_s[5];
assign adc_mon_data[111: 96] = adc_dfmt_data_s[6];
assign adc_mon_data[127:112] = adc_dfmt_data_s[7];
// adc channels - dma interface
always @(posedge adc_clk) begin
if (adc_dfmt_valid_s == 8'hff) begin
adc_data_cnt <= adc_data_cnt + 1'b1;
case (adc_enable_s)
8'b11111111: begin
adc_dwr <= 1'b1;
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[7],
adc_dfmt_data_s[6],
adc_dfmt_data_s[5],
adc_dfmt_data_s[4],
adc_dfmt_data_s[3],
adc_dfmt_data_s[2],
adc_dfmt_data_s[1],
adc_dfmt_data_s[0]};
end
8'b10000000: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[0], adc_ddata[127:16]};
end
8'b01000000: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[1], adc_ddata[127:16]};
end
8'b00100000: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[2], adc_ddata[127:16]};
end
8'b00010000: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[3], adc_ddata[127:16]};
end
8'b00001000: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[4], adc_ddata[127:16]};
end
8'b00000100: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[5], adc_ddata[127:16]};
end
8'b00000010: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[6], adc_ddata[127:16]};
end
8'b00000001: begin
adc_dwr <= (& adc_data_cnt);
adc_dsync <= 1'b1;
adc_ddata <= {adc_dfmt_data_s[7], adc_ddata[127:16]};
end
default: begin
adc_dwr <= 1'b1;
adc_dsync <= 1'b1;
adc_ddata <= {8{16'hdead}};
end
endcase
end else begin
adc_data_cnt <= adc_data_cnt;
adc_dwr <= 1'b0;
adc_dsync <= 1'b0;
adc_ddata <= 128'd0;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_adc_status_pn_err <= | up_adc_pn_err_s;
up_adc_status_pn_oos <= | up_adc_pn_oos_s;
up_adc_status_or <= | up_adc_or_s;
up_ack <= up_adc_common_ack_s | (| up_adc_channel_ack_s);
up_rdata <= up_adc_common_rdata_s |
up_adc_channel_rdata_s[0] |
up_adc_channel_rdata_s[1] |
up_adc_channel_rdata_s[2] |
up_adc_channel_rdata_s[3] |
up_adc_channel_rdata_s[4] |
up_adc_channel_rdata_s[5] |
up_adc_channel_rdata_s[6] |
up_adc_channel_rdata_s[7];
end
end
// main (device interface)
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N)) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
.adc_data_a (adc_data_s[0]),
.adc_or_a (adc_or_s[0]),
.adc_data_b (adc_data_s[1]),
.adc_or_b (adc_or_s[1]),
.adc_data_c (adc_data_s[2]),
.adc_or_c (adc_or_s[2]),
.adc_data_d (adc_data_s[3]),
.adc_or_d (adc_or_s[3]),
.adc_data_e (adc_data_s[4]),
.adc_or_e (adc_or_s[4]),
.adc_data_f (adc_data_s[5]),
.adc_or_f (adc_or_s[5]),
.adc_data_g (adc_data_s[6]),
.adc_or_g (adc_or_s[6]),
.adc_data_h (adc_data_s[7]),
.adc_or_h (adc_or_s[7]),
.adc_status (adc_status_s));
// channels
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_channel
axi_ad9671_channel #(.CHID(n)) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s[n]),
.adc_or (adc_or_s[n]),
.adc_dfmt_valid (adc_dfmt_valid_s[n]),
.adc_dfmt_data (adc_dfmt_data_s[n]),
.adc_enable (adc_enable_s[n]),
.up_adc_pn_err (up_adc_pn_err_s[n]),
.up_adc_pn_oos (up_adc_pn_oos_s[n]),
.up_adc_or (up_adc_or_s[n]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_s[n]),
.up_ack (up_adc_channel_ack_s[n]));
end
endgenerate
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
.delay_rwn (),
.delay_addr (),
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b0),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ready (1'd0),
.drp_locked (1'd0),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd7),
.dma_bw (32'd128),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9671_channel (
// adc interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
adc_or,
// channel interface
adc_dfmt_valid,
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input adc_valid;
input [15:0] adc_data;
input adc_or;
// channel interface
output adc_dfmt_valid;
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_pn_type_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// instantiations
axi_ad9671_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data),
.valid_out (adc_dfmt_valid),
.data_out (adc_dfmt_data),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_pn_sel (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9671_if (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// adc data output
adc_clk,
adc_rst,
adc_valid,
adc_data_a,
adc_or_a,
adc_data_b,
adc_or_b,
adc_data_c,
adc_or_c,
adc_data_d,
adc_or_d,
adc_data_e,
adc_or_e,
adc_data_f,
adc_or_f,
adc_data_g,
adc_or_g,
adc_data_h,
adc_or_h,
adc_status);
// parameters
parameter PCORE_4L_2L_N = 1;
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [(64*PCORE_4L_2L_N)+63:0] rx_data;
// adc data output
output adc_clk;
input adc_rst;
output adc_valid;
output [ 15:0] adc_data_a;
output adc_or_a;
output [ 15:0] adc_data_b;
output adc_or_b;
output [ 15:0] adc_data_c;
output adc_or_c;
output [ 15:0] adc_data_d;
output adc_or_d;
output [ 15:0] adc_data_e;
output adc_or_e;
output [ 15:0] adc_data_f;
output adc_or_f;
output [ 15:0] adc_data_g;
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
output adc_status;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
assign adc_or_c = 'd0;
assign adc_or_d = 'd0;
assign adc_or_e = 'd0;
assign adc_or_f = 'd0;
assign adc_or_g = 'd0;
assign adc_or_h = 'd0;
assign adc_data_a = {int_data[ 7: 0], int_data[ 15: 8]};
assign adc_data_b = {int_data[ 23: 16], int_data[ 31: 24]};
assign adc_data_c = {int_data[ 39: 32], int_data[ 47: 40]};
assign adc_data_d = {int_data[ 55: 48], int_data[ 63: 56]};
assign adc_data_e = {int_data[ 71: 64], int_data[ 79: 72]};
assign adc_data_f = {int_data[ 87: 80], int_data[ 95: 88]};
assign adc_data_g = {int_data[103: 96], int_data[111:104]};
assign adc_data_h = {int_data[119:112], int_data[127:120]};
always @(posedge rx_clk) begin
if (PCORE_4L_2L_N == 1'b1) begin
int_valid <= 1'b1;
int_data <= rx_data;
end else begin
int_valid <= ~int_valid;
int_data <= {rx_data[63:0], int_data[127:64]};
end
end
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9671
adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \
"axi_ad9671_if.v" \
"axi_ad9671.v" ]
adi_ip_properties axi_ad9671
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9671_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pn_type);
// adc interface
input adc_clk;
input adc_valid;
input [15:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
// internal registers
reg adc_pn_en = 'd0;
reg [15:0] adc_data_d = 'd0;
reg [31:0] adc_pn_data = 'd0;
reg adc_pn_valid = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire adc_pn_valid_s;
wire [31:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [31:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// PN23 function
function [31:0] pn23;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
dout[29] = din[20] ^ din[15];
dout[28] = din[19] ^ din[14];
dout[27] = din[18] ^ din[13];
dout[26] = din[17] ^ din[12];
dout[25] = din[16] ^ din[11];
dout[24] = din[15] ^ din[10];
dout[23] = din[14] ^ din[ 9];
dout[22] = din[13] ^ din[ 8];
dout[21] = din[12] ^ din[ 7];
dout[20] = din[11] ^ din[ 6];
dout[19] = din[10] ^ din[ 5];
dout[18] = din[ 9] ^ din[ 4];
dout[17] = din[ 8] ^ din[ 3];
dout[16] = din[ 7] ^ din[ 2];
dout[15] = din[ 6] ^ din[ 1];
dout[14] = din[ 5] ^ din[ 0];
dout[13] = din[ 4] ^ din[22] ^ din[17];
dout[12] = din[ 3] ^ din[21] ^ din[16];
dout[11] = din[ 2] ^ din[20] ^ din[15];
dout[10] = din[ 1] ^ din[19] ^ din[14];
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
dout[ 8] = din[22] ^ din[12];
dout[ 7] = din[21] ^ din[11];
dout[ 6] = din[20] ^ din[10];
dout[ 5] = din[19] ^ din[ 9];
dout[ 4] = din[18] ^ din[ 8];
dout[ 3] = din[17] ^ din[ 7];
dout[ 2] = din[16] ^ din[ 6];
dout[ 1] = din[15] ^ din[ 5];
dout[ 0] = din[14] ^ din[ 4];
pn23 = dout;
end
endfunction
// PN9 function
function [31:0] pn9;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[ 8] ^ din[ 4];
dout[30] = din[ 7] ^ din[ 3];
dout[29] = din[ 6] ^ din[ 2];
dout[28] = din[ 5] ^ din[ 1];
dout[27] = din[ 4] ^ din[ 0];
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 8] ^ din[ 0];
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
pn9 = dout;
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_valid_s = adc_valid & adc_pn_en;
assign adc_pn_data_in_s = {~adc_data[15], adc_data[14:0], ~adc_data_d[15], adc_data_d[14:0]};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[31:16] == adc_pn_data[31:16]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[15: 0] == adc_pn_data[15: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 32'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_pn_en <= ~adc_pn_en;
adc_data_d <= adc_data;
end
end
always @(posedge adc_clk) begin
if (adc_pn_valid_s == 1'b1) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
end
end
end
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
adc_pn_valid <= adc_pn_valid_s;
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_valid & adc_pn_err_s;
if (adc_pn_valid == 1'b1) begin
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

28
library/axi_dmac/axi_dmac_alt.v
View File

@ -208,7 +208,7 @@ module axi_dmac_alt (
input s_axi_aresetn;
input s_axi_awvalid;
input [13:0] s_axi_awaddr;
input [ 1:0] s_axi_awid;
input [ 2:0] s_axi_awid;
input [ 7:0] s_axi_awlen;
input [ 2:0] s_axi_awsize;
input [ 1:0] s_axi_awburst;
@ -223,11 +223,11 @@ module axi_dmac_alt (
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [ 1:0] s_axi_bid;
output [ 2:0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
input [ 1:0] s_axi_arid;
input [ 2:0] s_axi_arid;
input [ 7:0] s_axi_arlen;
input [ 2:0] s_axi_arsize;
input [ 1:0] s_axi_arburst;
@ -238,7 +238,7 @@ module axi_dmac_alt (
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rid;
output [ 2:0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
@ -248,7 +248,7 @@ module axi_dmac_alt (
input m_dest_axi_aresetn;
output m_dest_axi_awvalid;
output [31:0] m_dest_axi_awaddr;
output [ 1:0] m_dest_axi_awid;
output [ 2:0] m_dest_axi_awid;
output [ 7:0] m_dest_axi_awlen;
output [ 2:0] m_dest_axi_awsize;
output [ 1:0] m_dest_axi_awburst;
@ -263,11 +263,11 @@ module axi_dmac_alt (
input m_dest_axi_wready;
input m_dest_axi_bvalid;
input [ 1:0] m_dest_axi_bresp;
input [ 1:0] m_dest_axi_bid;
input [ 2:0] m_dest_axi_bid;
output m_dest_axi_bready;
output m_dest_axi_arvalid;
output [31:0] m_dest_axi_araddr;
output [ 1:0] m_dest_axi_arid;
output [ 2:0] m_dest_axi_arid;
output [ 7:0] m_dest_axi_arlen;
output [ 2:0] m_dest_axi_arsize;
output [ 1:0] m_dest_axi_arburst;
@ -278,7 +278,7 @@ module axi_dmac_alt (
input m_dest_axi_rvalid;
input [ 1:0] m_dest_axi_rresp;
input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
input [ 1:0] m_dest_axi_rid;
input [ 2:0] m_dest_axi_rid;
input m_dest_axi_rlast;
output m_dest_axi_rready;
@ -288,7 +288,7 @@ module axi_dmac_alt (
input m_src_axi_aresetn;
output m_src_axi_awvalid;
output [31:0] m_src_axi_awaddr;
output [ 1:0] m_src_axi_awid;
output [ 2:0] m_src_axi_awid;
output [ 7:0] m_src_axi_awlen;
output [ 2:0] m_src_axi_awsize;
output [ 1:0] m_src_axi_awburst;
@ -303,11 +303,11 @@ module axi_dmac_alt (
input m_src_axi_wready;
input m_src_axi_bvalid;
input [ 1:0] m_src_axi_bresp;
input [ 1:0] m_src_axi_bid;
input [ 2:0] m_src_axi_bid;
output m_src_axi_bready;
output m_src_axi_arvalid;
output [31:0] m_src_axi_araddr;
output [ 1:0] m_src_axi_arid;
output [ 2:0] m_src_axi_arid;
output [ 7:0] m_src_axi_arlen;
output [ 2:0] m_src_axi_arsize;
output [ 1:0] m_src_axi_arburst;
@ -318,7 +318,7 @@ module axi_dmac_alt (
input m_src_axi_rvalid;
input [ 1:0] m_src_axi_rresp;
input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
input [ 1:0] m_src_axi_rid;
input [ 2:0] m_src_axi_rid;
input m_src_axi_rlast;
output m_src_axi_rready;
@ -349,8 +349,8 @@ module axi_dmac_alt (
// defaults
assign s_axi_bid = 2'd0;
assign s_axi_rid = 2'd0;
assign s_axi_bid = 3'd0;
assign s_axi_rid = 3'd0;
assign s_axi_rlast = 1'd0;
// instantiation

27
library/axi_dmac/axi_dmac_hw.tcl
View File

@ -19,6 +19,8 @@ add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/commo
add_fileset_file axi_fifo.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/axi_fifo.v
add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray.v
add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v
add_fileset_file inc_id.h VERILOG_INCLUDE PATH inc_id.h
add_fileset_file resp.h VERILOG_INCLUDE PATH resp.h
add_fileset_file address_generator.v VERILOG PATH address_generator.v
add_fileset_file data_mover.v VERILOG PATH data_mover.v
add_fileset_file request_arb.v VERILOG PATH request_arb.v
@ -36,6 +38,7 @@ add_fileset_file splitter.v VERILOG PATH splitter.v
add_fileset_file response_generator.v VERILOG PATH response_generator.v
add_fileset_file axi_dmac.v VERILOG PATH axi_dmac.v
add_fileset_file axi_repack.v VERILOG PATH axi_repack.v
add_fileset_file axi_dmac_alt.v VERILOG PATH axi_dmac_alt.v
# parameters
@ -173,7 +176,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1
add_interface_port s_axi s_axi_rresp rresp Output 2
add_interface_port s_axi s_axi_rdata rdata Output 32
add_interface_port s_axi s_axi_rready rready Input 1
add_interface_port s_axi s_axi_awid awid Input 2
add_interface_port s_axi s_axi_awid awid Input 3
add_interface_port s_axi s_axi_awlen awlen Input 8
add_interface_port s_axi s_axi_awsize awsize Input 3
add_interface_port s_axi s_axi_awburst awburst Input 2
@ -181,15 +184,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
add_interface_port s_axi s_axi_awcache awcache Input 4
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_wlast wlast Input 1
add_interface_port s_axi s_axi_bid bid Output 2
add_interface_port s_axi s_axi_arid arid Input 2
add_interface_port s_axi s_axi_bid bid Output 3
add_interface_port s_axi s_axi_arid arid Input 3
add_interface_port s_axi s_axi_arlen arlen Input 8
add_interface_port s_axi s_axi_arsize arsize Input 3
add_interface_port s_axi s_axi_arburst arburst Input 2
add_interface_port s_axi s_axi_arlock arlock Input 1
add_interface_port s_axi s_axi_arcache arcache Input 4
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_rid rid Output 2
add_interface_port s_axi s_axi_rid rid Output 3
add_interface_port s_axi s_axi_rlast rlast Output 1
# conditional interface
@ -227,7 +230,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
add_interface_port m_dest_axi m_dest_axi_awid awid Output 2
add_interface_port m_dest_axi m_dest_axi_awid awid Output 3
add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
@ -235,15 +238,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
add_interface_port m_dest_axi m_dest_axi_bid bid Input 2
add_interface_port m_dest_axi m_dest_axi_arid arid Output 2
add_interface_port m_dest_axi m_dest_axi_bid bid Input 3
add_interface_port m_dest_axi m_dest_axi_arid arid Output 3
add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
add_interface_port m_dest_axi m_dest_axi_rid rid Input 2
add_interface_port m_dest_axi m_dest_axi_rid rid Input 3
add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
}
@ -276,7 +279,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rready rready Output 1
add_interface_port m_src_axi m_src_axi_awid awid Output 2
add_interface_port m_src_axi m_src_axi_awid awid Output 3
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
@ -284,15 +287,15 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
add_interface_port m_src_axi m_src_axi_bid bid Input 2
add_interface_port m_src_axi m_src_axi_arid arid Output 2
add_interface_port m_src_axi m_src_axi_bid bid Input 3
add_interface_port m_src_axi m_src_axi_arid arid Output 3
add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
add_interface_port m_src_axi m_src_axi_rid rid Input 2
add_interface_port m_src_axi m_src_axi_rid rid Input 3
add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
}

707
library/axi_jesd_gt/axi_jesd_gt.v Normal file
View File

@ -0,0 +1,707 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_jesd_gt (
// physical interface
ref_clk_q,
ref_clk_c,
rx_data_p,
rx_data_n,
rx_sync,
rx_sysref,
rx_ext_sysref,
tx_data_p,
tx_data_n,
tx_sync,
tx_sysref,
tx_ext_sysref,
// core interface
rx_rst,
rx_clk,
rx_data,
rx_gt_charisk,
rx_gt_disperr,
rx_gt_notintable,
rx_gt_data,
rx_rst_done,
rx_ip_comma_align,
rx_ip_sync,
rx_ip_sof,
rx_ip_data,
tx_rst,
tx_clk,
tx_data,
tx_gt_charisk,
tx_gt_data,
tx_rst_done,
tx_ip_sync,
tx_ip_sof,
tx_ip_data,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready,
// master interface
m_axi_aclk,
m_axi_aresetn,
m_axi_awvalid,
m_axi_awaddr,
m_axi_awprot,
m_axi_awready,
m_axi_wvalid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wready,
m_axi_bvalid,
m_axi_bresp,
m_axi_bready,
m_axi_arvalid,
m_axi_araddr,
m_axi_arprot,
m_axi_arready,
m_axi_rvalid,
m_axi_rdata,
m_axi_rresp,
m_axi_rready,
// drp clock
drp_clk,
// es debug interface
es_dbg_data,
es_dbg_trigger,
// jesd debug interface
rx_mon_data,
rx_mon_trigger,
tx_mon_data,
tx_mon_trigger);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_LANES = 4;
parameter PCORE_QPLL_REFCLK_DIV = 1;
parameter PCORE_QPLL_CFG = 27'h0680181;
parameter PCORE_QPLL_FBDIV_RATIO = 1'b1;
parameter PCORE_QPLL_FBDIV = 10'b0000110000;
parameter PCORE_CPLL_FBDIV = 2;
parameter PCORE_RX_OUT_DIV = 1;
parameter PCORE_TX_OUT_DIV = 1;
parameter PCORE_RX_CLK25_DIV = 20;
parameter PCORE_TX_CLK25_DIV = 20;
parameter PCORE_PMA_RSV = 32'h001E7080;
parameter PCORE_RX_CDR_CFG = 72'h0b000023ff10400020;
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
// physical interface
input ref_clk_q;
input ref_clk_c;
input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p;
input [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n;
output rx_sync;
output rx_sysref;
input rx_ext_sysref;
output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p;
output [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n;
input tx_sync;
output tx_sysref;
input tx_ext_sysref;
// core interface
output rx_rst;
output rx_clk;
output [((PCORE_NUM_OF_LANES*32)-1):0] rx_data;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr;
output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable;
output [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data;
output rx_rst_done;
input rx_ip_comma_align;
input rx_ip_sync;
input [ 3:0] rx_ip_sof;
input [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data;
output tx_rst;
output tx_clk;
input [((PCORE_NUM_OF_LANES*32)-1):0] tx_data;
input [((PCORE_NUM_OF_LANES* 4)-1):0] tx_gt_charisk;
input [((PCORE_NUM_OF_LANES*32)-1):0] tx_gt_data;
output tx_rst_done;
output tx_ip_sync;
input [ 3:0] tx_ip_sof;
output [((PCORE_NUM_OF_LANES*32)-1):0] tx_ip_data;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [ 31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [ 31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [ 31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// master interface
input m_axi_aclk;
input m_axi_aresetn;
output m_axi_awvalid;
output [ 31:0] m_axi_awaddr;
output [ 2:0] m_axi_awprot;
input m_axi_awready;
output m_axi_wvalid;
output [ 31:0] m_axi_wdata;
output [ 3:0] m_axi_wstrb;
input m_axi_wready;
input m_axi_bvalid;
input [ 1:0] m_axi_bresp;
output m_axi_bready;
output m_axi_arvalid;
output [ 31:0] m_axi_araddr;
output [ 2:0] m_axi_arprot;
input m_axi_arready;
input m_axi_rvalid;
input [ 31:0] m_axi_rdata;
input [ 1:0] m_axi_rresp;
output m_axi_rready;
// drp clock
input drp_clk;
// es debug interface
output [275:0] es_dbg_data;
output [ 7:0] es_dbg_trigger;
// jesd debug interface
output [((PCORE_NUM_OF_LANES*82)+5):0] rx_mon_data;
output [((PCORE_NUM_OF_LANES* 1)+1):0] rx_mon_trigger;
output [((PCORE_NUM_OF_LANES*36)+5):0] tx_mon_data;
output [ 5:0] tx_mon_trigger;
// reset and clocks
wire gt_pll_rst;
wire gt_rx_rst;
wire gt_tx_rst;
wire qpll_clk_0;
wire qpll_ref_clk_0;
wire qpll_clk_1;
wire qpll_ref_clk_1;
wire [ 7:0] qpll_clk;
wire [ 7:0] qpll_ref_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk;
wire axi_rstn;
wire axi_clk;
wire up_rstn;
wire up_clk;
wire drp_rst;
// internal signals
wire [ 8:0] up_status_extn_s;
wire [ 8:0] rx_rst_done_extn_s;
wire [ 8:0] rx_pll_locked_extn_s;
wire [ 8:0] tx_rst_done_extn_s;
wire [ 8:0] tx_pll_locked_extn_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s;
wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s;
wire [ 15:0] drp_rdata_gt_s[15:0];
wire drp_ready_gt_s[15:0];
wire [ 7:0] drp_rx_rate_gt_s[15:0];
wire qpll_locked_0_s;
wire qpll_locked_1_s;
wire [ 7:0] qpll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_pll_locked_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_rst_done_s;
wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_pll_locked_s;
wire up_cpll_pd_s;
wire [ 1:0] up_rx_sys_clk_sel_s;
wire [ 2:0] up_rx_out_clk_sel_s;
wire [ 1:0] up_tx_sys_clk_sel_s;
wire [ 2:0] up_tx_out_clk_sel_s;
wire drp_sel_s;
wire drp_wr_s;
wire [ 11:0] drp_addr_s;
wire [ 15:0] drp_wdata_s;
wire [ 15:0] drp_rdata_s;
wire drp_ready_s;
wire [ 7:0] drp_lanesel_s;
wire [ 7:0] drp_rx_rate_s;
wire es_sel_s;
wire es_wr_s;
wire [ 11:0] es_addr_s;
wire [ 15:0] es_wdata_s;
wire [ 15:0] es_rdata_s;
wire es_ready_s;
wire es_start_s;
wire es_stop_s;
wire es_init_s;
wire [ 15:0] es_sdata0_s;
wire [ 15:0] es_sdata1_s;
wire [ 15:0] es_sdata2_s;
wire [ 15:0] es_sdata3_s;
wire [ 15:0] es_sdata4_s;
wire [ 15:0] es_qdata0_s;
wire [ 15:0] es_qdata1_s;
wire [ 15:0] es_qdata2_s;
wire [ 15:0] es_qdata3_s;
wire [ 15:0] es_qdata4_s;
wire [ 4:0] es_prescale_s;
wire [ 11:0] es_hoffset_min_s;
wire [ 11:0] es_hoffset_max_s;
wire [ 11:0] es_hoffset_step_s;
wire [ 7:0] es_voffset_min_s;
wire [ 7:0] es_voffset_max_s;
wire [ 7:0] es_voffset_step_s;
wire [ 31:0] es_start_addr_s;
wire es_dmaerr_s;
wire es_status_s;
wire up_sel_s;
wire up_wr_s;
wire [ 13:0] up_addr_s;
wire [ 31:0] up_wdata_s;
wire [ 31:0] up_rdata_s;
wire up_ack_s;
// debug interface
assign rx_mon_data = {rx_sync, rx_sysref, rx_ip_sof, rx_ip_data, rx_mon_data_s};
assign rx_mon_trigger = {rx_sync, rx_sysref, rx_mon_trigger_s};
assign tx_mon_data = {tx_sync, tx_sysref, tx_ip_sof, tx_gt_charisk, tx_gt_data};
assign tx_mon_trigger = {tx_sync, tx_sysref, tx_ip_sof};
// signal name changes
assign axi_rstn = m_axi_aresetn;
assign axi_clk = m_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// drp is simply over-defined to avoid errors with singluar entries
assign up_status_extn_s = 9'hff;
assign rx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_rst_done_s};
assign rx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], rx_pll_locked_s};
assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s};
assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s};
assign rx_rst_done = | rx_rst_done_s;
assign tx_rst_done = | tx_rst_done_s;
assign drp_rdata_s = drp_rdata_gt_s[15] | drp_rdata_gt_s[14] |
drp_rdata_gt_s[13] | drp_rdata_gt_s[12] |
drp_rdata_gt_s[11] | drp_rdata_gt_s[10] |
drp_rdata_gt_s[ 9] | drp_rdata_gt_s[ 8] |
drp_rdata_gt_s[ 7] | drp_rdata_gt_s[ 6] |
drp_rdata_gt_s[ 5] | drp_rdata_gt_s[ 4] |
drp_rdata_gt_s[ 3] | drp_rdata_gt_s[ 2] |
drp_rdata_gt_s[ 1] | drp_rdata_gt_s[ 0];
assign drp_ready_s = drp_ready_gt_s[15] | drp_ready_gt_s[14] |
drp_ready_gt_s[13] | drp_ready_gt_s[12] |
drp_ready_gt_s[11] | drp_ready_gt_s[10] |
drp_ready_gt_s[ 9] | drp_ready_gt_s[ 8] |
drp_ready_gt_s[ 7] | drp_ready_gt_s[ 6] |
drp_ready_gt_s[ 5] | drp_ready_gt_s[ 4] |
drp_ready_gt_s[ 3] | drp_ready_gt_s[ 2] |
drp_ready_gt_s[ 1] | drp_ready_gt_s[ 0];
assign drp_rx_rate_s = drp_rx_rate_gt_s[15] | drp_rx_rate_gt_s[14] |
drp_rx_rate_gt_s[13] | drp_rx_rate_gt_s[12] |
drp_rx_rate_gt_s[11] | drp_rx_rate_gt_s[10] |
drp_rx_rate_gt_s[ 9] | drp_rx_rate_gt_s[ 8] |
drp_rx_rate_gt_s[ 7] | drp_rx_rate_gt_s[ 6] |
drp_rx_rate_gt_s[ 5] | drp_rx_rate_gt_s[ 4] |
drp_rx_rate_gt_s[ 3] | drp_rx_rate_gt_s[ 2] |
drp_rx_rate_gt_s[ 1] | drp_rx_rate_gt_s[ 0];
assign tx_ip_data = tx_data;
// clock buffers
BUFG i_bufg_rx_clk (
.I (rx_out_clk[0]),
.O (rx_clk));
BUFG i_bufg_tx_clk (
.I (tx_out_clk[0]),
.O (tx_clk));
// transceivers
assign qpll_clk = {{4{qpll_clk_1}}, {4{qpll_clk_0}}};
assign qpll_ref_clk = {{4{qpll_ref_clk_1}}, {4{qpll_ref_clk_0}}};
assign qpll_locked_s = {{4{qpll_locked_1_s}}, {4{qpll_locked_0_s}}};
ad_gt_common_1 #(
.DRP_ID (14),
.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
.QPLL_CFG (PCORE_QPLL_CFG),
.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
.QPLL_FBDIV (PCORE_QPLL_FBDIV))
i_gt_common_1 (
.rst (gt_pll_rst),
.ref_clk (ref_clk_q),
.qpll_clk (qpll_clk_0),
.qpll_ref_clk (qpll_ref_clk_0),
.qpll_locked (qpll_locked_0_s),
.drp_clk (drp_clk),
.drp_sel (drp_sel_s),
.drp_addr (drp_addr_s),
.drp_wr (drp_wr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_gt_s[14]),
.drp_ready (drp_ready_gt_s[14]),
.drp_lanesel (drp_lanesel_s),
.drp_rx_rate (drp_rx_rate_gt_s[14]));
ad_gt_common_1 #(
.DRP_ID (15),
.QPLL_REFCLK_DIV (PCORE_QPLL_REFCLK_DIV),
.QPLL_CFG (PCORE_QPLL_CFG),
.QPLL_FBDIV_RATIO (PCORE_QPLL_FBDIV_RATIO),
.QPLL_FBDIV (PCORE_QPLL_FBDIV))
i_gt_common_2 (
.rst (gt_pll_rst),
.ref_clk (ref_clk_q),
.qpll_clk (qpll_clk_1),
.qpll_ref_clk (qpll_ref_clk_1),
.qpll_locked (qpll_locked_1_s),
.drp_clk (drp_clk),
.drp_sel (drp_sel_s),
.drp_addr (drp_addr_s),
.drp_wr (drp_wr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_gt_s[15]),
.drp_ready (drp_ready_gt_s[15]),
.drp_lanesel (drp_lanesel_s),
.drp_rx_rate (drp_rx_rate_gt_s[15]));
genvar n;
generate
for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data[n*32+31:n*32]),
.rx_data (rx_data[n*32+31:n*32]));
ad_gt_channel_1 #(
.DRP_ID (n),
.CPLL_FBDIV (PCORE_CPLL_FBDIV),
.RX_OUT_DIV (PCORE_RX_OUT_DIV),
.TX_OUT_DIV (PCORE_TX_OUT_DIV),
.RX_CLK25_DIV (PCORE_RX_CLK25_DIV),
.TX_CLK25_DIV (PCORE_TX_CLK25_DIV),
.PMA_RSV (PCORE_PMA_RSV),
.RX_CDR_CFG (PCORE_RX_CDR_CFG))
i_gt_channel_1 (
.ref_clk (ref_clk_c),
.cpll_pd (up_cpll_pd_s),
.cpll_rst (gt_pll_rst),
.qpll_clk (qpll_clk[n]),
.qpll_ref_clk (qpll_ref_clk[n]),
.qpll_locked (qpll_locked_s[n]),
.rx_rst (gt_rx_rst),
.rx_p (rx_data_p[n]),
.rx_n (rx_data_n[n]),
.rx_sys_clk_sel (up_rx_sys_clk_sel_s),
.rx_out_clk_sel (up_rx_out_clk_sel_s),
.rx_out_clk (rx_out_clk[n]),
.rx_rst_done (rx_rst_done_s[n]),
.rx_pll_locked (rx_pll_locked_s[n]),
.rx_clk (rx_clk),
.rx_charisk (rx_gt_charisk[n*4+3:n*4]),
.rx_disperr (rx_gt_disperr[n*4+3:n*4]),
.rx_notintable (rx_gt_notintable[n*4+3:n*4]),
.rx_data (rx_gt_data[n*32+31:n*32]),
.rx_comma_align_enb (rx_ip_comma_align),
.tx_rst (gt_tx_rst),
.tx_p (tx_data_p[n]),
.tx_n (tx_data_n[n]),
.tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.tx_out_clk_sel (up_tx_out_clk_sel_s),
.tx_out_clk (tx_out_clk[n]),
.tx_rst_done (tx_rst_done_s[n]),
.tx_pll_locked (tx_pll_locked_s[n]),
.tx_clk (tx_clk),
.tx_charisk (tx_gt_charisk[n*4+3:n*4]),
.tx_data (tx_gt_data[n*32+31:n*32]),
.drp_clk (drp_clk),
.drp_sel (drp_sel_s),
.drp_addr (drp_addr_s),
.drp_wr (drp_wr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_gt_s[n]),
.drp_ready (drp_ready_gt_s[n]),
.drp_lanesel (drp_lanesel_s),
.drp_rx_rate (drp_rx_rate_gt_s[n]),
.rx_mon_trigger (rx_mon_trigger_s[n]),
.rx_mon_data (rx_mon_data_s[n*50+49:n*50]));
end
endgenerate
// eye scan
ad_gt_es #(.GTH_GTX_N(0)) i_gt_es (
.drp_rst (drp_rst),
.drp_clk (drp_clk),
.es_sel (es_sel_s),
.es_wr (es_wr_s),
.es_addr (es_addr_s),
.es_wdata (es_wdata_s),
.es_rdata (es_rdata_s),
.es_ready (es_ready_s),
.axi_rstn (axi_rstn),
.axi_clk (axi_clk),
.axi_awvalid (m_axi_awvalid),
.axi_awaddr (m_axi_awaddr),
.axi_awprot (m_axi_awprot),
.axi_awready (m_axi_awready),
.axi_wvalid (m_axi_wvalid),
.axi_wdata (m_axi_wdata),
.axi_wstrb (m_axi_wstrb),
.axi_wready (m_axi_wready),
.axi_bvalid (m_axi_bvalid),
.axi_bresp (m_axi_bresp),
.axi_bready (m_axi_bready),
.axi_arvalid (m_axi_arvalid),
.axi_araddr (m_axi_araddr),
.axi_arprot (m_axi_arprot),
.axi_arready (m_axi_arready),
.axi_rvalid (m_axi_rvalid),
.axi_rdata (m_axi_rdata),
.axi_rresp (m_axi_rresp),
.axi_rready (m_axi_rready),
.es_start (es_start_s),
.es_stop (es_stop_s),
.es_init (es_init_s),
.es_sdata0 (es_sdata0_s),
.es_sdata1 (es_sdata1_s),
.es_sdata2 (es_sdata2_s),
.es_sdata3 (es_sdata3_s),
.es_sdata4 (es_sdata4_s),
.es_qdata0 (es_qdata0_s),
.es_qdata1 (es_qdata1_s),
.es_qdata2 (es_qdata2_s),
.es_qdata3 (es_qdata3_s),
.es_qdata4 (es_qdata4_s),
.es_prescale (es_prescale_s),
.es_hoffset_min (es_hoffset_min_s),
.es_hoffset_max (es_hoffset_max_s),
.es_hoffset_step (es_hoffset_step_s),
.es_voffset_min (es_voffset_min_s),
.es_voffset_max (es_voffset_max_s),
.es_voffset_step (es_voffset_step_s),
.es_start_addr (es_start_addr_s),
.es_dmaerr (es_dmaerr_s),
.es_status (es_status_s),
.es_dbg_trigger (es_dbg_trigger),
.es_dbg_data (es_dbg_data));
// processor
up_gt #(.PCORE_ID(PCORE_ID)) i_up_gt (
.gt_pll_rst (gt_pll_rst),
.gt_rx_rst (gt_rx_rst),
.gt_tx_rst (gt_tx_rst),
.up_cpll_pd (up_cpll_pd_s),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_s),
.up_rx_out_clk_sel (up_rx_out_clk_sel_s),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_s),
.up_tx_out_clk_sel (up_tx_out_clk_sel_s),
.rx_clk (rx_clk),
.rx_rst (rx_rst),
.rx_ext_sysref (rx_ext_sysref),
.rx_sysref (rx_sysref),
.rx_ip_sync (rx_ip_sync),
.rx_sync (rx_sync),
.rx_rst_done (rx_rst_done_extn_s[7:0]),
.rx_pll_locked (rx_pll_locked_extn_s[7:0]),
.rx_error (1'd0),
.tx_clk (tx_clk),
.tx_rst (tx_rst),
.tx_ext_sysref (tx_ext_sysref),
.tx_sysref (tx_sysref),
.tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync),
.tx_rst_done (tx_rst_done_extn_s[7:0]),
.tx_pll_locked (tx_pll_locked_extn_s[7:0]),
.tx_error (1'd0),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ready (drp_ready_s),
.drp_lanesel (drp_lanesel_s),
.drp_rx_rate (drp_rx_rate_s),
.es_sel (es_sel_s),
.es_wr (es_wr_s),
.es_addr (es_addr_s),
.es_wdata (es_wdata_s),
.es_rdata (es_rdata_s),
.es_ready (es_ready_s),
.es_start (es_start_s),
.es_stop (es_stop_s),
.es_init (es_init_s),
.es_prescale (es_prescale_s),
.es_voffset_step (es_voffset_step_s),
.es_voffset_max (es_voffset_max_s),
.es_voffset_min (es_voffset_min_s),
.es_hoffset_max (es_hoffset_max_s),
.es_hoffset_min (es_hoffset_min_s),
.es_hoffset_step (es_hoffset_step_s),
.es_start_addr (es_start_addr_s),
.es_sdata0 (es_sdata0_s),
.es_sdata1 (es_sdata1_s),
.es_sdata2 (es_sdata2_s),
.es_sdata3 (es_sdata3_s),
.es_sdata4 (es_sdata4_s),
.es_qdata0 (es_qdata0_s),
.es_qdata1 (es_qdata1_s),
.es_qdata2 (es_qdata2_s),
.es_qdata3 (es_qdata3_s),
.es_qdata4 (es_qdata4_s),
.es_dmaerr (es_dmaerr_s),
.es_status (es_status_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// axi interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

23
library/axi_jesd_gt/axi_jesd_gt_ip.tcl Normal file
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@ -0,0 +1,23 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_jesd_gt
adi_ip_files axi_jesd_gt [list \
"$ad_hdl_dir/library/common/ad_gt_common_1.v" \
"$ad_hdl_dir/library/common/ad_gt_channel_1.v" \
"$ad_hdl_dir/library/common/ad_gt_es.v" \
"$ad_hdl_dir/library/common/ad_jesd_align.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_gt.v" \
"axi_jesd_gt.v" ]
adi_ip_properties axi_jesd_gt
ipx::save_core [ipx::current_core]

18
library/common/ad_gt_es.v
View File

@ -131,6 +131,8 @@ module ad_gt_es (
// state machine
parameter ES_FSM_IDLE = 6'h00;
parameter ES_FSM_STATUS = 6'h30;
parameter ES_FSM_INIT = 6'h31;
parameter ES_FSM_CTRLINIT_READ = 6'h01;
parameter ES_FSM_CTRLINIT_RRDY = 6'h02;
parameter ES_FSM_CTRLINIT_WRITE = 6'h03;
@ -451,15 +453,25 @@ module ad_gt_es (
end else begin
case (es_fsm)
ES_FSM_IDLE: begin // idle
if (es_start == 1'b0) begin
if (es_start == 1'b1) begin
es_fsm <= ES_FSM_STATUS;
end else begin
es_fsm <= ES_FSM_IDLE;
end else if (es_init == 1'b1) begin
end
end
ES_FSM_STATUS: begin // set status
es_fsm <= ES_FSM_INIT;
end
ES_FSM_INIT: begin // initialize
if (es_init == 1'b1) begin
es_fsm <= ES_FSM_CTRLINIT_READ;
end else begin
es_fsm <= ES_FSM_HOFFSET_READ;
end
end
ES_FSM_CTRLINIT_READ: begin // control read
es_fsm <= ES_FSM_CTRLINIT_RRDY;
end

99
library/common/altera/ad_jesd_align.v Normal file
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@ -0,0 +1,99 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_jesd_align (
// jesd interface
rx_clk,
rx_sof,
rx_ip_data,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [31:0] rx_ip_data;
// aligned data
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [31:0] rx_data = 'd0;
// dword may contain more than one frame per clock
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
if (rx_sof[3] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[ 7: 0];
rx_data[23:16] <= rx_ip_data[15: 8];
rx_data[15: 8] <= rx_ip_data[23:16];
rx_data[ 7: 0] <= rx_ip_data[31:24];
end else if (rx_sof[2] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[31:24];
rx_data[23:16] <= rx_ip_data_d[ 7: 0];
rx_data[15: 8] <= rx_ip_data_d[15: 8];
rx_data[ 7: 0] <= rx_ip_data_d[23:16];
end else if (rx_sof[1] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[23:16];
rx_data[23:16] <= rx_ip_data[31:24];
rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
end else if (rx_sof[0] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[15: 8];
rx_data[23:16] <= rx_ip_data[23:16];
rx_data[15: 8] <= rx_ip_data[31:24];
rx_data[ 7: 0] <= rx_ip_data_d[ 7: 0];
end else begin
rx_data[31:24] <= 8'd0;
rx_data[23:16] <= 8'd0;
rx_data[15: 8] <= 8'd0;
rx_data[ 7: 0] <= 8'd0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

68
library/common/altera/ad_rst.v Normal file
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@ -0,0 +1,68 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_rst (
// clock reset
preset,
clk,
rst);
// clock reset
input preset;
input clk;
output rst;
// simple reset gen
lpm_ff #(.LPM_WIDTH(1), .LPM_AVALUE(1'b1)) i_rst_reg (
.enable (1'b1),
.data (1'b0),
.aset (preset),
.clock (clk),
.q (rst));
endmodule
// ***************************************************************************
// ***************************************************************************

266
library/common/altera/ad_xcvr_rx_rst.v Normal file
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@ -0,0 +1,266 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_xcvr_rx_rst (
// clock, reset and pll locked
rx_clk,
rx_rstn,
rx_sw_rstn,
rx_pll_locked,
// xcvr status and reset
rx_cal_busy,
rx_cdr_locked,
rx_analog_reset,
rx_digital_reset,
rx_ready,
rx_rst_state);
// parameters
parameter NUM_OF_LANES = 4;
parameter RX_CAL_DONE_COUNT_WIDTH = 8;
parameter RX_CDR_LOCKED_COUNT_WIDTH = 8;
parameter RX_ANALOG_RESET_COUNT_WIDTH = 5;
parameter RX_DIGITAL_RESET_COUNT_WIDTH = 12;
localparam RX_RESET_FSM_INIT = 4'h0;
localparam RX_RESET_FSM_ARST0 = 4'h1;
localparam RX_RESET_FSM_ARST1 = 4'h2;
localparam RX_RESET_FSM_ARST2 = 4'h3;
localparam RX_RESET_FSM_ARST3 = 4'h4;
localparam RX_RESET_FSM_ARSTD = 4'h5;
localparam RX_RESET_FSM_DRST0 = 4'h6;
localparam RX_RESET_FSM_DRST1 = 4'h7;
localparam RX_RESET_FSM_DRST2 = 4'h8;
localparam RX_RESET_FSM_DRST3 = 4'h9;
localparam RX_RESET_FSM_DRSTD = 4'ha;
localparam RX_RESET_FSM_IDLE = 4'hb;
// clock, reset and pll locked
input rx_clk;
input rx_rstn;
input rx_sw_rstn;
input rx_pll_locked;
// xcvr status and reset
input [NUM_OF_LANES-1:0] rx_cal_busy;
input [NUM_OF_LANES-1:0] rx_cdr_locked;
output [NUM_OF_LANES-1:0] rx_analog_reset;
output [NUM_OF_LANES-1:0] rx_digital_reset;
output rx_ready;
output [ 3:0] rx_rst_state;
// internal registers
reg [ 2:0] rx_rst_req_m = 'd0;
reg rx_rst_req = 'd0;
reg [RX_CAL_DONE_COUNT_WIDTH:0] rx_cal_done_cnt = 'd0;
reg [RX_CDR_LOCKED_COUNT_WIDTH:0] rx_cdr_locked_cnt = 'd0;
reg [RX_ANALOG_RESET_COUNT_WIDTH:0] rx_analog_reset_cnt = 'd0;
reg [RX_DIGITAL_RESET_COUNT_WIDTH:0] rx_digital_reset_cnt = 'd0;
reg [ 3:0] rx_rst_state = 'd0;
reg [NUM_OF_LANES-1:0] rx_analog_reset = 'd0;
reg [NUM_OF_LANES-1:0] rx_digital_reset = 'd0;
reg rx_ready = 'd0;
// internal signals
wire rx_rst_req_s;
wire rx_cal_busy_s;
wire rx_cal_done_s;
wire rx_cal_done_valid_s;
wire rx_cdr_locked_s;
wire rx_cdr_locked_valid_s;
wire rx_analog_reset_s;
wire rx_analog_reset_valid_s;
wire rx_digital_reset_s;
wire rx_digital_reset_valid_s;
// reset request
assign rx_rst_req_s = ~(rx_rstn & rx_sw_rstn & rx_pll_locked);
always @(posedge rx_clk) begin
rx_rst_req_m <= {rx_rst_req_m[1:0], rx_rst_req_s};
rx_rst_req <= rx_rst_req_m[2];
end
// cal busy check width
assign rx_cal_busy_s = | rx_cal_busy;
assign rx_cal_done_s = ~rx_cal_busy_s;
assign rx_cal_done_valid_s = rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH];
always @(posedge rx_clk) begin
if (rx_cal_done_s == 1'd0) begin
rx_cal_done_cnt <= 'd0;
end else if (rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH] == 1'b0) begin
rx_cal_done_cnt <= rx_cal_done_cnt + 1'b1;
end
end
// cdr locked check width
assign rx_cdr_locked_s = | rx_cdr_locked;
assign rx_cdr_locked_valid_s = rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH];
always @(posedge rx_clk) begin
if (rx_cdr_locked_s == 1'd0) begin
rx_cdr_locked_cnt <= 'd0;
end else if (rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH] == 1'b0) begin
rx_cdr_locked_cnt <= rx_cdr_locked_cnt + 1'b1;
end
end
// analog reset width
assign rx_analog_reset_s = | rx_analog_reset;
assign rx_analog_reset_valid_s = rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH];
always @(posedge rx_clk) begin
if (rx_analog_reset_s == 1'd0) begin
rx_analog_reset_cnt <= 'd0;
end else if (rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH] == 1'b0) begin
rx_analog_reset_cnt <= rx_analog_reset_cnt + 1'b1;
end
end
// digital reset width
assign rx_digital_reset_s = | rx_digital_reset;
assign rx_digital_reset_valid_s = rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH];
always @(posedge rx_clk) begin
if (rx_digital_reset_s == 1'd0) begin
rx_digital_reset_cnt <= 'd0;
end else if (rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH] == 1'b0) begin
rx_digital_reset_cnt <= rx_digital_reset_cnt + 1'b1;
end
end
// state machine
always @(posedge rx_clk) begin
if (rx_rst_req == 1'b1) begin
rx_rst_state <= RX_RESET_FSM_INIT;
end else begin
case (rx_rst_state)
RX_RESET_FSM_INIT: begin
rx_rst_state <= RX_RESET_FSM_ARST0;
end
RX_RESET_FSM_ARST0: begin
if ((rx_cal_done_valid_s == 1'b1) && (rx_analog_reset_valid_s == 1'b1)) begin
rx_rst_state <= RX_RESET_FSM_ARST1;
end else begin
rx_rst_state <= RX_RESET_FSM_ARST0;
end
end
RX_RESET_FSM_ARST1: begin
rx_rst_state <= RX_RESET_FSM_ARST2;
end
RX_RESET_FSM_ARST2: begin
rx_rst_state <= RX_RESET_FSM_ARST3;
end
RX_RESET_FSM_ARST3: begin
rx_rst_state <= RX_RESET_FSM_ARSTD;
end
RX_RESET_FSM_ARSTD: begin
rx_rst_state <= RX_RESET_FSM_DRST0;
end
RX_RESET_FSM_DRST0: begin
if ((rx_cdr_locked_valid_s == 1'b1) && (rx_digital_reset_valid_s == 1'b1)) begin
rx_rst_state <= RX_RESET_FSM_DRST1;
end else begin
rx_rst_state <= RX_RESET_FSM_DRST0;
end
end
RX_RESET_FSM_DRST1: begin
rx_rst_state <= RX_RESET_FSM_DRST2;
end
RX_RESET_FSM_DRST2: begin
rx_rst_state <= RX_RESET_FSM_DRST3;
end
RX_RESET_FSM_DRST3: begin
rx_rst_state <= RX_RESET_FSM_DRSTD;
end
RX_RESET_FSM_DRSTD: begin
rx_rst_state <= RX_RESET_FSM_IDLE;
end
RX_RESET_FSM_IDLE: begin
rx_rst_state <= RX_RESET_FSM_IDLE;
end
default: begin
rx_rst_state <= RX_RESET_FSM_INIT;
end
endcase
end
end
// output signals
always @(posedge rx_clk) begin
if (rx_rst_state == RX_RESET_FSM_INIT) begin
rx_analog_reset <= {{NUM_OF_LANES{1'b1}}};
end else if (rx_rst_state == RX_RESET_FSM_ARSTD) begin
rx_analog_reset <= {{NUM_OF_LANES{1'b0}}};
end
if (rx_rst_state == RX_RESET_FSM_INIT) begin
rx_digital_reset <= {{NUM_OF_LANES{1'b1}}};
end else if (rx_rst_state == RX_RESET_FSM_DRSTD) begin
rx_digital_reset <= {{NUM_OF_LANES{1'b0}}};
end
if (rx_rst_state == RX_RESET_FSM_IDLE) begin
rx_ready <= 1'b1;
end else begin
rx_ready <= 1'b0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

46
library/common/up_gt.v
View File

@ -303,12 +303,10 @@ module up_gt (
reg es_ready = 'd0;
reg [15:0] drp_rdata_int = 'd0;
reg drp_ready_int = 'd0;
reg es_start_m1 = 'd0;
reg es_start_m2 = 'd0;
reg es_start_m3 = 'd0;
reg es_stop_m1 = 'd0;
reg es_stop_m2 = 'd0;
reg es_stop_m3 = 'd0;
reg es_start_d1 = 'd0;
reg es_start_d2 = 'd0;
reg es_stop_d1 = 'd0;
reg es_stop_d2 = 'd0;
reg es_start = 'd0;
reg es_stop = 'd0;
@ -335,6 +333,8 @@ module up_gt (
wire [15:0] up_drp_rdata_s;
wire up_drp_status_s;
wire [ 7:0] up_drp_rx_rate_s;
wire es_start_s;
wire es_stop_s;
wire up_es_dmaerr_s;
wire up_es_status_s;
@ -711,32 +711,30 @@ module up_gt (
always @(posedge drp_clk) begin
if (drp_rst == 1'b1) begin
es_start_m1 <= 'd0;
es_start_m2 <= 'd0;
es_start_m3 <= 'd0;
es_stop_m1 <= 'd0;
es_stop_m2 <= 'd0;
es_stop_m3 <= 'd0;
es_start_d1 <= 'd0;
es_start_d2 <= 'd0;
es_stop_d1 <= 'd0;
es_stop_d2 <= 'd0;
es_start <= 'd0;
es_stop <= 'd0;
end else begin
es_start_m1 <= up_es_start;
es_start_m2 <= es_start_m1;
es_start_m3 <= es_start_m2;
es_stop_m1 <= up_es_stop;
es_stop_m2 <= es_stop_m1;
es_stop_m3 <= es_stop_m2;
es_start <= es_start_m2 & ~es_start_m3;
es_stop <= es_stop_m2 & ~es_stop_m3;
es_start_d1 <= es_start_s;
es_start_d2 <= es_start_d1;
es_stop_d1 <= es_stop_s;
es_stop_d2 <= es_stop_d1;
es_start <= es_start_d1 & ~es_start_d2;
es_stop <= es_stop_d1 & ~es_stop_d2;
end
end
// es control & status
up_xfer_cntrl #(.DATA_WIDTH(258)) i_es_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(260)) i_es_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_es_init,
.up_data_cntrl ({ up_es_start,
up_es_stop,
up_es_init,
up_es_prescale,
up_es_voffset_step,
up_es_voffset_max,
@ -757,7 +755,9 @@ module up_gt (
up_es_qdata4}),
.d_rst (drp_rst),
.d_clk (drp_clk),
.d_data_cntrl ({ es_init,
.d_data_cntrl ({ es_start_s,
es_stop_s,
es_init,
es_prescale,
es_voffset_step,
es_voffset_max,

219
projects/ad9467_fmc/common/ad9467_bd.tcl Normal file
View File

@ -0,0 +1,219 @@
# ad9467
set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
set adc_data_or_p [create_bd_port -dir I adc_data_or_p]
set adc_data_or_n [create_bd_port -dir I adc_data_or_n]
set adc_data_in_n [create_bd_port -dir I -from 7 -to 0 adc_data_in_n]
set adc_data_in_p [create_bd_port -dir I -from 7 -to 0 adc_data_in_p]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 1 -to 0 spi_csn_o]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
# adc peripheral
set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467]
set axi_ad9467_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9467_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma
if {$sys_zynq == 1} {
set axi_ad9467_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9467_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9467_dma_interconnect
}
# spi
if {$sys_zynq == 0} {
set axi_ad9467_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9467_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9467_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9467_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9467_spi
} else {
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
}
# additions to default configuration
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect
} else {
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
}
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc
set_property -dict [list CONFIG.NUM_SI {9}] $axi_mem_interconnect
}
# clock for ila
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
set_property LEFT 31 [get_bd_ports GPIO_I]
set_property LEFT 31 [get_bd_ports GPIO_O]
set_property LEFT 31 [get_bd_ports GPIO_T]
set sys_ila_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
} else {
set ila_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 ila_clkgen]
set_property -dict [list CONFIG.PRIM_IN_FREQ {200}] $ila_clkgen
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125}] $ila_clkgen
set_property -dict [list CONFIG.USE_LOCKED {false}] $ila_clkgen
set_property -dict [list CONFIG.USE_RESET {false}] $ila_clkgen
connect_bd_net -net sys_200m_clk [get_bd_pins ila_clkgen/clk_in1]
set sys_ila_clk_source [get_bd_pins ila_clkgen/clk_out1]
connect_bd_net -net sys_ila_clk $sys_ila_clk_source
}
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9467_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9467_spi/ss_o]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9467_spi/sck_i]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9467_spi/sck_o]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9467_spi/io0_i]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9467_spi/io0_o]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9467_spi/io1_i]
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
} else {
set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat]
set_property -dict [list CONFIG.NUM_PORTS {2}] $sys_spi_csn_concat
connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
}
# connections (ad9467)
connect_bd_net -net axi_ad9467_adc_clk_in_n [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9467/adc_clk_in_p]
connect_bd_net -net axi_ad9467_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9467/adc_clk_in_n]
connect_bd_net -net axi_ad9467_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9467/adc_data_in_n]
connect_bd_net -net axi_ad9467_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9467/adc_data_in_p]
connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_data_or_p]
connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_data_or_n]
set adc_250m_clk_source [get_bd_pins axi_ad9467/adc_clk]
connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467_dma/fifo_wr_clk] $adc_250m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467/delay_clk]
connect_bd_net -net axi_ad9467_dma_dwr [get_bd_pins axi_ad9467/adc_dwr] [get_bd_pins axi_ad9467_dma/fifo_wr_en]
connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_ddata] [get_bd_pins axi_ad9467_dma/fifo_wr_din]
connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_doverflow] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2]
# interconnect (cpu)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins $sys_100m_clk_source]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] [get_bd_pins $sys_100m_resetn_source]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] [get_bd_pins $sys_100m_resetn_source]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma/s_axi_aresetn]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9467_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9467/s_axi]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9467_spi/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_spi/s_axi_aresetn]
connect_bd_net -net axi_ad9467_spi_irq [get_bd_pins axi_ad9467_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
}
# interconnect (mem/adc)
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9467_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9467_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9467_dma_interconnect_s0 [get_bd_intf_pins axi_ad9467_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9467_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9467_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9467_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma_interconnect/S00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma_interconnect/ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467_dma_interconnect/M00_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
}
# ila (with fifo to prevent timing failure)
set ila_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 ila_fifo]
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_fifo
set_property -dict [list CONFIG.Input_Data_Width {16}] $ila_fifo
set_property -dict [list CONFIG.Input_Depth {128}] $ila_fifo
set_property -dict [list CONFIG.Output_Data_Width {32}] $ila_fifo
set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_fifo
set_property -dict [list CONFIG.Reset_Pin {false}] $ila_fifo
set ila_ad9467_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ad9467_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ad9467_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {32}] $ila_ad9467_mon
set ila_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ila_constant_1]
connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins ila_fifo/din] [get_bd_pins axi_ad9467/adc_ddata]
connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467/adc_clk] [get_bd_pins ila_fifo/wr_clk]
connect_bd_net -net sys_ila_clk [get_bd_pins ila_fifo/rd_clk] [get_bd_pins ila_ad9467_mon/clk]
connect_bd_net -net xlconstant_0_const [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_pins ila_constant_1/const]
connect_bd_net -net ila_fifo_dout [get_bd_pins ila_fifo/dout] [get_bd_pins ila_ad9467_mon/probe0]
# address mapping
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467/s_axi/axi_lite] SEG_data_ad9467_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467_dma/s_axi/axi_lite] SEG_data_ad9467_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9467_spi/axi_lite/Reg] SEG_data_ad9467_spi
}
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9467_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
}

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projects/ad9467_fmc/common/ad9467_spi.v Normal file
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@ -0,0 +1,107 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9467_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule

3
projects/ad9467_fmc/kc705/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source ../common/ad9467_bd.tcl

37
projects/ad9467_fmc/kc705/system_constr.xdc Normal file
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# ad9467
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
## spi
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## FMC_LPC_LA32_P
# clocks
create_clock -name adc_clk -period 4.00 [get_ports adc_clk_in_p]
set_clock_groups -asynchronous -group {adc_clk}

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# load script
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
set project_name ad9467_fmc_kc705
adi_project_create $project_name
adi_project_files $project_name [list "../common/ad9467_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc"]
adi_project_run $project_name

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_1_n,
ddr3_1_p,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
mdio_mdc,
mdio_mdio_io,
mii_rst_n,
mii_col,
mii_crs,
mii_rx_clk,
mii_rx_er,
mii_rx_dv,
mii_rxd,
mii_tx_clk,
mii_tx_en,
mii_txd,
fan_pwm,
gpio_lcd,
gpio_led,
gpio_sw,
iic_rstn,
iic_scl,
iic_sda,
hdmi_out_clk,
hdmi_hsync,
hdmi_vsync,
hdmi_data_e,
hdmi_data,
spdif,
adc_clk_in_n,
adc_clk_in_p,
adc_data_in_n,
adc_data_in_p,
adc_data_or_n,
adc_data_or_p,
spi_clk,
spi_csn_adc,
spi_csn_clk,
spi_sdio
);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [ 2:0] ddr3_1_n;
output [ 1:0] ddr3_1_p;
output ddr3_reset_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output mdio_mdc;
inout mdio_mdio_io;
output mii_rst_n;
input mii_col;
input mii_crs;
input mii_rx_clk;
input mii_rx_er;
input mii_rx_dv;
input [ 3:0] mii_rxd;
input mii_tx_clk;
output mii_tx_en;
output [ 3:0] mii_txd;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [ 7:0] gpio_led;
inout [ 8:0] gpio_sw;
output iic_rstn;
inout iic_scl;
inout iic_sda;
output hdmi_out_clk;
output hdmi_hsync;
output hdmi_vsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
input adc_clk_in_n;
input adc_clk_in_p;
input [ 7:0] adc_data_in_n;
input [ 7:0] adc_data_in_p;
input adc_data_or_n;
input adc_data_or_p;
output spi_clk;
output spi_csn_adc;
output spi_csn_clk;
inout spi_sdio;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9467_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
system_wrapper i_system_wrapper (
.ddr3_1_n (ddr3_1_n),
.ddr3_1_p (ddr3_1_p),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.fan_pwm (fan_pwm),
.gpio_lcd_tri_io (gpio_lcd),
.gpio_led_tri_io (gpio_led),
.gpio_sw_tri_io (gpio_sw),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.iic_rstn (iic_rstn),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio_io),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.unc_int0 (1'b0),
.unc_int3 (1'b0),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad9467_bd.tcl

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# ad9467
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC_LPC_LA07_N
## spi
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## FMC_LPC_LA32_P
# clocks
create_clock -name adc_clk -period 4.00 [get_ports adc_clk_in_p]
set_clock_groups -asynchronous -group {adc_clk}

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# load script
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
set project_name ad9467_fmc_zed
adi_project_create $project_name
adi_project_files $project_name [list "../common/ad9467_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
adi_project_run $project_name

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
adc_clk_in_n,
adc_clk_in_p,
adc_data_in_n,
adc_data_in_p,
adc_data_or_n,
adc_data_or_p,
spi_clk,
spi_csn_adc,
spi_csn_clk,
spi_sdio
);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
input adc_clk_in_n;
input adc_clk_in_p;
input [ 7:0] adc_data_in_n;
input [ 7:0] adc_data_in_p;
input adc_data_or_n;
input adc_data_or_p;
output spi_clk;
output spi_csn_adc;
output spi_csn_clk;
inout spi_sdio;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
genvar n;
generate
for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0]));
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1]));
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9467_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
system_wrapper i_system_wrapper (
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.adc_clk_in_n(adc_clk_in_n),
.adc_clk_in_p(adc_clk_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_or_n(adc_data_or_n),
.adc_data_or_p(adc_data_or_p),
.spi_clk_i(1'b0),
.spi_clk_o(spi_clk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_sdi_i(spi_miso),
.spi_sdo_i(1'b0),
.spi_sdo_o(spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

787
projects/common/a5gt/a5gt_system_assign.tcl Executable file
View File

@ -0,0 +1,787 @@
# clocks and resets
set_location_assignment PIN_C34 -to sys_clk
set_location_assignment PIN_D34 -to "sys_clk(n)"
set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sys_clk -disable
set_location_assignment PIN_L6 -to sys_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sys_resetn
# ddr3
set_location_assignment PIN_B31 -to ddr3_a[0]
set_location_assignment PIN_A30 -to ddr3_a[1]
set_location_assignment PIN_A31 -to ddr3_a[2]
set_location_assignment PIN_A32 -to ddr3_a[3]
set_location_assignment PIN_A33 -to ddr3_a[4]
set_location_assignment PIN_B33 -to ddr3_a[5]
set_location_assignment PIN_H31 -to ddr3_a[6]
set_location_assignment PIN_J31 -to ddr3_a[7]
set_location_assignment PIN_C31 -to ddr3_a[8]
set_location_assignment PIN_D31 -to ddr3_a[9]
set_location_assignment PIN_C32 -to ddr3_a[10]
set_location_assignment PIN_D32 -to ddr3_a[11]
set_location_assignment PIN_N31 -to ddr3_a[12]
set_location_assignment PIN_P31 -to ddr3_a[13]
set_location_assignment PIN_M32 -to ddr3_ba[0]
set_location_assignment PIN_N32 -to ddr3_ba[1]
set_location_assignment PIN_J34 -to ddr3_ba[2]
set_location_assignment PIN_B30 -to ddr3_clk_p
set_location_assignment PIN_C30 -to ddr3_clk_n
set_location_assignment PIN_E31 -to ddr3_cke
set_location_assignment PIN_L34 -to ddr3_cs_n
set_location_assignment PIN_K34 -to ddr3_ras_n
set_location_assignment PIN_L33 -to ddr3_cas_n
set_location_assignment PIN_M33 -to ddr3_we_n
set_location_assignment PIN_G30 -to ddr3_reset_n
set_location_assignment PIN_L31 -to ddr3_odt
set_location_assignment PIN_F33 -to ddr3_rzq
set_location_assignment PIN_N30 -to ddr3_dqs_p[0]
set_location_assignment PIN_P30 -to ddr3_dqs_n[0]
set_location_assignment PIN_R29 -to ddr3_dqs_p[1]
set_location_assignment PIN_T29 -to ddr3_dqs_n[1]
set_location_assignment PIN_J30 -to ddr3_dm[0]
set_location_assignment PIN_J29 -to ddr3_dm[1]
set_location_assignment PIN_B28 -to ddr3_dq[0]
set_location_assignment PIN_C29 -to ddr3_dq[1]
set_location_assignment PIN_R30 -to ddr3_dq[2]
set_location_assignment PIN_A29 -to ddr3_dq[3]
set_location_assignment PIN_A28 -to ddr3_dq[4]
set_location_assignment PIN_L30 -to ddr3_dq[5]
set_location_assignment PIN_D30 -to ddr3_dq[6]
set_location_assignment PIN_D29 -to ddr3_dq[7]
set_location_assignment PIN_L28 -to ddr3_dq[8]
set_location_assignment PIN_M28 -to ddr3_dq[9]
set_location_assignment PIN_H28 -to ddr3_dq[10]
set_location_assignment PIN_C28 -to ddr3_dq[11]
set_location_assignment PIN_D28 -to ddr3_dq[12]
set_location_assignment PIN_F28 -to ddr3_dq[13]
set_location_assignment PIN_M29 -to ddr3_dq[14]
set_location_assignment PIN_N29 -to ddr3_dq[15]
set_location_assignment PIN_R28 -to ddr3_dqs_p[2]
set_location_assignment PIN_T28 -to ddr3_dqs_n[2]
set_location_assignment PIN_M26 -to ddr3_dqs_p[3]
set_location_assignment PIN_N26 -to ddr3_dqs_n[3]
set_location_assignment PIN_K27 -to ddr3_dm[2]
set_location_assignment PIN_J26 -to ddr3_dm[3]
set_location_assignment PIN_P27 -to ddr3_dq[16]
set_location_assignment PIN_R27 -to ddr3_dq[17]
set_location_assignment PIN_H27 -to ddr3_dq[18]
set_location_assignment PIN_B27 -to ddr3_dq[19]
set_location_assignment PIN_C27 -to ddr3_dq[20]
set_location_assignment PIN_E27 -to ddr3_dq[21]
set_location_assignment PIN_M27 -to ddr3_dq[22]
set_location_assignment PIN_N27 -to ddr3_dq[23]
set_location_assignment PIN_C26 -to ddr3_dq[24]
set_location_assignment PIN_D26 -to ddr3_dq[25]
set_location_assignment PIN_K25 -to ddr3_dq[26]
set_location_assignment PIN_R26 -to ddr3_dq[27]
set_location_assignment PIN_T27 -to ddr3_dq[28]
set_location_assignment PIN_A26 -to ddr3_dq[29]
set_location_assignment PIN_F26 -to ddr3_dq[30]
set_location_assignment PIN_G26 -to ddr3_dq[31]
set_location_assignment PIN_A20 -to ddr3_dqs_p[4]
set_location_assignment PIN_B21 -to ddr3_dqs_n[4]
set_location_assignment PIN_C23 -to ddr3_dqs_p[5]
set_location_assignment PIN_D23 -to ddr3_dqs_n[5]
set_location_assignment PIN_M21 -to ddr3_dm[4]
set_location_assignment PIN_B22 -to ddr3_dm[5]
set_location_assignment PIN_D20 -to ddr3_dq[32]
set_location_assignment PIN_H21 -to ddr3_dq[33]
set_location_assignment PIN_D21 -to ddr3_dq[34]
set_location_assignment PIN_J21 -to ddr3_dq[35]
set_location_assignment PIN_A21 -to ddr3_dq[36]
set_location_assignment PIN_G21 -to ddr3_dq[37]
set_location_assignment PIN_A22 -to ddr3_dq[38]
set_location_assignment PIN_C20 -to ddr3_dq[39]
set_location_assignment PIN_A23 -to ddr3_dq[40]
set_location_assignment PIN_E22 -to ddr3_dq[41]
set_location_assignment PIN_L22 -to ddr3_dq[42]
set_location_assignment PIN_C22 -to ddr3_dq[43]
set_location_assignment PIN_N22 -to ddr3_dq[44]
set_location_assignment PIN_F22 -to ddr3_dq[45]
set_location_assignment PIN_P22 -to ddr3_dq[46]
set_location_assignment PIN_J22 -to ddr3_dq[47]
set_location_assignment PIN_D24 -to ddr3_dqs_p[6]
set_location_assignment PIN_E24 -to ddr3_dqs_n[6]
set_location_assignment PIN_A25 -to ddr3_dqs_p[7]
set_location_assignment PIN_B25 -to ddr3_dqs_n[7]
set_location_assignment PIN_J23 -to ddr3_dm[6]
set_location_assignment PIN_D25 -to ddr3_dm[7]
set_location_assignment PIN_C24 -to ddr3_dq[48]
set_location_assignment PIN_M23 -to ddr3_dq[49]
set_location_assignment PIN_B24 -to ddr3_dq[50]
set_location_assignment PIN_R23 -to ddr3_dq[51]
set_location_assignment PIN_G24 -to ddr3_dq[52]
set_location_assignment PIN_G23 -to ddr3_dq[53]
set_location_assignment PIN_F24 -to ddr3_dq[54]
set_location_assignment PIN_F23 -to ddr3_dq[55]
set_location_assignment PIN_R24 -to ddr3_dq[56]
set_location_assignment PIN_G25 -to ddr3_dq[57]
set_location_assignment PIN_T26 -to ddr3_dq[58]
set_location_assignment PIN_E25 -to ddr3_dq[59]
set_location_assignment PIN_N24 -to ddr3_dq[60]
set_location_assignment PIN_K24 -to ddr3_dq[61]
set_location_assignment PIN_T25 -to ddr3_dq[62]
set_location_assignment PIN_P24 -to ddr3_dq[63]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_p
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_reset_n
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_rzq
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[47]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[63]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dm[0]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dm[1]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[0]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[1]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[2]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[3]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[4]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[5]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[6]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[7]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[8]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[9]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[10]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[11]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[12]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[13]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[14]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[15]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dm[2]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dm[3]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[16]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[17]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[18]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[19]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[20]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[21]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[22]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[23]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[24]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[25]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[26]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[27]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[28]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[29]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[30]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_p
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_n
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_p
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cke
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cs_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ras_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cas_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_we_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_reset_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_odt
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[14]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[15]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[16]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[17]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[18]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[19]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[20]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[21]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[22]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[23]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[24]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[25]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[26]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[27]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[28]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[29]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[30]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[31]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[32]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[33]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[34]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[35]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[36]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[37]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[38]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[39]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[40]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[41]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[42]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[43]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[44]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[45]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[46]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[47]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[48]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[49]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[50]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[51]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[52]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[53]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[54]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[55]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[56]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[57]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[58]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[59]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[60]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[61]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[62]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[63]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[16]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[17]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[18]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[19]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[20]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[21]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[22]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[23]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[24]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[25]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[26]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[27]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[28]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[29]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31]
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_fmcjesdadc1|sys_ddr3_cntrl
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_addr_cmd_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_avl_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_config_clk
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_afi_clk
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_fmcjesdadc1|sys_ddr3_cntrl|pll0|pll_hr_clk
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[5].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[6].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uio_pads|dq_ddio[7].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[5]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[6]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[7]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[5]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[6]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|uread_datapath|reset_n_fifo_write_side[7]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_mem_stable_n
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|p0|umemphy|ureset|phy_reset_n
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_fmcjesdadc1|sys_ddr3_cntrl|s0|sequencer_rw_mgr_inst|rw_mgr_inst|rw_mgr_core_inst|rw_soft_reset_n
# ethernet interface
set_location_assignment PIN_M14 -to eth_rx_clk
set_location_assignment PIN_N14 -to eth_rx_data[0]
set_location_assignment PIN_N15 -to eth_rx_data[1]
set_location_assignment PIN_P15 -to eth_rx_data[2]
set_location_assignment PIN_B9 -to eth_rx_data[3]
set_location_assignment PIN_C9 -to eth_rx_cntrl
set_location_assignment PIN_K18 -to eth_tx_clk_out
set_location_assignment PIN_L18 -to eth_tx_data[0]
set_location_assignment PIN_R11 -to eth_tx_data[1]
set_location_assignment PIN_T11 -to eth_tx_data[2]
set_location_assignment PIN_H9 -to eth_tx_data[3]
set_location_assignment PIN_J9 -to eth_tx_cntrl
set_location_assignment PIN_F7 -to eth_mdc
set_location_assignment PIN_G7 -to eth_mdio_i
set_location_assignment PIN_F9 -to eth_mdio_o
set_location_assignment PIN_G9 -to eth_mdio_t
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_data[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_rx_cntrl[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_clk_out[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_data[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_tx_cntrl
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t
# leds
set_location_assignment PIN_M19 -to led_grn[0]
set_location_assignment PIN_L19 -to led_grn[1]
set_location_assignment PIN_K19 -to led_grn[2]
set_location_assignment PIN_J19 -to led_grn[3]
set_location_assignment PIN_K20 -to led_grn[4]
set_location_assignment PIN_J20 -to led_grn[5]
set_location_assignment PIN_T20 -to led_grn[6]
set_location_assignment PIN_R20 -to led_grn[7]
set_location_assignment PIN_N20 -to led_red[0]
set_location_assignment PIN_C15 -to led_red[1]
set_location_assignment PIN_AL28 -to led_red[2]
set_location_assignment PIN_F11 -to led_red[3]
set_location_assignment PIN_AJ31 -to led_red[4]
set_location_assignment PIN_AN34 -to led_red[5]
set_location_assignment PIN_AJ34 -to led_red[6]
set_location_assignment PIN_AK33 -to led_red[7]
set_location_assignment PIN_D6 -to push_buttons[0]
set_location_assignment PIN_C6 -to push_buttons[1]
set_location_assignment PIN_K7 -to push_buttons[2]
set_location_assignment PIN_C8 -to dip_switches[0]
set_location_assignment PIN_D8 -to dip_switches[1]
set_location_assignment PIN_E7 -to dip_switches[2]
set_location_assignment PIN_E6 -to dip_switches[3]
set_location_assignment PIN_G8 -to dip_switches[4]
set_location_assignment PIN_F8 -to dip_switches[5]
set_location_assignment PIN_D15 -to dip_switches[6]
set_location_assignment PIN_G11 -to dip_switches[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_grn[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to led_red[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to push_buttons[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[7]

1
projects/common/kc705/kc705_system_bd.tcl
View File

@ -118,6 +118,7 @@ set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
# instance: default peripherals

202
projects/common/zc706/zc706_system_mig.prj Normal file
View File

@ -0,0 +1,202 @@
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>system_axi_ddr_cntrl_0</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7z045-ffg900/-2</TargetFPGA>
<Version>2.0</Version>
<SystemClock>Differential</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>1</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
<TimePeriod>1250</TimePeriod>
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>64</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<C0_MEM_SIZE>1073741824</C0_MEM_SIZE>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E10" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B7" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H12" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A10" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B9" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E11" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A9" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D11" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B6" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F9" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E8" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B10" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J8" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H7" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A7" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E7" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="F10" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G10" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D10" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J11" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="L12" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="G14" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C16" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C11" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L1" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H6" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H3" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G1" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H2" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G5" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G4" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E2" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E3" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D4" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E5" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L2" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F4" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F3" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D1" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D3" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A2" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B2" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B4" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B5" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A3" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B1" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K5" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C1" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C4" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K10" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L9" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J9" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K11" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L10" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J10" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L7" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J4" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F13" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G15" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K1" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E16" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C17" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D14" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B17" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B12" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C12" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A12" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A14" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L3" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A13" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B11" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J5" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K6" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G6" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H4" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K2" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H1" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="D5" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A4" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K8" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F12" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E17" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A15" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K3" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J1" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E6" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A5" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="L8" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F17" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B15" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="G7" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H11" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="G17" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="H9/G9(CC_P/N)" Bank="34" name="sys_clk_p/n" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

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projects/fmcjesdadc1/a5gt/system_bd.qsys Executable file
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projects/fmcjesdadc1/a5gt/system_constr.sdc Executable file
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create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m
set_false_path -from $clk_100m -to $clk_rxlink
set_false_path -from $clk_166m -to $clk_100m
set_false_path -from $clk_166m -to $clk_rxlink
set_false_path -from $clk_rxlink -to $clk_100m
set_false_path -from $clk_rxlink -to $clk_166m
set_false_path -from $clk_125m -to $clk_25m
set_false_path -from $clk_125m -to $clk_2m5
set_false_path -from $clk_25m -to $clk_125m
set_false_path -from $clk_25m -to $clk_2m5
set_false_path -from $clk_2m5 -to $clk_125m
set_false_path -from $clk_2m5 -to $clk_25m

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projects/fmcjesdadc1/a5gt/system_project.tcl Executable file
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load_package flow
source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
set_global_assignment -name FAMILY "Arria V"
set_global_assignment -name DEVICE 5AGTFD7K3F40I3
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
# reference clock
set_location_assignment PIN_AB9 -to ref_clk
set_location_assignment PIN_AB8 -to "ref_clk(n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk
set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk
# lane data
set_location_assignment PIN_AE1 -to rx_data[0]
set_location_assignment PIN_AE2 -to "rx_data[0](n)"
set_location_assignment PIN_AA1 -to rx_data[1]
set_location_assignment PIN_AA2 -to "rx_data[1](n)"
set_location_assignment PIN_U1 -to rx_data[2]
set_location_assignment PIN_U2 -to "rx_data[2](n)"
set_location_assignment PIN_R1 -to rx_data[3]
set_location_assignment PIN_R2 -to "rx_data[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2]
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3]
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0]
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1]
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2]
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3]
# jesd signals
set_location_assignment PIN_AD25 -to rx_sync
set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sync
set_location_assignment PIN_AC24 -to rx_sysref
set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sysref
# spi
set_location_assignment PIN_AG27 -to spi_csn
set_location_assignment PIN_AH27 -to spi_clk
set_location_assignment PIN_AD24 -to spi_sdio
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
# globals
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
execute_flow -compile

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projects/fmcjesdadc1/a5gt/system_timing.tcl Executable file
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report_timing -detail path_only -npaths 20 -file timing_impl.log

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projects/fmcjesdadc1/a5gt/system_top.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_a,
ddr3_ba,
ddr3_clk_p,
ddr3_clk_n,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_dq,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_odt,
ddr3_rzq,
// ethernet
eth_rx_clk,
eth_rx_data,
eth_rx_cntrl,
eth_tx_clk_out,
eth_tx_data,
eth_tx_cntrl,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
// board gpio
led_grn,
led_red,
push_buttons,
dip_switches,
// lane interface
ref_clk,
rx_data,
rx_sync,
rx_sysref,
// spi
spi_csn,
spi_clk,
spi_sdio);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_clk_p;
output ddr3_clk_n;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
output ddr3_odt;
input ddr3_rzq;
// ethernet
input eth_rx_clk;
input [ 3:0] eth_rx_data;
input eth_rx_cntrl;
output eth_tx_clk_out;
output [ 3:0] eth_tx_data;
output eth_tx_cntrl;
output eth_mdc;
input eth_mdio_i;
output eth_mdio_o;
output eth_mdio_t;
// board gpio
output [ 7:0] led_grn;
output [ 7:0] led_red;
input [ 2:0] push_buttons;
input [ 7:0] dip_switches;
// lane interface
input ref_clk;
input [ 3:0] rx_data;
output rx_sync;
output rx_sysref;
// spi
output spi_csn;
output spi_clk;
inout spi_sdio;
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
// internal clocks and resets
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
wire adc0_clk;
wire adc1_clk;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire spi_csn_s;
wire spi_clk_s;
wire spi_mosi_s;
wire spi_miso_s;
wire [ 63:0] adc0_ddata_s;
wire adc0_dsync_s;
wire adc0_dovf_s;
wire adc0_dwr_s;
wire adc0_mon_valid_s;
wire [ 55:0] adc0_mon_data_s;
wire [ 63:0] adc1_ddata_s;
wire adc1_dsync_s;
wire adc1_dovf_s;
wire adc1_dwr_s;
wire adc1_mon_valid_s;
wire [ 55:0] adc1_mon_data_s;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
wire rx_sw_rstn_s;
wire rx_sysref_s;
wire rx_err_s;
wire rx_ready_s;
wire [ 3:0] rx_rst_state_s;
wire rx_lane_aligned_s;
wire [ 3:0] rx_analog_reset_s;
wire [ 3:0] rx_digital_reset_s;
wire [ 3:0] rx_cdr_locked_s;
wire [ 3:0] rx_cal_busy_s;
wire rx_pll_locked_s;
wire [ 15:0] rx_xcvr_status_s;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (eth_tx_reset_s),
.outclock (eth_tx_clk),
.dataout (eth_tx_clk_out));
assign eth_tx_reset_s = ~sys_pll_locked_s;
always @(posedge rx_clk) begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (114),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data (rx_data_s[n*32+31:n*32]));
end
endgenerate
assign rx_xcvr_status_s[15:15] = 1'd0;
assign rx_xcvr_status_s[14:14] = rx_sync;
assign rx_xcvr_status_s[13:13] = rx_ready_s;
assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
.rx_sw_rstn (rx_sw_rstn_s),
.rx_pll_locked (rx_pll_locked_s),
.rx_cal_busy (rx_cal_busy_s),
.rx_cdr_locked (rx_cdr_locked_s),
.rx_analog_reset (rx_analog_reset_s),
.rx_digital_reset (rx_digital_reset_s),
.rx_ready (rx_ready_s),
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.sys_clk (sys_clk),
.spi4_csn (spi_csn_s),
.spi4_clk (spi_clk_s),
.spi4_mosi (spi_mosi_s),
.spi4_miso (spi_miso_s),
.spi3_csn (spi_csn),
.spi3_clk (spi_clk),
.spi3_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_pll_locked_export (sys_pll_locked_s),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.sys_ddr3_phy_mem_cke (ddr3_cke),
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.sys_ddr3_phy_mem_dm (ddr3_dm),
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.sys_ddr3_phy_mem_dq (ddr3_dq),
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
.sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
.sys_spi_MISO (spi_miso_s),
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk_s),
.sys_spi_SS_n (spi_csn_s),
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_0_adc_clock_clk (adc0_clk),
.axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s),
.axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s),
.axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_dunf (1'b0),
.axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s),
.axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s),
.axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s),
.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
.axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s),
.axi_dmac_0_fifo_wr_if_data (adc0_ddata_s),
.axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.axi_ad9250_1_adc_clock_clk (adc1_clk),
.axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s),
.axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s),
.axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_dunf (1'b0),
.axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s),
.axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s),
.axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s),
.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
.axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s),
.axi_dmac_1_fifo_wr_if_data (adc1_ddata_s),
.axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sysref_export (rx_sysref),
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sync_n_export (rx_sync),
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_export (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s));
endmodule
// ***************************************************************************
// ***************************************************************************

150
projects/fmcjesdadc1/common/fmcjesdadc1_spi.v Normal file
View File

@ -0,0 +1,150 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcjesdadc1_spi (
// master clock
sys_clk,
// 4-wire spi interface
spi4_csn,
spi4_clk,
spi4_mosi,
spi4_miso,
// 3-wire spi interface
spi3_csn,
spi3_clk,
spi3_sdio);
// parameters
localparam FMC27X_CPLD = 8'h00;
localparam FMC27X_AD9517 = 8'h84;
localparam FMC27X_AD9250_0 = 8'h80;
localparam FMC27X_AD9250_1 = 8'h81;
localparam FMC27X_AD9129_0 = 8'h82;
localparam FMC27X_AD9129_1 = 8'h83;
// master clock
input sys_clk;
// 4-wire spi interface
input spi4_csn;
input spi4_clk;
input spi4_mosi;
output spi4_miso;
// 3-wire spi interface
output spi3_csn;
output spi3_clk;
inout spi3_sdio;
// internal registers
reg spi4_clk_d = 'd0;
reg spi4_csn_d = 'd0;
reg [ 5:0] spi4_clkcnt = 'd0;
reg [ 6:0] spi4_bitcnt = 'd0;
reg [ 7:0] spi4_devid = 'd0;
reg spi4_rwn = 'd0;
reg spi3_enable = 'd0;
// pass through most of the stuff (no need to change clock or miso or mosi)
assign spi4_miso = spi3_sdio;
assign spi3_csn = spi4_csn;
assign spi3_clk = spi4_clk;
assign spi3_sdio = ((spi4_csn == 1'b0) && (spi3_enable == 1'b1)) ? 1'bz : spi4_mosi;
// the spi4 format is a preamble that selects a particular device, so all we need
// to do is collect the first 8 bits, then control the tristate based on the
// device's address and data widths. the details of the spi formats can be found
// in the data sheet of the devices.
always @(posedge sys_clk) begin
spi4_clk_d <= spi4_clk;
spi4_csn_d <= spi4_csn;
if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
spi4_clkcnt <= 6'd0;
end else begin
spi4_clkcnt <= spi4_clkcnt + 1'b1;
end
if ((spi4_csn == 1'b1) && (spi4_csn_d == 1'b0)) begin
spi4_bitcnt <= 7'd0;
spi4_devid <= 8'd0;
spi4_rwn <= 1'd0;
end else if ((spi4_clk == 1'b1) && (spi4_clk_d == 1'b0)) begin
spi4_bitcnt <= spi4_bitcnt + 1'b1;
if (spi4_bitcnt < 8) begin
spi4_devid <= {spi4_devid[6:0], spi4_mosi};
end
if (spi4_bitcnt == 8) begin
spi4_rwn <= spi4_mosi;
end
end
if (spi4_csn == 1'b0) begin
if ((spi4_devid == FMC27X_CPLD) || (spi4_devid == FMC27X_AD9129_0) ||
(spi4_devid == FMC27X_AD9129_1)) begin
if ((spi4_bitcnt == 16) && (spi4_clkcnt == 8)) begin
spi3_enable <= spi4_rwn;
end
end else if ((spi4_devid == FMC27X_AD9517) || (spi4_devid == FMC27X_AD9250_0) ||
(spi4_devid == FMC27X_AD9250_1)) begin
if ((spi4_bitcnt == 24) && (spi4_clkcnt == 8)) begin
spi3_enable <= spi4_rwn;
end
end
end else begin
spi3_enable <= 1'b0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

165
projects/scripts/adi_board.tcl
View File

@ -11,14 +11,14 @@ proc set_num {number} {
}
}
# search the first free HP port in case of a Zynq device
proc free_hp_port {} {
proc free_hp_port { sys_ps7 } {
set hp_port_num 0
set hp_port 1
while(hp_port) {
set hp_port_num [expr hp_port_num + 1]
set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" [get_bd_cells sys_ps7]]
while { $hp_port == 1 } {
set hp_port_num [expr $hp_port_num + 1]
set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" $sys_ps7]
}
return $hp_port_num
@ -42,9 +42,6 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
# sys_proc is a zynq
set sys_proc [get_bd_cells sys_ps7]
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
@ -57,13 +54,10 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${peripheral_name}/s_axi_aresetn"]
} else {
# sys_proc is a micorblaze
set sys_proc [get_bd_cells sys_mb]
# connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn_intc \
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
# connect clk and reset for the peripheral port
@ -109,12 +103,10 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
# sys_proc is a zynq
set sys_proc [get_bd_cells sys_ps7]
# add SPI interface to ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_proc
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_proc
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells sys_ps7]
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] [get_bd_cells sys_ps7]
set i 0
while { $i < $spi_ss_width } {
@ -155,58 +147,76 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
[get_bd_ports spi_csn_i] \
[get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_clk_i] \
[get_bd_ports spi_sclk_i] \
[get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_clk_o] \
[get_bd_ports spi_sclk_o] \
[get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i \
[get_bd_ports spi_sdo_i] \
[get_bd_ports spi_mosi_i] \
[get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o \
[get_bd_ports spi_sdo_o] \
[get_bd_ports spi_mosi_o] \
[get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i \
[get_bd_ports spi_sdi_i] \
[get_bd_ports spi_miso_i] \
[get_bd_pins sys_ps7/SPI0_MISO_I]
} else {
# SPI SS lines
set spi_csn_i [create_bd_port -dir I -from [expr $spi_ss_width - 1] -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
# instanciate AXI_SPI core
set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name
set_property -dict [list CONFIG.C_NUM_SS_BITS {$spi_ss_width}] $spi_name
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
switch $spi_ss_width {
1
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $spi_name
}
2
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $spi_name
}
3
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $spi_name
}
4
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $spi_name
}
}
adi_interconnect_lite $spi_name $spi_base_addr
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${spi_name}/ext_spi_clk"] \
$::sys_100m_clk_source
# spi external ports
connect_bd_net -net spi_csn_o \
[get_bd_ports spi_csn_o] \
[get_bd_pins "${spi_name}/ss_i"]
[get_bd_pins "${spi_name}/ss_o"]
connect_bd_net -net spi_csn_i \
[get_bd_ports spi_csn_i] \
[get_bd_pins "${spi_name}/ss_o"]
[get_bd_pins "${spi_name}/ss_i"]
connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_clk_o] \
[get_bd_ports spi_sclk_o] \
[get_bd_pins "${spi_name}/sck_o"]
connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_clk_i] \
[get_bd_ports spi_sclk_i] \
[get_bd_pins "${spi_name}/sck_i"]
connect_bd_net -net spi_mosi_o \
[get_bd_pins spi_sdo_o] \
[get_bd_ports spi_mosi_o] \
[get_bd_pins "${spi_name}/io0_o"]
connect_bd_net -net spi_mosi_i \
[get_bd_pins spi_sdo_i] \
[get_bd_ports spi_mosi_i] \
[get_bd_pins "${spi_name}/io0_i"]
connect_bd_net -net spi_miso_i \
[get_bd_ports spi_sdi_i] \
[get_bd_ports spi_miso_i] \
[get_bd_pins "${spi_name}/io1_i"]
create_bd_addr_seg -range 0x00010000 -offset $spi_base_addr
$::sys_addr_cntrl_space \
[get_bd_addr_segs "${spi_name}/axi_lite/Reg"] \
"SEG_data_${spi_name}"
}
}
@ -215,43 +225,59 @@ proc adi_dma_interconnect { dma_name port_name} {
# check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } {
set hp_port [free_hp_port]
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] $sys_ps7
set axi_dma_interconnect_($hp_port) [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_($hp_port)]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_($hp_port)
set hp_port [free_hp_port [get_bd_cells sys_ps7]]
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
switch $hp_port {
1
{
set axi_dma_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_1]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_1
}
2
{
set axi_dma_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_2]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_2
}
3
{
set axi_dma_interconnect_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_3]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_3
}
}
# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
connect_bd_net -net sys_100m_clk \
[get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_clk \
[get_bd_pins axi_ddr_interconnect/M00_ACLK] $::sys_100m_clk_source
[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_ddr_interconnect_m00_axi \
connect_bd_intf_net -intf_net axi_dma_interconnect_m00_axi \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \
[get_bd_intf_pins sys_ps7/S_AXI_HP1]
# connect clk and reset for the interconnect
connect_bd_net -net sys_200m_clk \
[get_bd_pins "${axi_dma_interconnect_($hp_port)}/S00_ACLK"] \
[get_bd_pins $clk]
connect_bd_net -net sys_100m_resetn_intc \
[get_bd_pins "$axi_dma_interconnect_($hp_port)/S00_ARESETN"] \
[get_bd_pins $reset_i]
connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ACLK"] \
$::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ARESETN"] \
$::sys_100m_resetn_source
# connect clk and reset for the peripheral port
puts "${dma_name}/${peripheral_port}_aclk"
connect_bd_net -net sys_200m_clk \
[get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
connect_bd_net -net sys_200m_resetn \
[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
puts "${dma_name}/${port_name}_aclk"
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${dma_name}/${port_name}_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
# Connect the interconnect to the dma
connect_bd_intf_net -intf_net ${dma_name}_interconnect_s00_axi \
connect_bd_intf_net -intf_net "axi_dma_interconnect_${hp_port}_s00_axi" \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \
[get_bd_intf_pins "${dma_name}/${port_name}"]
@ -262,35 +288,34 @@ proc adi_dma_interconnect { dma_name port_name} {
"SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
} else {
set axi_ddr_interconnect [get_bd_cells axi_ddr_interconnect]
set axi_mem_interconnect [get_bd_cells axi_mem_interconnect]
# increment the number of the master ports of the interconnect
set number_of_slave [get_property CONFIG.NUM_SI $axi_ddr_interconnect]
set number_of_slave [get_property CONFIG.NUM_SI $axi_mem_interconnect]
set number_of_slave [expr $number_of_slave + 1]
set_property CONFIG.NUM_SI $number_of_slave $axi_ddr_interconnect
set_property CONFIG.NUM_SI $number_of_slave $axi_mem_interconnect
# connect clk and reset for the interconnect
connect_bd_net -net sys_200m_clk \
[get_bd_pins "${axi_ddr_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
$::sys_200m_clk_source
connect_bd_net -net sys_100m_resetn_intc \
[get_bd_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${axi_mem_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
$::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
$::sys_100m_resetn_source
# connect clk and reset for the peripheral port
puts "${dma_name}/${peripheral_port}_aclk"
connect_bd_net -net sys_200m_clk \
[get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
connect_bd_net -net sys_200m_resetn \
[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${dma_name}/${port_name}_aclk"]
connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${dma_name}/${port_name}_aresetn"]
# make the port connection
connect_bd_intf_net -intf_net "axi_ddr_interconnect_s${number_of_slave}" \
[get_bd_intf_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_AXI"] \
[get_bd_intf_pins "${dma_name}/${peripheral_port}"]
connect_bd_intf_net -intf_net "axi_mem_interconnect_s${number_of_slave}" \
[get_bd_intf_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_AXI"] \
[get_bd_intf_pins "${dma_name}/${port_name}"]
# define address space for the peripheral
create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address \
[get_bd_addr_spaces "${dma_name}/${peripheral_port}"] \
create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
[get_bd_addr_spaces "${dma_name}/${port_name}"] \
[get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \
"SEG_data_${dma_name}_2_ddr"
}

1
projects/scripts/adi_project.tcl
View File

@ -88,6 +88,7 @@ proc adi_project_run {project_name} {
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
set_property STRATEGY "Performance_Explore" [get_runs impl_1]
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1