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axi_adc_trigger: added triggered flag

main
Adrian Costina 2017-06-23 14:36:22 +03:00
parent ca12938873
commit 9d572b406b
2 changed files with 21 additions and 5 deletions
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1
library/axi_adc_trigger/axi_adc_trigger_ip.tcl
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@ -6,6 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_adc_trigger
adi_ip_files axi_adc_trigger [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_adc_trigger_constr.xdc" \
"axi_adc_trigger_reg.v" \

25
library/axi_adc_trigger/axi_adc_trigger_reg.v
View File

@ -79,6 +79,7 @@ module axi_adc_trigger_reg (
// internal signals
wire [ 9:0] config_trigger;
wire adc_triggered;
// internal registers
@ -167,11 +168,11 @@ module axi_adc_trigger_reg (
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
up_fifo_depth <= up_wdata;
end
// if (triggered == 1'b1) begin
// up_triggered <= 1'b1;
// end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
// up_triggered <= up_wdata[0];
// end
if (adc_triggered == 1'b1) begin
up_triggered <= 1'b1;
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
up_triggered <= up_wdata[0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_trigger_delay <= up_wdata;
end
@ -245,6 +246,20 @@ module axi_adc_trigger_reg (
fifo_depth, // 32
trigger_delay})); // 32
up_xfer_status #(.DATA_WIDTH(1)) i_xfer_status (
// up interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(adc_triggered),
// device interface
.d_rst(1'd0),
.d_clk(clk),
.d_data_status(triggered));
endmodule
// ***************************************************************************