Fix warnings

main
AndreiGrozav 2016-11-14 15:17:15 +02:00
parent 12d6e46ae7
commit 9d6c93a5d8
7 changed files with 51 additions and 3 deletions

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@ -150,6 +150,7 @@ module axi_ad7616_control (
up_cnvst_en <= 1'b0; up_cnvst_en <= 1'b0;
up_conv_rate <= 32'b0; up_conv_rate <= 32'b0;
up_burst_length <= 5'h0; up_burst_length <= 5'h0;
up_write_data <= 16'h0;
end else begin end else begin
up_wack <= up_wreq_s; up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin

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@ -166,6 +166,7 @@ module axi_ad9162_core (
.dac_rst (dac_rst), .dac_rst (dac_rst),
.dac_sync (dac_sync_s), .dac_sync (dac_sync_s),
.dac_frame (), .dac_frame (),
.dac_clksel (),
.dac_par_type (), .dac_par_type (),
.dac_par_enb (), .dac_par_enb (),
.dac_r1_mode (), .dac_r1_mode (),

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@ -272,6 +272,13 @@ module axi_ad9361 #(
wire tdd_rx_rf_en_s; wire tdd_rx_rf_en_s;
wire tdd_tx_rf_en_s; wire tdd_tx_rf_en_s;
wire [ 7:0] tdd_status_s; wire [ 7:0] tdd_status_s;
wire up_drp_sel;
wire up_drp_wr;
wire [11:0] up_drp_addr;
wire [31:0] up_drp_wdata;
wire [31:0] up_drp_rdata;
wire up_drp_ready;
wire up_drp_locked;
// signal name changes // signal name changes

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@ -42,7 +42,7 @@ module axi_dmac (
input s_axi_aresetn, input s_axi_aresetn,
input s_axi_awvalid, input s_axi_awvalid,
input [13:0] s_axi_awaddr, input [31:0] s_axi_awaddr,
output s_axi_awready, output s_axi_awready,
input [2:0] s_axi_awprot, input [2:0] s_axi_awprot,
input s_axi_wvalid, input s_axi_wvalid,
@ -53,7 +53,7 @@ module axi_dmac (
output [ 1:0] s_axi_bresp, output [ 1:0] s_axi_bresp,
input s_axi_bready, input s_axi_bready,
input s_axi_arvalid, input s_axi_arvalid,
input [13:0] s_axi_araddr, input [31:0] s_axi_araddr,
output s_axi_arready, output s_axi_arready,
input [2:0] s_axi_arprot, input [2:0] s_axi_arprot,
output s_axi_rvalid, output s_axi_rvalid,

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@ -130,6 +130,7 @@ always @(negedge up_rstn or posedge up_clk)
begin begin
if (up_rstn == 0) if (up_rstn == 0)
begin begin
reserved_r1 <= 'd0;
up_wack <= 1'b0; up_wack <= 1'b0;
control_r <= 'h0; control_r <= 'h0;
reference_speed_r <= 'd1000; reference_speed_r <= 'd1000;

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@ -526,6 +526,41 @@ module util_adxcvr_xch #(
.TX_XCLK_SEL ("TXOUT"), .TX_XCLK_SEL ("TXOUT"),
.UCODEER_CLR (1'b0)) .UCODEER_CLR (1'b0))
i_gtxe2_channel ( i_gtxe2_channel (
.RXOUTCLKPCS (),
.RXPHSLIPMONITOR (),
.PHYSTATUS (),
.RXCDRLOCK (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCOMINITDET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADERVALID (),
.RXPHALIGNDONE (),
.RXQPISENN (),
.RXQPISENP (),
.RXRATEDONE (),
.RXSTARTOFSEQ (),
.RXVALID (),
.TXCOMFINISH (),
.TXDLYSRESETDONE (),
.TXGEARBOXREADY (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXQPISENN (),
.TXQPISENP (),
.TXRATEDONE (),
.PCSRSVDOUT (),
.RXCLKCORCNT (),
.RXHEADER (),
.RXCHBONDO (),
.RXPHMONITOR (),
.TSTOUT (),
.GTREFCLKMONITOR (),
.CFGRESET (1'h0), .CFGRESET (1'h0),
.CLKRSVD (4'h0), .CLKRSVD (4'h0),
.CPLLFBCLKLOST (), .CPLLFBCLKLOST (),

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@ -142,6 +142,9 @@ module util_adxcvr_xcm #(
.SIM_RESET_SPEEDUP ("TRUE"), .SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION ("4.0")) .SIM_VERSION ("4.0"))
i_gtxe2_common ( i_gtxe2_common (
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.REFCLKOUTMONITOR (),
.BGBYPASSB (1'h1), .BGBYPASSB (1'h1),
.BGMONITORENB (1'h1), .BGMONITORENB (1'h1),
.BGPDB (1'h1), .BGPDB (1'h1),