docs: Improve consistency (#1229)
* docs: Improve consistency The following rules have been implemented: 1. Tables/lists should contain only the carriers that we support for that reference design. 2. Hexadecimal addresses should be written in caps and separated by an underscore (eg. 0x9C4A_0000). 3. Block diagrams should contain subtitles only if there are at least two different diagrams. 4. The GPIOs should be listed in descending order and should have the number of bits specified next to their name. 5. All the source code links references should contain the project name. 6. The infrastructure documentation, if exists, should be listed after the IP list.main
StancaPop
GitHub
parent
679d8e71ab
commit
9dfd00018a
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@ -43,6 +43,8 @@ data stream at maximum data rate, is triggered by the BUSY signal of the device.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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.. image:: ad469x_hdl.svg
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:width: 800
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:align: center
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@ -51,14 +53,17 @@ Block diagram
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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===================== ==========
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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===================== ===========
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Instance Address
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===================== ==========
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axi_ad469x_dma 0x44a30000
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spi_clkgen 0x44a70000
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spi_ad469x_axi_regmap 0x44a00000
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ad469x_trigger_gen 0x44b00000
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===================== ==========
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===================== ===========
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axi_ad469x_dma 0x44A3_0000
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spi_clkgen 0x44A7_0000
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spi_ad469x_axi_regmap 0x44A0_0000
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ad469x_trigger_gen 0x44B0_0000
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===================== ===========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -157,11 +162,6 @@ A more comprehensive build guide can be found in the :ref:`build_hdl` user guide
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :dokuwiki:`AD469X User guide <resources/eval/user-guides/ad469x>`
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -175,8 +175,7 @@ Hardware related
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`ad469x_fmc HDL project <projects/ad469x_fmc>`
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- :ref:`SPI_ENGINE <spi_engine>`
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- :git-hdl:`AD469X_FMC HDL project source code <projects/ad469x_fmc>`
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.. list-table::
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:widths: 30 35 35
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@ -225,10 +224,12 @@ HDL related
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- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
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- :ref:`here <spi_engine offload>`
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- :ref:`SPI Engine Framework documentation <spi_engine>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-no-os:`No-OS project <projects/ad469x_fmcz>`
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- :git-no-os:`AD469X_FMCZ No-OS project source code <projects/ad469x_fmcz>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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@ -7,11 +7,11 @@ Overview
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-------------------------------------------------------------------------------
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The :adi:`AD7616` is a 16-bit, data acquisition system (DAS) that supports
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dual simultaneous sampling of 16 channels. The :adi:`AD7616` operates from a
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single 5 V supply and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar
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input signals while sampling at throughput rates up to 1 MSPS per channel pair
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with 90 dB SNR. Higher SNR performance can be achieved with the on-chip
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oversampling mode; 92 dB for an oversampling ratio of 2.
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dual simultaneous sampling of 16 channels. It operates from a single 5 V supply
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and can accommodate ±10 V, ±5 V, and ±2.5 V true bipolar input signals while
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sampling at throughput rates up to 1 MSPS per channel pair with 90 dB SNR.
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Higher SNR performance can be achieved with the on-chip oversampling mode;
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92 dB for an oversampling ratio of 2.
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The input clamp protection circuitry can tolerate voltages up to ±20 V.
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The :adi:`AD7616` has 1 MΩ analog input impedance regardless of sampling
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@ -57,6 +57,8 @@ The data path of the HDL design is simple as follows:
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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AD7616_SDZ serial interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -120,15 +122,18 @@ LK41 A Onboard 3v3 power supply selected
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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======================== ==========
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ==========
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axi_ad7616_dma 0x44a30000
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spi_clkgen 0x44a70000
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ad7616_pwm_gen 0x44b00000
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spi_ad7616_axi_regmap ** 0x44a00000
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axi_ad7616 * 0x44a80000
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======================== ==========
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======================== ===========
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axi_ad7616_dma 0x44A3_0000
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spi_clkgen 0x44A7_0000
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ad7616_pwm_gen 0x44B0_0000
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spi_ad7616_axi_regmap ** 0x44A0_0000
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axi_ad7616 * 0x44A8_0000
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======================== ===========
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.. admonition:: Legend
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:class: note
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@ -198,11 +203,11 @@ The Software GPIO number is calculated as follows:
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- OUT
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- 43
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- 97
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* - adc_hw_rngsel
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* - adc_hw_rngsel[1:0]
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- OUT
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- 42:41
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- 96:95
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* - adc_os **
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* - adc_os[2:0] **
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- OUT
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- 40:38
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- 94:92
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@ -214,7 +219,7 @@ The Software GPIO number is calculated as follows:
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- OUT
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- 36
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- 90
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* - adc_chsel
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* - adc_chsel[2:0]
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- OUT
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- 35:33
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- 89:87
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@ -297,12 +302,6 @@ Connections and hardware changes
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :dokuwiki:`AD7616 User guide <resources/eval/user-guides/ad7616-sdz>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -313,7 +312,7 @@ Hardware related
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`ad7616_sdz HDL project <projects/ad7616_sdz>`
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- :git-hdl:`AD7616_SDZ HDL project source code <projects/ad7616_sdz>`
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.. list-table::
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:widths: 30 35 35
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@ -374,12 +373,12 @@ HDL related
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- ``*`` instantiated only for SER_PAR_N=0 (parallel interface)
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- ``**`` instantiated only for SER_PAR_N=1 (serial interface)
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- :ref:`SPI_ENGINE <spi_engine>`
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- :ref:`SPI Engine Framework documentation <spi_engine>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-no-os:`No-OS project <projects/ad7616-sdz>`
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- :git-no-os:`AD7616_SDZ No-OS project source code <projects/ad7616-sdz>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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@ -107,6 +107,8 @@ Block design
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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Example block design for Single link; M=8; L=4
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -370,61 +372,61 @@ GPIOs
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-
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- Zynq-7000
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- Zynq MP
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* - gpio[0:10]
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- INOUT
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- 32-42
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- 86-96
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- 110-120
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* - hmc_gpio1
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- INOUT
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- 43
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- 97
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- 121
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* - agc0[0:1]
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- IN
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- 44, 45
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- 98, 99
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- 122, 123
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* - agc1[0:1]
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- IN
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- 46, 47
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- 100, 101
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- 124, 125
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* - agc2[0:1]
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- IN
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- 48, 49
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- 102, 103
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- 126, 127
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* - agc3[0:1]
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- IN
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- 50, 51
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- 104, 105
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- 128, 129
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* - irqb[0:1]
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- IN
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- 52, 53
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- 106, 107
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- 130, 131
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* - hmc_sync
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* - txen[1:0]
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- OUT
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- 54
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- 108
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- 132
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- 59:58
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- 113:112
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- 137:136
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* - rxen[1:0]
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- OUT
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- 57:56
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- 111:110
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- 135:134
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* - rstb
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- OUT
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- 55
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- 109
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- 133
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* - rxen[0:1]
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* - hmc_sync
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- OUT
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- 56, 57
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- 110, 111
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- 134, 135
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* - txen[0:1]
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- OUT
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- 58, 59
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- 112, 113
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- 136, 137
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- 54
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- 108
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- 132
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* - irqb[1:0]
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- IN
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- 53:52
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- 107:106
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- 131:130
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* - agc3[1:0]
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- IN
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- 51:50
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- 105:104
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- 129:128
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* - agc2[1:0]
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- IN
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- 49:48
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- 103:102
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- 127:126
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* - agc1[1:0]
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- IN
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- 47:46
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- 101:100
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- 125:124
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* - agc0[1:0]
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- IN
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- 45:44
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- 99:98
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- 123:122
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* - hmc_gpio1
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- INOUT
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- 43
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- 97
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- 121
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* - gpio[10:0]
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- INOUT
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- 42:32
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- 96:86
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- 120:110
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -141,21 +141,13 @@ Systems related
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Here you can find the quick start guides available for these evaluation boards:
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.. list-table::
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:widths: 20 10 20 20 20 10
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:widths: 50 50
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:header-rows: 1
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* - Evaluation board
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- Zynq-7000
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- Zynq UltraScale+ MP
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- Microblaze
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- Versal
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- Arria 10
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* - AD9783-EBZ
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- ---
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- :dokuwiki:`[Wiki] ZCU102 <resources/fpga/xilinx/interposer/ad9783>`
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- ---
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- ---
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- ---
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -199,8 +191,8 @@ HDL related
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts <master:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts>`
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- :git-linux:`Linux driver ad9783.c <master:drivers/iio/frequency>`
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- :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts <arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts>`
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- :git-linux:`Linux driver ad9783.c <drivers/iio/frequency>`
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.. include:: ../common/more_information.rst
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@ -60,6 +60,8 @@ Block design
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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.. image:: adaq7980_sdz_hdl.svg
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:width: 800
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:align: center
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@ -68,14 +70,17 @@ Block diagram
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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=========================== ==========
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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=========================== ===========
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Instance Address
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=========================== ==========
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axi_adaq7980_dma 0x44a30000
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spi_clkgen 0x44a70000
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spi_adaq7980_adc_axi_regmap 0x44a00000
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spi_trigger_gen 0x44b00000
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=========================== ==========
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=========================== ===========
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axi_adaq7980_dma 0x44A3_0000
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spi_clkgen 0x44A7_0000
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spi_adaq7980_adc_axi_regmap 0x44A0_0000
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spi_trigger_gen 0x44B0_0000
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=========================== ===========
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -143,7 +148,7 @@ The Software GPIO number is calculated as follows:
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- INOUT
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- 40
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- 94
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* - adaq7980_gpio
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* - adaq7980_gpio[7:0]
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- INOUT
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- 39:32
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- 93:86
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@ -182,12 +187,6 @@ A more comprehensive build guide can be found in the :ref:`build_hdl` user guide
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :dokuwiki:`ADAQ7980 User guide <resources/eval/user-guides/adaq7980-sdz>`
|
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
|
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|
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -198,8 +197,7 @@ Hardware related
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`adaq7980_sdz HDL project <projects/adaq7980_sdz>`
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- :ref:`SPI_ENGINE <spi_engine>`
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- :git-hdl:`ADAQ7980_SDZ HDL project source code <projects/adaq7980_sdz>`
|
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|
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.. list-table::
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:widths: 30 35 35
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@ -209,49 +207,51 @@ HDL related
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- Source code link
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- Documentation link
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_dmac <main:library/axi_clkgen>`
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- :git-hdl:`library/axi_dmac <library/axi_clkgen>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
|
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <master:library/axi_dmac>`
|
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- :git-hdl:`library/axi_dmac <library/axi_dmac>`
|
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- :ref:`here <axi_dmac>`
|
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* - AXI_HDMI_TX
|
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- :git-hdl:`library/axi_hdmi_tx <main:library/axi_hdmi_tx>`
|
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- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
|
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
|
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi <main:library/axi_i2s_adi>`
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- :git-hdl:`library/axi_i2s_adi <library/axi_i2s_adi>`
|
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- ---
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* - AXI_PWM_GEN
|
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- :git-hdl:`library/axi_pwm_gen <main:library/axi_pwm_gen>`
|
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- :git-hdl:`library/axi_pwm_gen <library/axi_pwm_gen>`
|
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
|
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* - AXI_SPDIF_TX
|
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- :git-hdl:`library/axi_spdif_tx <main:library/axi_spdif_tx>`
|
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- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
|
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- ---
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* - AXI_SPI_ENGINE
|
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- :git-hdl:`library/spi_engine/axi_spi_engine <main:library/spi_engine/axi_spi_engine>`
|
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- :git-hdl:`library/spi_engine/axi_spi_engine <library/spi_engine/axi_spi_engine>`
|
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- :ref:`here <spi_engine axi>`
|
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* - AXI_SYSID
|
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- :git-hdl:`library/axi_sysid <main:library/axi_sysid>`
|
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- :git-hdl:`library/axi_sysid <library/axi_sysid>`
|
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
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* - SPI_ENGINE_EXECUTION
|
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- :git-hdl:`library/spi_engine/spi_engine_execution <main:library/spi_engine/spi_engine_execution>`
|
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- :git-hdl:`library/spi_engine/spi_engine_execution <library/spi_engine/spi_engine_execution>`
|
||||
- :ref:`here <spi_engine execution>`
|
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* - SPI_ENGINE_INTERCONNECT
|
||||
- :git-hdl:`library/spi_engine/spi_engine_interconnect <main:library/spi_engine/spi_engine_interconnect>`
|
||||
- :git-hdl:`library/spi_engine/spi_engine_interconnect <library/spi_engine/spi_engine_interconnect>`
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- :ref:`here <spi_engine interconnect>`
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* - SPI_ENGINE_OFFLOAD
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- :git-hdl:`library/spi_engine/spi_engine_offload <main:library/spi_engine/spi_engine_offload>`
|
||||
- :git-hdl:`library/spi_engine/spi_engine_offload <library/spi_engine/spi_engine_offload>`
|
||||
- :ref:`here <spi_engine offload>`
|
||||
* - SYSID_ROM
|
||||
- :git-hdl:`library/sysid_rom <main:library/sysid_rom>`
|
||||
- :git-hdl:`library/sysid_rom <library/sysid_rom>`
|
||||
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
||||
* - UTIL_I2C_MIXER
|
||||
- :git-hdl:`library/util_i2c_mixer <main:library/util_i2c_mixer>`
|
||||
- :git-hdl:`library/util_i2c_mixer <library/util_i2c_mixer>`
|
||||
- :ref:`here <spi_engine offload>`
|
||||
|
||||
- :ref:`SPI Engine Framework documentation <spi_engine>`
|
||||
|
||||
Software related
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
- :git-no-os:`No-OS project <projects/adaq7980_sdz>`
|
||||
- :git-no-os:`ADAQ7980_SDZ No-OS project <projects/adaq7980_sdz>`
|
||||
|
||||
- :dokuwiki:`How to build No-OS <resources/no-os/build>`
|
||||
|
||||
|
|
|
|||
|
|
@ -277,21 +277,21 @@ GPIOs
|
|||
-
|
||||
- Zynq-7000
|
||||
- Zynq MP
|
||||
* - signal name
|
||||
* - signal_name[31:0]
|
||||
- IN/OUT/INOUT
|
||||
- 32-63
|
||||
- 86-117
|
||||
- 110-141
|
||||
* - signal name
|
||||
- 127:96
|
||||
- 181:150
|
||||
- 205:174
|
||||
* - signal_name[31:0]
|
||||
- IN/OUT/INOUT
|
||||
- 64-95
|
||||
- 118-149
|
||||
- 142-173
|
||||
* - signal name
|
||||
- 95:64
|
||||
- 149:118
|
||||
- 173:142
|
||||
* - signal_name[31:0]
|
||||
- IN/OUT/INOUT
|
||||
- 96-127
|
||||
- 150-181
|
||||
- 174-205
|
||||
- 63:32
|
||||
- 117:86
|
||||
- 141:110
|
||||
|
||||
Interrupts
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -702,9 +702,15 @@ HDL related
|
|||
- :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac`
|
||||
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/jesd204_tpl_dac>`
|
||||
|
||||
\**\* MENTION THESE for JESD reference designs \**\*
|
||||
|
||||
- :dokuwiki:`[Wiki] Generic JESD204B block designs <resources/fpga/docs/hdl/generic_jesd_bds>`
|
||||
- :dokuwiki:`[Wiki] JESD204B High-Speed Serial Interface Support <resources/fpga/peripherals/jesd204>`
|
||||
|
||||
\**\* MENTION THIS for SPI Engine reference designs \**\*
|
||||
|
||||
- :ref:`SPI Engine Framework documentation <spi_engine>`
|
||||
|
||||
Software related
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue