xfer-logic: stretch toggles to allow capture
parent
e9231c8f36
commit
9e2e2ef44e
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@ -72,6 +72,9 @@ module up_xfer_status (
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// internal registers
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reg d_xfer_state_m1 = 'd0;
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reg d_xfer_state_m2 = 'd0;
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reg d_xfer_state = 'd0;
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reg [ 5:0] d_xfer_count = 'd0;
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reg d_xfer_toggle = 'd0;
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reg [DW:0] d_xfer_data = 'd0;
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@ -79,27 +82,37 @@ module up_xfer_status (
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reg up_xfer_toggle_m1 = 'd0;
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reg up_xfer_toggle_m2 = 'd0;
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reg up_xfer_toggle_m3 = 'd0;
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reg up_xfer_toggle = 'd0;
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reg [DW:0] up_data_status = 'd0;
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// internal signals
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wire d_xfer_enable_s;
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wire up_xfer_toggle_s;
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// device status transfer
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assign d_xfer_enable_s = d_xfer_state ^ d_xfer_toggle;
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always @(posedge d_clk) begin
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if (d_rst == 1'b1) begin
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d_xfer_state_m1 <= 'd0;
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d_xfer_state_m2 <= 'd0;
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d_xfer_state <= 'd0;
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d_xfer_count <= 'd0;
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d_xfer_toggle <= 'd0;
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d_xfer_data <= 'd0;
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d_acc_data <= 'd0;
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end else begin
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d_xfer_state_m1 <= up_xfer_toggle;
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d_xfer_state_m2 <= d_xfer_state_m1;
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d_xfer_state <= d_xfer_state_m2;
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d_xfer_count <= d_xfer_count + 1'd1;
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if (d_xfer_count == 6'd1) begin
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_xfer_toggle <= ~d_xfer_toggle;
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d_xfer_data <= d_acc_data;
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end
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if (d_xfer_count == 6'd1) begin
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if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin
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d_acc_data <= d_data_status;
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end else begin
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d_acc_data <= d_acc_data | d_data_status;
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@ -114,11 +127,13 @@ module up_xfer_status (
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up_xfer_toggle_m1 <= 'd0;
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up_xfer_toggle_m2 <= 'd0;
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up_xfer_toggle_m3 <= 'd0;
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up_xfer_toggle <= 'd0;
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up_data_status <= 'd0;
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end else begin
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up_xfer_toggle_m1 <= d_xfer_toggle;
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up_xfer_toggle_m2 <= up_xfer_toggle_m1;
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up_xfer_toggle_m3 <= up_xfer_toggle_m2;
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up_xfer_toggle <= up_xfer_toggle_m3;
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if (up_xfer_toggle_s == 1'b1) begin
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up_data_status <= d_xfer_data;
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end
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