From 9e50f5afa84d13bc7827892435a5d1abe1aef33a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 20 Jun 2017 16:00:03 +0200 Subject: [PATCH] jesd204: Handle sysref events in the register map There are currently two sysref related events. One the sysref captured event which is generated when an external sysref edge has been observed. The other is the sysref alignment error event which is generated when a sysref edge is observed that has a different alignment from previously observed sysref edges. Capture those events in the register map. This is useful for error diagnostic. The events are sticky and write-1-to-clear. Signed-off-by: Lars-Peter Clausen --- .../axi_jesd204_common/jesd204_up_sysref.v | 39 ++++++++++++++++++- .../jesd204/axi_jesd204_rx/axi_jesd204_rx.v | 3 +- .../axi_jesd204_rx/axi_jesd204_rx_constr.xdc | 12 ++++++ .../jesd204/axi_jesd204_tx/axi_jesd204_tx.v | 3 +- .../axi_jesd204_tx/axi_jesd204_tx_constr.xdc | 12 ++++++ library/jesd204/jesd204_common/lmfc.v | 6 +-- library/jesd204/jesd204_rx/rx.v | 5 +-- library/jesd204/jesd204_tx/tx.v | 2 - 8 files changed, 69 insertions(+), 13 deletions(-) diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v index c5d50a2e5..437149df8 100644 --- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v +++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v @@ -61,12 +61,37 @@ module jesd204_up_sysref ( output reg [7:0] up_cfg_lmfc_offset, output reg up_cfg_sysref_disable, - input core_event_sysref_alignment_error + input core_event_sysref_alignment_error, + input core_event_sysref_edge ); reg up_status_sysref_alignment_error = 1'b0; wire up_status_sysref_captured; +reg [1:0] up_sysref_status; +reg [1:0] up_sysref_status_clear; +wire [1:0] up_sysref_event; + +sync_event #( + .NUM_OF_EVENTS(2) +) i_sysref_event_sync ( + .in_clk(core_clk), + .in_event({ + core_event_sysref_alignment_error, + core_event_sysref_edge + }), + .out_clk(up_clk), + .out_event(up_sysref_event) +); + +always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_sysref_status <= 2'b00; + end else begin + up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event; + end +end + always @(*) begin case (up_raddr) /* JESD SYSREF configuraton */ @@ -80,6 +105,10 @@ always @(*) begin /* 02-09 */ up_cfg_lmfc_offset, /* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */ }; + 12'h042: up_rdata <= { + /* 02-31 */ 30'h00, + /* 00-01 */ up_sysref_status + }; default: up_rdata <= 32'h00000000; endcase end @@ -104,4 +133,12 @@ always @(posedge up_clk) begin end end +always @(*) begin + if (up_wreq == 1'b1 && up_waddr == 12'h042) begin + up_sysref_status_clear <= up_wdata[1:0]; + end else begin + up_sysref_status_clear <= 2'b00; + end +end + endmodule diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v index df27ba2c9..ea60cbd01 100644 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v @@ -215,7 +215,8 @@ jesd204_up_sysref i_up_sysref ( .up_reset(up_reset), .core_clk(core_clk), - .core_event_sysref_alignment_error(), + .core_event_sysref_edge(core_event_sysref_edge), + .core_event_sysref_alignment_error(core_event_sysref_alignment_error), .up_raddr(up_raddr), .up_rdata(up_rdata_sysref), diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc index aacb6dfce..9174a6c8b 100644 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc @@ -63,6 +63,18 @@ set_false_path \ -from [get_pins {i_up_rx/i_sync_status/out_toggle_d1_reg/C}] \ -to [get_pins {i_up_rx/i_sync_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] + # Don't place them too far appart set_max_delay -datapath_only \ -from [get_pins {i_up_rx/i_sync_status/cdc_hold_reg[*]/C}] \ diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v index 0d75eabc6..31601141d 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v @@ -240,7 +240,8 @@ jesd204_up_sysref i_up_sysref ( .up_reset(up_reset), .core_clk(core_clk), - .core_event_sysref_alignment_error(1'b0), // FIXME + .core_event_sysref_alignment_error(core_event_sysref_alignment_error), + .core_event_sysref_edge(core_event_sysref_edge), .up_cfg_lmfc_offset(up_cfg_lmfc_offset), .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot), diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc index b3e1a53c4..da4425cae 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc @@ -63,6 +63,18 @@ set_false_path \ -from [get_pins {i_up_tx/i_sync_state/in_toggle_d1_reg/C}] \ -to [get_pins {i_up_tx/i_sync_state/i_sync_out/cdc_sync_stage1_reg[0]/D}] +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_sysref_event_sync/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_sysref_event_sync/out_event_reg*/D}] + # Don't place them too far appart set_max_delay -datapath_only \ -from [get_pins {i_up_tx/i_sync_state/cdc_hold_reg[*]/C}] \ diff --git a/library/jesd204/jesd204_common/lmfc.v b/library/jesd204/jesd204_common/lmfc.v index 799fefc34..0ad79bde5 100644 --- a/library/jesd204/jesd204_common/lmfc.v +++ b/library/jesd204/jesd204_common/lmfc.v @@ -51,14 +51,12 @@ module jesd204_lmfc ( input [7:0] cfg_beats_per_multiframe, input [7:0] cfg_lmfc_offset, input cfg_sysref_oneshot, - input clear_sysref_captured, input cfg_sysref_disable, output reg lmfc_edge, output reg lmfc_clk, output reg [7:0] lmfc_counter, - output reg sysref_captured, output reg sysref_edge, output reg sysref_alignment_error ); @@ -68,6 +66,8 @@ reg sysref_d1 = 1'b0; reg sysref_d2 = 1'b0; reg sysref_d3 = 1'b0; +reg sysref_captured; + /* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */ reg [7:0] lmfc_counter_next = 'h00; @@ -104,8 +104,6 @@ always @(posedge clk) begin sysref_captured <= 1'b0; end else if (sysref_edge == 1'b1) begin sysref_captured <= 1'b1; - end else if (clear_sysref_captured == 1'b1) begin - sysref_captured <= 1'b0; end end diff --git a/library/jesd204/jesd204_rx/rx.v b/library/jesd204/jesd204_rx/rx.v index d93356960..55f26c160 100644 --- a/library/jesd204/jesd204_rx/rx.v +++ b/library/jesd204/jesd204_rx/rx.v @@ -221,10 +221,7 @@ jesd204_lmfc i_lmfc ( .lmfc_counter(lmfc_counter), .sysref_edge(event_sysref_edge), - .sysref_alignment_error(event_sysref_alignment_error), - - .sysref_captured(), - .clear_sysref_captured(1'b0) + .sysref_alignment_error(event_sysref_alignment_error) ); jesd204_rx_ctrl #( diff --git a/library/jesd204/jesd204_tx/tx.v b/library/jesd204/jesd204_tx/tx.v index 1db770a53..4615fde03 100644 --- a/library/jesd204/jesd204_tx/tx.v +++ b/library/jesd204/jesd204_tx/tx.v @@ -127,8 +127,6 @@ jesd204_lmfc i_lmfc ( .sysref(sysref), - .clear_sysref_captured(1'b0), - .sysref_captured(), .sysref_edge(event_sysref_edge), .sysref_alignment_error(event_sysref_alignment_error),