zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arradio/ad9361- updates

main
Rejeesh Kutty 2016-10-31 15:34:32 -04:00
parent b94cc8afb1
commit 9f4c5f8060
3 changed files with 185 additions and 139 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
library/altera/alt_serdes/alt_serdes_hw.tcl
View File

@ -29,7 +29,7 @@ set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
set_parameter_property SERDES_FACTOR TYPE INTEGER
set_parameter_property SERDES_FACTOR UNITS None
set_parameter_property SERDES_FACTOR HDL_PARAMETER false
set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
set_parameter_property SERDES_FACTOR ALLOWED_RANGES {2 4 8}
add_parameter CLKIN_FREQUENCY FLOAT 500.0
set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
@ -66,6 +66,22 @@ proc p_alt_serdes {} {
## arria 10, serdes clock, data-in and data-out
if {($m_serdes_factor == 2) && ($m_device_family == "Arria 10")} {
add_hdl_instance alt_serdes_out altera_gpio
set_instance_parameter_value alt_serdes_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_serdes_out {SIZE} {1}
set_instance_parameter_value alt_serdes_out {gui_diff_buff} {0}
set_instance_parameter_value alt_serdes_out {gui_io_reg_mode} {DDIO}
return
}
if {($m_serdes_factor == 2) && ($m_device_family == "Cyclone V")} {
return
}
if {($m_mode == "CLK") && ($m_device_family == "Arria 10")} {
add_instance alt_serdes_pll altera_iopll
@ -109,6 +125,8 @@ proc p_alt_serdes {} {
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
return
}
if {($m_mode == "IN") && ($m_device_family == "Arria 10")} {
@ -137,6 +155,8 @@ proc p_alt_serdes {} {
set_interface_property data_s EXPORT_OF alt_serdes_in.rx_out
add_interface delay_locked conduit end
set_interface_property delay_locked EXPORT_OF alt_serdes_in.rx_dpa_locked
return
}
if {($m_mode == "OUT") && ($m_device_family == "Arria 10")} {
@ -161,6 +181,8 @@ proc p_alt_serdes {} {
set_interface_property div_clk EXPORT_OF alt_serdes_out.ext_coreclock
add_interface data_s conduit end
set_interface_property data_s EXPORT_OF alt_serdes_out.tx_in
return
}
## cyclone v, serdes clock, data-in and data-out
@ -205,6 +227,8 @@ proc p_alt_serdes {} {
set_interface_property drp_rst EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
add_interface pll_reconfig avalon slave
set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
return
}
}

209
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -1,85 +1,72 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9361
set_module_property DESCRIPTION "AXI AD9361 Interface"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9361
set_module_property ELABORATION_CALLBACK p_axi_ad9361
# files
add_fileset quartus_synth QUARTUS_SYNTH "p_axi_ad9361_fset" ""
set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file ad_addsub.v VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v
add_fileset_file ad_tdd_control.v VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
add_fileset_file up_tdd_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_tdd_cntrl.v
add_fileset_file axi_ad9361_lvds_if.v VERILOG PATH altera/axi_ad9361_lvds_if.v
add_fileset_file axi_ad9361_cmos_if.v VERILOG PATH altera/axi_ad9361_cmos_if.v
add_fileset_file axi_ad9361_rx_pnmon.v VERILOG PATH axi_ad9361_rx_pnmon.v
add_fileset_file axi_ad9361_rx_channel.v VERILOG PATH axi_ad9361_rx_channel.v
add_fileset_file axi_ad9361_rx.v VERILOG PATH axi_ad9361_rx.v
add_fileset_file axi_ad9361_tx_channel.v VERILOG PATH axi_ad9361_tx_channel.v
add_fileset_file axi_ad9361_tx.v VERILOG PATH axi_ad9361_tx.v
add_fileset_file axi_ad9361_tdd.v VERILOG PATH axi_ad9361_tdd.v
add_fileset_file axi_ad9361_tdd_if.v VERILOG PATH axi_ad9361_tdd_if.v
add_fileset_file axi_ad9361.v VERILOG PATH axi_ad9361.v TOP_LEVEL_FILE
add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
add_fileset_file axi_ad9361_constr.sdc SDC PATH axi_ad9361_constr.sdc
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
ad_ip_files axi_ad9361 [list\
$ad_hdl_dir/library/altera/common/ad_cmos_out_core_c5.v \
$ad_hdl_dir/library/altera/common/ad_serdes_in_core_c5.v \
$ad_hdl_dir/library/altera/common/ad_serdes_out_core_c5.v \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/altera/common/ad_dcfilter.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/ad_pnmon.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_datafmt.v \
$ad_hdl_dir/library/common/ad_iqcor.v \
$ad_hdl_dir/library/common/ad_addsub.v \
$ad_hdl_dir/library/common/ad_tdd_control.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_delay_cntrl.v \
$ad_hdl_dir/library/common/up_adc_common.v \
$ad_hdl_dir/library/common/up_adc_channel.v \
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
$ad_hdl_dir/library/common/up_tdd_cntrl.v \
altera/axi_ad9361_lvds_if.v \
altera/axi_ad9361_cmos_if.v \
axi_ad9361_rx_pnmon.v \
axi_ad9361_rx_channel.v \
axi_ad9361_rx.v \
axi_ad9361_tx_channel.v \
axi_ad9361_tx.v \
axi_ad9361_tdd.v \
axi_ad9361_tdd_if.v \
axi_ad9361.v \
$ad_hdl_dir/library/common/ad_axi_ip_constr.sdc \
axi_ad9361_constr.sdc] \
axi_ad9361_fileset
# parameters
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter ID INTEGER 0
add_parameter MODE_1R1T INTEGER 0
add_parameter DEVICE_TYPE INTEGER 0
add_parameter TDD_DISABLE INTEGER 0
add_parameter CMOS_OR_LVDS_N INTEGER 0
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
add_parameter ADC_USERPORTS_DISABLE INTEGER 0
add_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
add_parameter ADC_DCFILTER_DISABLE INTEGER 0
add_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
add_parameter DAC_IODELAY_ENABLE INTEGER 0
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
add_parameter DAC_DDS_DISABLE INTEGER 0
add_parameter DAC_USERPORTS_DISABLE INTEGER 0
add_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
add_parameter IO_DELAY_GROUP STRING "dev_if_delay_group"
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter ID INTEGER 0
ad_ip_parameter MODE_1R1T INTEGER 0
ad_ip_parameter DEVICE_TYPE INTEGER 0
ad_ip_parameter TDD_DISABLE INTEGER 0
ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0
ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0
ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0
ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0
ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0
ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0
ad_ip_parameter DAC_DDS_DISABLE INTEGER 0
ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
# interfaces
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# master-slave interface
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
ad_alt_intf signal tdd_sync input 1
@ -171,12 +158,37 @@ ad_alt_intf signal up_dac_gpio_out output 32
ad_alt_intf signal up_adc_gpio_in input 32
ad_alt_intf signal up_adc_gpio_out output 32
# generated cores
add_hdl_instance ad_serdes_clk_core alt_serdes
set_instance_parameter_value ad_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value ad_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_in_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_in_core_a10 {MODE} {IN}
set_instance_parameter_value ad_serdes_in_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_in_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_in_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_serdes_out_core_a10 alt_serdes
set_instance_parameter_value ad_serdes_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_serdes_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_serdes_out_core_a10 {SERDES_FACTOR} {4}
set_instance_parameter_value ad_serdes_out_core_a10 {CLKIN_FREQUENCY} {250.0}
add_hdl_instance ad_cmos_out_core_a10 alt_serdes
set_instance_parameter_value ad_cmos_out_core_a10 {MODE} {OUT}
set_instance_parameter_value ad_cmos_out_core_a10 {DDR_OR_SDR_N} {1}
set_instance_parameter_value ad_cmos_out_core_a10 {SERDES_FACTOR} {2}
set_instance_parameter_value ad_cmos_out_core_a10 {CLKIN_FREQUENCY} {250.0}
# updates
proc p_axi_ad9361 {} {
proc axi_ad9361_elab {} {
set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N]
set m_device_family [get_parameter_value DEVICE_FAMILY]
add_interface device_if conduit end
set_interface_property device_if associatedClock none
@ -210,58 +222,13 @@ proc p_axi_ad9361 {} {
add_interface_port device_if enable enable Output 1
add_interface_port device_if txnrx txnrx Output 1
if {$m_device_family == "Arria 10"} {
add_hdl_instance alt_serdes_clk_core alt_serdes
set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK}
set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_in_core alt_serdes
set_instance_parameter_value alt_serdes_in_core {MODE} {IN}
set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_serdes_out_core alt_serdes
set_instance_parameter_value alt_serdes_out_core {MODE} {OUT}
set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1}
set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4}
set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0}
add_hdl_instance alt_ddio_in altera_gpio
set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input}
set_instance_parameter_value alt_ddio_in {SIZE} {1}
set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO}
add_hdl_instance alt_ddio_out altera_gpio
set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output}
set_instance_parameter_value alt_ddio_out {SIZE} {1}
set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0}
set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO}
}
if {$m_device_family == "Cyclone V"} {
## add_hdl_instance do not work here (pending altera support)
}
}
proc p_axi_ad9361_fset {entityName} {
proc axi_ad9361_fileset {entityName} {
ad_ip_file ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
ad_ip_file ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
ad_ip_file ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
ad_ip_file ad_cmos_in.v ad_cmos_in.v ad_cmos_in_core
ad_ip_file ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
add_fileset_file ad_serdes_in.v VERILOG PATH ad_serdes_in.v
add_fileset_file ad_serdes_out.v VERILOG PATH ad_serdes_out.v
add_fileset_file ad_serdes_clk.v VERILOG PATH ad_serdes_clk.v
add_fileset_file ad_cmos_in.v VERILOG PATH ad_cmos_in.v
add_fileset_file ad_cmos_out.v VERILOG PATH ad_cmos_out.v
ad_ip_modfile ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core
ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core
}

89
library/scripts/adi_ip_alt.tcl
View File

@ -1,4 +1,5 @@
###################################################################################################
###################################################################################################
# keep interface-mess out of the way - keeping it pretty is a waste of time
proc ad_alt_intf {type name dir width {arg_1 ""} {arg_2 ""}} {
@ -89,41 +90,87 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
close $fp_target
}
###################################################################################################
###################################################################################################
proc ad_ip_create {pname pdesc {pelabfunction ""} {pcomposefunction ""}} {
set_module_property NAME $pname
set_module_property DESCRIPTION $pdesc
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME $pname
if {$pelabfunction ne ""} {
set_module_property ELABORATION_CALLBACK $pelabfunction
}
if {$pcomposefunction ne ""} {
set_module_property ELABORATION_CALLBACK $pcomposefunction
}
}
###################################################################################################
###################################################################################################
proc ad_ip_parameter {pname ptype pdefault} {
if {$pname eq "DEVICE_FAMILY"} {
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
return
}
add_parameter $pname $ptype $pdefault
set_parameter_property $pname HDL_PARAMETER true
set_parameter_property $pname ENABLED true
}
proc ad_ip_files {pname pfiles {pfunction ""}} {
###################################################################################################
###################################################################################################
set ftopfile [lindex $pfiles end]
set pfiles [lreplace $pfiles end end]
proc ad_ip_addfile {pname pfile} {
set pmodule [file tail $pfile]
regsub {\..$} $pmodule {} mname
if {$pname eq $mname} {
add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
return
}
set ptype [file extension $pfile]
if {$ptype eq ".v"} {
add_fileset_file $pmodule VERILOG PATH $pfile
return
}
if {$ptype eq ".sdc"} {
add_fileset_file $pmodule SDC PATH $pfile
return
}
}
proc ad_ip_files {pname pfiles {pfunction ""}} {
add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
set_fileset_property quartus_synth TOP_LEVEL $pname
foreach pfile $pfiles {
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile
ad_ip_addfile $pname $pfile
}
set pfile $ftopfile
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
add_fileset quartus_sim SIM_VERILOG $pfunction ""
set_fileset_property quartus_sim TOP_LEVEL $pname
foreach pfile $pfiles {
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile
ad_ip_addfile $pname $pfile
}
set pfile $ftopfile
set pmodule [file tail $pfile]
add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
}
###################################################################################################
###################################################################################################
proc ad_ip_intf_s_axi {aclk arstn} {
add_interface s_axi_clock clock end
@ -157,7 +204,10 @@ proc ad_ip_intf_s_axi {aclk arstn} {
add_interface_port s_axi s_axi_rready rready Input 1
}
proc ad_ip_file {ifile ofile flist} {
###################################################################################################
###################################################################################################
proc ad_ip_modfile {ifile ofile flist} {
global ad_hdl_dir
@ -179,5 +229,10 @@ proc ad_ip_file {ifile ofile flist} {
close $srcfile
close $dstfile
ad_ip_addfile ad_ip_addfile $ofile
}
###################################################################################################
###################################################################################################