pzsdr- name changes
Rejeesh Kutty
parent
0d232a270a
commit
9f8433159f
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# pz-pcie
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS := system_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += system_top.v
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M_DEPS += system_constr.xdc
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../common/rfsom/rfsom_system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../../common/rfsom/rfsom_system_bd.tcl
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M_DEPS += ../../common/xilinx/sys_wfifo.tcl
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M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
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M_DEPS += ../../common/rfsom/rfsom_system_ps7.tcl
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += .Xil
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.PHONY: all lib clean clean-all
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all: lib pzpcie_rfsom.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9361 clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_i2s_adi clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_upack clean
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make -C ../../../library/util_wfifo clean
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pzpcie_rfsom.sdk/system_top.hdf: $(M_DEPS)
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rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> pzpcie_rfsom_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9361
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_i2s_adi
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/util_cpack
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make -C ../../../library/util_upack
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make -C ../../../library/util_wfifo
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####################################################################################
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####################################################################################
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source $ad_hdl_dir/projects/common/rfsom/rfsom_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
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source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl
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source ../common/pzpcie_bd.tcl
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set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
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# constraints
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# ad9361
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## IO_L12P_T1_MRCC_35
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## IO_L12N_T1_MRCC_35
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## IO_L7P_T1_AD2P_35
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set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## IO_L7N_T1_AD2N_35
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## IO_L1P_T0_AD0P_35
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## IO_L1N_T0_AD0N_35
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set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## IO_L2P_T0_AD8P_35
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set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## IO_L2N_T0_AD8N_35
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set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## IO_L3P_T0_DQS_AD1P_35
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set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## IO_L3N_T0_DQS_AD1N_35
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## IO_L4P_T0_35
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## IO_L4N_T0_35
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## IO_L5P_T0_AD9P_35
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set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## IO_L5N_T0_AD9N_35
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## IO_L6P_T0_35
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## IO_L6N_T0_VREF_35
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## IO_L8P_T1_AD10P_35
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## IO_L8N_T1_AD10N_35
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## IO_L9P_T1_DQS_AD3P_35
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## IO_L9N_T1_DQS_AD3N_35
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set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## IO_L13P_T2_MRCC_35
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## IO_L13N_T2_MRCC_35
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## IO_L14P_T2_AD4P_SRCC_35
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## IO_L14N_T2_AD4N_SRCC_35
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## IO_L15P_T2_DQS_AD12P_35
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## IO_L15N_T2_DQS_AD12N_35
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## IO_L16P_T2_35
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## IO_L16N_T2_35
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## IO_L17P_T2_AD5P_35
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L23_13_JX2_N
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set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## IO_L20P_T3_AD6P_35
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set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## IO_L20N_T3_AD6N_35
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## IO_L21P_T3_DQS_AD14P_35
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## IO_L21N_T3_DQS_AD14N_35
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## IO_L22P_T3_AD7P_35
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## IO_L22N_T3_AD7N_35
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set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## IO_L23P_T3_34
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set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## IO_L23N_T3_34
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set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## IO_L24P_T3_34
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set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35
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set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34
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set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## IO_25_VRP_34
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set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS25} [get_ports gpio_rf0] ; ## IO_L20_13_JX2_P
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS25} [get_ports gpio_rf1] ; ## IO_L20_13_JX2_N
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_rf2] ; ## IO_L22_12_JX2_N
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports gpio_rf3] ; ## IO_L05_34_JX4_N
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] ; ## IO_L23P_T3_35
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## IO_L23N_T3_35
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## IO_L24P_T3_AD15P_35
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## IO_L24N_T3_AD15N_35
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# clocks
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create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
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create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_create pzpcie_rfsom
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adi_project_files pzpcie_rfsom [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/rfsom/rfsom_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/rfsom/rfsom_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run pzpcie_rfsom
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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eth1_mdc,
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eth1_mdio,
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eth1_rgmii_rxclk,
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eth1_rgmii_rxctl,
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eth1_rgmii_rxdata,
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eth1_rgmii_txclk,
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|
||||||
eth1_rgmii_txctl,
|
|
||||||
eth1_rgmii_txdata,
|
|
||||||
|
|
||||||
fixed_io_ddr_vrn,
|
|
||||||
fixed_io_ddr_vrp,
|
|
||||||
fixed_io_mio,
|
|
||||||
fixed_io_ps_clk,
|
|
||||||
fixed_io_ps_porb,
|
|
||||||
fixed_io_ps_srstb,
|
|
||||||
|
|
||||||
hdmi_out_clk,
|
|
||||||
hdmi_vsync,
|
|
||||||
hdmi_hsync,
|
|
||||||
hdmi_data_e,
|
|
||||||
hdmi_data,
|
|
||||||
hdmi_pd,
|
|
||||||
hdmi_intn,
|
|
||||||
|
|
||||||
spdif,
|
|
||||||
spdif_in,
|
|
||||||
|
|
||||||
i2s_mclk,
|
|
||||||
i2s_bclk,
|
|
||||||
i2s_lrclk,
|
|
||||||
i2s_sdata_out,
|
|
||||||
i2s_sdata_in,
|
|
||||||
|
|
||||||
iic_scl,
|
|
||||||
iic_sda,
|
|
||||||
|
|
||||||
gpio_bd,
|
|
||||||
|
|
||||||
rx_clk_in_p,
|
|
||||||
rx_clk_in_n,
|
|
||||||
rx_frame_in_p,
|
|
||||||
rx_frame_in_n,
|
|
||||||
rx_data_in_p,
|
|
||||||
rx_data_in_n,
|
|
||||||
tx_clk_out_p,
|
|
||||||
tx_clk_out_n,
|
|
||||||
tx_frame_out_p,
|
|
||||||
tx_frame_out_n,
|
|
||||||
tx_data_out_p,
|
|
||||||
tx_data_out_n,
|
|
||||||
|
|
||||||
enable,
|
|
||||||
txnrx,
|
|
||||||
|
|
||||||
tdd_sync,
|
|
||||||
|
|
||||||
gpio_rf0,
|
|
||||||
gpio_rf1,
|
|
||||||
gpio_rf2,
|
|
||||||
gpio_rf3,
|
|
||||||
gpio_rfpwr_enable,
|
|
||||||
gpio_clksel,
|
|
||||||
gpio_resetb,
|
|
||||||
gpio_sync,
|
|
||||||
gpio_en_agc,
|
|
||||||
gpio_ctl,
|
|
||||||
gpio_status,
|
|
||||||
|
|
||||||
spi_csn,
|
|
||||||
spi_clk,
|
|
||||||
spi_mosi,
|
|
||||||
spi_miso);
|
|
||||||
|
|
||||||
|
|
||||||
inout [14:0] ddr_addr;
|
|
||||||
inout [ 2:0] ddr_ba;
|
|
||||||
inout ddr_cas_n;
|
|
||||||
inout ddr_ck_n;
|
|
||||||
inout ddr_ck_p;
|
|
||||||
inout ddr_cke;
|
|
||||||
inout ddr_cs_n;
|
|
||||||
inout [ 3:0] ddr_dm;
|
|
||||||
inout [31:0] ddr_dq;
|
|
||||||
inout [ 3:0] ddr_dqs_n;
|
|
||||||
inout [ 3:0] ddr_dqs_p;
|
|
||||||
inout ddr_odt;
|
|
||||||
inout ddr_ras_n;
|
|
||||||
inout ddr_reset_n;
|
|
||||||
inout ddr_we_n;
|
|
||||||
|
|
||||||
output eth1_mdc;
|
|
||||||
inout eth1_mdio;
|
|
||||||
input eth1_rgmii_rxclk;
|
|
||||||
input eth1_rgmii_rxctl;
|
|
||||||
input [ 3:0] eth1_rgmii_rxdata;
|
|
||||||
output eth1_rgmii_txclk;
|
|
||||||
output eth1_rgmii_txctl;
|
|
||||||
output [ 3:0] eth1_rgmii_txdata;
|
|
||||||
|
|
||||||
inout fixed_io_ddr_vrn;
|
|
||||||
inout fixed_io_ddr_vrp;
|
|
||||||
inout [53:0] fixed_io_mio;
|
|
||||||
inout fixed_io_ps_clk;
|
|
||||||
inout fixed_io_ps_porb;
|
|
||||||
inout fixed_io_ps_srstb;
|
|
||||||
|
|
||||||
output hdmi_out_clk;
|
|
||||||
output hdmi_vsync;
|
|
||||||
output hdmi_hsync;
|
|
||||||
output hdmi_data_e;
|
|
||||||
output [15:0] hdmi_data;
|
|
||||||
output hdmi_pd;
|
|
||||||
input hdmi_intn;
|
|
||||||
|
|
||||||
output spdif;
|
|
||||||
input spdif_in;
|
|
||||||
|
|
||||||
output i2s_mclk;
|
|
||||||
output i2s_bclk;
|
|
||||||
output i2s_lrclk;
|
|
||||||
output i2s_sdata_out;
|
|
||||||
input i2s_sdata_in;
|
|
||||||
|
|
||||||
inout iic_scl;
|
|
||||||
inout iic_sda;
|
|
||||||
|
|
||||||
inout [11:0] gpio_bd;
|
|
||||||
|
|
||||||
input rx_clk_in_p;
|
|
||||||
input rx_clk_in_n;
|
|
||||||
input rx_frame_in_p;
|
|
||||||
input rx_frame_in_n;
|
|
||||||
input [ 5:0] rx_data_in_p;
|
|
||||||
input [ 5:0] rx_data_in_n;
|
|
||||||
output tx_clk_out_p;
|
|
||||||
output tx_clk_out_n;
|
|
||||||
output tx_frame_out_p;
|
|
||||||
output tx_frame_out_n;
|
|
||||||
output [ 5:0] tx_data_out_p;
|
|
||||||
output [ 5:0] tx_data_out_n;
|
|
||||||
|
|
||||||
output enable;
|
|
||||||
output txnrx;
|
|
||||||
|
|
||||||
inout tdd_sync;
|
|
||||||
|
|
||||||
inout gpio_rf0;
|
|
||||||
inout gpio_rf1;
|
|
||||||
inout gpio_rf2;
|
|
||||||
inout gpio_rf3;
|
|
||||||
inout gpio_rfpwr_enable;
|
|
||||||
inout gpio_clksel;
|
|
||||||
inout gpio_resetb;
|
|
||||||
inout gpio_sync;
|
|
||||||
inout gpio_en_agc;
|
|
||||||
inout [ 3:0] gpio_ctl;
|
|
||||||
inout [ 7:0] gpio_status;
|
|
||||||
|
|
||||||
output spi_csn;
|
|
||||||
output spi_clk;
|
|
||||||
output spi_mosi;
|
|
||||||
input spi_miso;
|
|
||||||
|
|
||||||
|
|
||||||
// internal signals
|
|
||||||
|
|
||||||
wire [63:0] gpio_i;
|
|
||||||
wire [63:0] gpio_o;
|
|
||||||
wire [63:0] gpio_t;
|
|
||||||
|
|
||||||
wire tdd_sync_i;
|
|
||||||
wire tdd_sync_o;
|
|
||||||
wire tdd_sync_t;
|
|
||||||
|
|
||||||
// assignments
|
|
||||||
|
|
||||||
assign hdmi_pd = 1'b0;
|
|
||||||
|
|
||||||
// instantiations
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf (
|
|
||||||
.dio_t ({gpio_t[56:51], gpio_t[46:32]}),
|
|
||||||
.dio_i ({gpio_o[56:51], gpio_o[46:32]}),
|
|
||||||
.dio_o ({gpio_i[56:51], gpio_i[46:32]}),
|
|
||||||
.dio_p ({ gpio_rf0, // 56:56
|
|
||||||
gpio_rf1, // 55:55
|
|
||||||
gpio_rf2, // 54:54
|
|
||||||
gpio_rf3, // 53:53
|
|
||||||
gpio_rfpwr_enable, // 52:52
|
|
||||||
gpio_clksel, // 51:51
|
|
||||||
gpio_resetb, // 46:46
|
|
||||||
gpio_sync, // 45:45
|
|
||||||
gpio_en_agc, // 44:44
|
|
||||||
gpio_ctl, // 43:40
|
|
||||||
gpio_status})); // 39:32
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
|
|
||||||
.dio_t (gpio_t[11:0]),
|
|
||||||
.dio_i (gpio_o[11:0]),
|
|
||||||
.dio_o (gpio_i[11:0]),
|
|
||||||
.dio_p (gpio_bd));
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
|
|
||||||
.dio_t (tdd_sync_t),
|
|
||||||
.dio_i (tdd_sync_o),
|
|
||||||
.dio_o (tdd_sync_i),
|
|
||||||
.dio_p (tdd_sync));
|
|
||||||
|
|
||||||
system_wrapper i_system_wrapper (
|
|
||||||
.ddr_addr (ddr_addr),
|
|
||||||
.ddr_ba (ddr_ba),
|
|
||||||
.ddr_cas_n (ddr_cas_n),
|
|
||||||
.ddr_ck_n (ddr_ck_n),
|
|
||||||
.ddr_ck_p (ddr_ck_p),
|
|
||||||
.ddr_cke (ddr_cke),
|
|
||||||
.ddr_cs_n (ddr_cs_n),
|
|
||||||
.ddr_dm (ddr_dm),
|
|
||||||
.ddr_dq (ddr_dq),
|
|
||||||
.ddr_dqs_n (ddr_dqs_n),
|
|
||||||
.ddr_dqs_p (ddr_dqs_p),
|
|
||||||
.ddr_odt (ddr_odt),
|
|
||||||
.ddr_ras_n (ddr_ras_n),
|
|
||||||
.ddr_reset_n (ddr_reset_n),
|
|
||||||
.ddr_we_n (ddr_we_n),
|
|
||||||
.enable (enable),
|
|
||||||
.eth1_125mclk (),
|
|
||||||
.eth1_25mclk (),
|
|
||||||
.eth1_2m5clk (),
|
|
||||||
.eth1_clock_speed (),
|
|
||||||
.eth1_duplex_status (),
|
|
||||||
.eth1_intn (1'b1),
|
|
||||||
.eth1_link_status (),
|
|
||||||
.eth1_mdio_mdc (eth1_mdc),
|
|
||||||
.eth1_mdio_mdio_io (eth1_mdio),
|
|
||||||
.eth1_refclk (),
|
|
||||||
.eth1_rgmii_rd (eth1_rgmii_rxdata),
|
|
||||||
.eth1_rgmii_rx_ctl (eth1_rgmii_rxctl),
|
|
||||||
.eth1_rgmii_rxc (eth1_rgmii_rxclk),
|
|
||||||
.eth1_rgmii_td (eth1_rgmii_txdata),
|
|
||||||
.eth1_rgmii_tx_ctl (eth1_rgmii_txctl),
|
|
||||||
.eth1_rgmii_txc (eth1_rgmii_txclk),
|
|
||||||
.eth1_speed_mode (),
|
|
||||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
||||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
||||||
.fixed_io_mio (fixed_io_mio),
|
|
||||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
||||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
||||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
||||||
.gpio_i (gpio_i),
|
|
||||||
.gpio_o (gpio_o),
|
|
||||||
.gpio_t (gpio_t),
|
|
||||||
.hdmi_data (hdmi_data),
|
|
||||||
.hdmi_data_e (hdmi_data_e),
|
|
||||||
.hdmi_hsync (hdmi_hsync),
|
|
||||||
.hdmi_out_clk (hdmi_out_clk),
|
|
||||||
.hdmi_vsync (hdmi_vsync),
|
|
||||||
.i2s_bclk (i2s_bclk),
|
|
||||||
.i2s_lrclk (i2s_lrclk),
|
|
||||||
.i2s_mclk (i2s_mclk),
|
|
||||||
.i2s_sdata_in (i2s_sdata_in),
|
|
||||||
.i2s_sdata_out (i2s_sdata_out),
|
|
||||||
.iic_main_scl_io (iic_scl),
|
|
||||||
.iic_main_sda_io (iic_sda),
|
|
||||||
.otg_vbusoc (1'b0),
|
|
||||||
.ps_intr_00 (1'b0),
|
|
||||||
.ps_intr_01 (1'b0),
|
|
||||||
.ps_intr_02 (1'b0),
|
|
||||||
.ps_intr_03 (1'b0),
|
|
||||||
.ps_intr_04 (1'b0),
|
|
||||||
.ps_intr_05 (1'b0),
|
|
||||||
.ps_intr_06 (1'b0),
|
|
||||||
.ps_intr_07 (1'b0),
|
|
||||||
.ps_intr_08 (1'b0),
|
|
||||||
.ps_intr_09 (1'b0),
|
|
||||||
.ps_intr_10 (1'b0),
|
|
||||||
.ps_intr_11 (1'b0),
|
|
||||||
.rx_clk_in_n (rx_clk_in_n),
|
|
||||||
.rx_clk_in_p (rx_clk_in_p),
|
|
||||||
.rx_data_in_n (rx_data_in_n),
|
|
||||||
.rx_data_in_p (rx_data_in_p),
|
|
||||||
.rx_frame_in_n (rx_frame_in_n),
|
|
||||||
.rx_frame_in_p (rx_frame_in_p),
|
|
||||||
.spdif (spdif),
|
|
||||||
.spi0_clk_i (1'b0),
|
|
||||||
.spi0_clk_o (spi_clk),
|
|
||||||
.spi0_csn_0_o (spi_csn),
|
|
||||||
.spi0_csn_1_o (),
|
|
||||||
.spi0_csn_2_o (),
|
|
||||||
.spi0_csn_i (1'b1),
|
|
||||||
.spi0_sdi_i (spi_miso),
|
|
||||||
.spi0_sdo_i (1'b0),
|
|
||||||
.spi0_sdo_o (spi_mosi),
|
|
||||||
.spi1_clk_i (1'b0),
|
|
||||||
.spi1_clk_o (),
|
|
||||||
.spi1_csn_0_o (),
|
|
||||||
.spi1_csn_1_o (),
|
|
||||||
.spi1_csn_2_o (),
|
|
||||||
.spi1_csn_i (1'b1),
|
|
||||||
.spi1_sdi_i (1'b0),
|
|
||||||
.spi1_sdo_i (1'b0),
|
|
||||||
.spi1_sdo_o (),
|
|
||||||
.tdd_sync_i (tdd_sync_i),
|
|
||||||
.tdd_sync_o (tdd_sync_o),
|
|
||||||
.tdd_sync_t (tdd_sync_t),
|
|
||||||
.tx_clk_out_n (tx_clk_out_n),
|
|
||||||
.tx_clk_out_p (tx_clk_out_p),
|
|
||||||
.tx_data_out_n (tx_data_out_n),
|
|
||||||
.tx_data_out_p (tx_data_out_p),
|
|
||||||
.tx_frame_out_n (tx_frame_out_n),
|
|
||||||
.tx_frame_out_p (tx_frame_out_p),
|
|
||||||
.txnrx (txnrx),
|
|
||||||
.up_enable (gpio_o[47]),
|
|
||||||
.up_txnrx (gpio_o[48]));
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
|
|
@ -1,140 +0,0 @@
|
||||||
|
|
||||||
# lbfmc
|
|
||||||
|
|
||||||
set axi_gpio_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0]
|
|
||||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_0
|
|
||||||
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_0_0_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_0_0_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_0_0_t
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_0_1_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_0_1_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_0_1_t
|
|
||||||
|
|
||||||
ad_connect gpio_0_0_i axi_gpio_0/gpio_io_i
|
|
||||||
ad_connect gpio_0_0_o axi_gpio_0/gpio_io_o
|
|
||||||
ad_connect gpio_0_0_t axi_gpio_0/gpio_io_t
|
|
||||||
ad_connect gpio_0_1_i axi_gpio_0/gpio2_io_i
|
|
||||||
ad_connect gpio_0_1_o axi_gpio_0/gpio2_io_o
|
|
||||||
ad_connect gpio_0_1_t axi_gpio_0/gpio2_io_t
|
|
||||||
|
|
||||||
set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
|
|
||||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_1
|
|
||||||
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_1_0_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_1_0_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_1_0_t
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_1_1_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_1_1_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_1_1_t
|
|
||||||
|
|
||||||
ad_connect gpio_1_0_i axi_gpio_1/gpio_io_i
|
|
||||||
ad_connect gpio_1_0_o axi_gpio_1/gpio_io_o
|
|
||||||
ad_connect gpio_1_0_t axi_gpio_1/gpio_io_t
|
|
||||||
ad_connect gpio_1_1_i axi_gpio_1/gpio2_io_i
|
|
||||||
ad_connect gpio_1_1_o axi_gpio_1/gpio2_io_o
|
|
||||||
ad_connect gpio_1_1_t axi_gpio_1/gpio2_io_t
|
|
||||||
|
|
||||||
set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
|
|
||||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
|
|
||||||
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_2_0_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_2_0_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_2_0_t
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_2_1_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_2_1_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_2_1_t
|
|
||||||
|
|
||||||
ad_connect gpio_2_0_i axi_gpio_2/gpio_io_i
|
|
||||||
ad_connect gpio_2_0_o axi_gpio_2/gpio_io_o
|
|
||||||
ad_connect gpio_2_0_t axi_gpio_2/gpio_io_t
|
|
||||||
ad_connect gpio_2_1_i axi_gpio_2/gpio2_io_i
|
|
||||||
ad_connect gpio_2_1_o axi_gpio_2/gpio2_io_o
|
|
||||||
ad_connect gpio_2_1_t axi_gpio_2/gpio2_io_t
|
|
||||||
|
|
||||||
set axi_gpio_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_3]
|
|
||||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_3
|
|
||||||
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_3_0_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_3_0_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_3_0_t
|
|
||||||
create_bd_port -dir I -from 31 -to 0 gpio_3_1_i
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_3_1_o
|
|
||||||
create_bd_port -dir O -from 31 -to 0 gpio_3_1_t
|
|
||||||
|
|
||||||
ad_connect gpio_3_0_i axi_gpio_3/gpio_io_i
|
|
||||||
ad_connect gpio_3_0_o axi_gpio_3/gpio_io_o
|
|
||||||
ad_connect gpio_3_0_t axi_gpio_3/gpio_io_t
|
|
||||||
ad_connect gpio_3_1_i axi_gpio_3/gpio2_io_i
|
|
||||||
ad_connect gpio_3_1_o axi_gpio_3/gpio2_io_o
|
|
||||||
ad_connect gpio_3_1_t axi_gpio_3/gpio2_io_t
|
|
||||||
|
|
||||||
set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
|
|
||||||
set_property -dict [list CONFIG.NUM_OF_LANES {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.RX_NUM_OF_LANES {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.TX_NUM_OF_LANES {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
|
|
||||||
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
|
|
||||||
|
|
||||||
set util_pzslb_gtlb [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb]
|
|
||||||
|
|
||||||
create_bd_port -dir I fmc_gt_ref_clk0
|
|
||||||
create_bd_port -dir I fmc_gt_ref_clk1
|
|
||||||
create_bd_port -dir I fmc_gt_rx_p
|
|
||||||
create_bd_port -dir I fmc_gt_rx_n
|
|
||||||
create_bd_port -dir O fmc_gt_tx_p
|
|
||||||
create_bd_port -dir O fmc_gt_tx_n
|
|
||||||
|
|
||||||
ad_connect sys_cpu_clk util_pzslb_gtlb/up_clk
|
|
||||||
ad_connect sys_cpu_resetn util_pzslb_gtlb/up_rstn
|
|
||||||
ad_connect util_pzslb_gtlb/qpll_ref_clk fmc_gt_ref_clk0
|
|
||||||
ad_connect util_pzslb_gtlb/cpll_ref_clk fmc_gt_ref_clk1
|
|
||||||
ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb/gt_qpll_0
|
|
||||||
ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb/gt_pll_0
|
|
||||||
ad_connect util_pzslb_gtlb/rx_p fmc_gt_rx_p
|
|
||||||
ad_connect util_pzslb_gtlb/rx_n fmc_gt_rx_n
|
|
||||||
ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb/gt_rx_0
|
|
||||||
ad_connect util_pzslb_gtlb/tx_p fmc_gt_tx_p
|
|
||||||
ad_connect util_pzslb_gtlb/tx_n fmc_gt_tx_n
|
|
||||||
ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb/gt_tx_0
|
|
||||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb/rx_gt_comma_align_enb_0
|
|
||||||
ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb/gt_rx_ip_0
|
|
||||||
ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb/gt_tx_ip_0
|
|
||||||
|
|
||||||
ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
|
|
||||||
|
|
||||||
ad_cpu_interconnect 0x41200000 axi_gpio_0
|
|
||||||
ad_cpu_interconnect 0x41210000 axi_gpio_1
|
|
||||||
ad_cpu_interconnect 0x41220000 axi_gpio_2
|
|
||||||
ad_cpu_interconnect 0x41230000 axi_gpio_3
|
|
||||||
|
|
||||||
create_bd_port -dir O up_clk
|
|
||||||
create_bd_port -dir O up_rst
|
|
||||||
create_bd_port -dir O up_rstn
|
|
||||||
create_bd_port -dir I up_pn_err_clr
|
|
||||||
create_bd_port -dir I up_pn_oos_clr
|
|
||||||
create_bd_port -dir O up_pn_err
|
|
||||||
create_bd_port -dir O up_pn_oos
|
|
||||||
|
|
||||||
ad_connect sys_cpu_clk up_clk
|
|
||||||
ad_connect sys_cpu_reset up_rst
|
|
||||||
ad_connect sys_cpu_resetn up_rstn
|
|
||||||
ad_connect up_pn_err_clr util_pzslb_gtlb/up_pn_err_clr
|
|
||||||
ad_connect up_pn_oos_clr util_pzslb_gtlb/up_pn_oos_clr
|
|
||||||
ad_connect up_pn_err util_pzslb_gtlb/up_pn_err
|
|
||||||
ad_connect up_pn_oos util_pzslb_gtlb/up_pn_oos
|
|
||||||
|
|
||||||
delete_bd_objs [get_bd_cells ila_adc]
|
|
||||||
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
|
|
||||||
|
|
||||||
|
|
@ -1,52 +0,0 @@
|
||||||
####################################################################################
|
|
||||||
####################################################################################
|
|
||||||
## Copyright 2011(c) Analog Devices, Inc.
|
|
||||||
## Auto-generated, do not modify!
|
|
||||||
####################################################################################
|
|
||||||
####################################################################################
|
|
||||||
|
|
||||||
M_DEPS := system_project.tcl
|
|
||||||
M_DEPS += ../../scripts/adi_env.tcl-notrace
|
|
||||||
M_DEPS += ../../scripts/adi_project.tcl-notrace
|
|
||||||
M_DEPS += ../../scripts/adi_board.tcl-notrace
|
|
||||||
M_DEPS += system_top.v
|
|
||||||
M_DEPS += system_constr.xdc
|
|
||||||
M_DEPS += ../../../library/common/ad_iobuf.v
|
|
||||||
M_DEPS += ../../pzsdr/rfsom/system_constr.xdc
|
|
||||||
M_DEPS += ../../common/rfsom/rfsom_system_constr.xdc
|
|
||||||
|
|
||||||
M_VIVADO := vivado -mode batch -source
|
|
||||||
|
|
||||||
M_FLIST := *.cache
|
|
||||||
M_FLIST += *.data
|
|
||||||
M_FLIST += *.xpr
|
|
||||||
M_FLIST += *.log
|
|
||||||
M_FLIST += *.jou
|
|
||||||
M_FLIST += xgui
|
|
||||||
M_FLIST += *.runs
|
|
||||||
M_FLIST += *.srcs
|
|
||||||
M_FLIST += *.sdk
|
|
||||||
M_FLIST += .Xil
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
.PHONY: all lib clean clean-all
|
|
||||||
all: lib pzslb_rfsom.sdk/system_top.hdf
|
|
||||||
|
|
||||||
|
|
||||||
clean:
|
|
||||||
rm -rf $(M_FLIST)
|
|
||||||
|
|
||||||
|
|
||||||
clean-all:clean
|
|
||||||
|
|
||||||
|
|
||||||
pzslb_rfsom.sdk/system_top.hdf: $(M_DEPS)
|
|
||||||
rm -rf $(M_FLIST)
|
|
||||||
$(M_VIVADO) system_project.tcl >> pzslb_rfsom_vivado.log 2>&1
|
|
||||||
|
|
||||||
|
|
||||||
lib:
|
|
||||||
|
|
||||||
####################################################################################
|
|
||||||
####################################################################################
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
|
|
||||||
source $ad_hdl_dir/projects/common/rfsom/rfsom_system_bd.tcl -notrace
|
|
||||||
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl -notrace
|
|
||||||
source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl -notrace
|
|
||||||
source ../common/pzslb_bd.tcl -notrace
|
|
||||||
|
|
||||||
set_property -dict [list CONFIG.DAC_IODELAY_ENABLE {1}] $axi_ad9361
|
|
||||||
|
|
||||||
|
|
@ -1,107 +0,0 @@
|
||||||
|
|
||||||
# constraints
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_p] ; ## IO_L13P_T2_MRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk0_n] ; ## IO_L13N_T2_MRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_p] ; ## IO_L13P_T2_MRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports fmc_clk1_n] ; ## IO_L13N_T2_MRCC_13
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports fmc_prstn] ; ## IO_25_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[0]] ; ## IO_L12P_T1_MRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[0]] ; ## IO_L12N_T1_MRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[1]] ; ## IO_L11P_T1_SRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[1]] ; ## IO_L11N_T1_SRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[2]] ; ## IO_L1P_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[2]] ; ## IO_L1N_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[3]] ; ## IO_L2P_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[3]] ; ## IO_L2N_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[4]] ; ## IO_L3P_T0_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[4]] ; ## IO_L3N_T0_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[5]] ; ## IO_L4P_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[5]] ; ## IO_L4N_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[6]] ; ## IO_L5P_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[6]] ; ## IO_L5N_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[7]] ; ## IO_L6P_T0_12
|
|
||||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[7]] ; ## IO_L6N_T0_VREF_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[8]] ; ## IO_L7P_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[8]] ; ## IO_L7N_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[9]] ; ## IO_L8P_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[9]] ; ## IO_L8N_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[10]] ; ## IO_L9P_T1_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[10]] ; ## IO_L9N_T1_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[11]] ; ## IO_L10P_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[11]] ; ## IO_L10N_T1_12
|
|
||||||
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[12]] ; ## IO_L14P_T2_SRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[12]] ; ## IO_L14N_T2_SRCC_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[13]] ; ## IO_L15P_T2_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[13]] ; ## IO_L15N_T2_DQS_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[14]] ; ## IO_L16P_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[14]] ; ## IO_L16N_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[15]] ; ## IO_L17P_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[15]] ; ## IO_L17N_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[16]] ; ## IO_L18P_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[16]] ; ## IO_L18N_T2_12
|
|
||||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[17]] ; ## IO_L12P_T1_MRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[17]] ; ## IO_L12N_T1_MRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[18]] ; ## IO_L11P_T1_SRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[18]] ; ## IO_L11N_T1_SRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[19]] ; ## IO_L1P_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[19]] ; ## IO_L1N_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[20]] ; ## IO_L2P_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[20]] ; ## IO_L2N_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[21]] ; ## IO_L3P_T0_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[21]] ; ## IO_L3N_T0_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[22]] ; ## IO_L4P_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[22]] ; ## IO_L4N_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[23]] ; ## IO_L6P_T0_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[23]] ; ## IO_L6N_T0_VREF_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[24]] ; ## IO_L7P_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[24]] ; ## IO_L7N_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[25]] ; ## IO_L8P_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[25]] ; ## IO_L8N_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[26]] ; ## IO_L9P_T1_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[26]] ; ## IO_L9N_T1_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[27]] ; ## IO_L10P_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[27]] ; ## IO_L10N_T1_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[28]] ; ## IO_L14P_T2_SRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[28]] ; ## IO_L14N_T2_SRCC_13
|
|
||||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[29]] ; ## IO_L15P_T2_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[29]] ; ## IO_L15N_T2_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[30]] ; ## IO_L16P_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[30]] ; ## IO_L16N_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[31]] ; ## IO_L17P_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[31]] ; ## IO_L17N_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[32]] ; ## IO_L18P_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[32]] ; ## IO_L18N_T2_13
|
|
||||||
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports fmc_la_p[33]] ; ## IO_L19P_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports fmc_la_n[33]] ; ## IO_L19N_T3_VREF_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports pmod0[0]] ; ## IO_L21P_T3_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports pmod0[1]] ; ## IO_L21N_T3_DQS_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports pmod0[2]] ; ## IO_L22P_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports pmod0[3]] ; ## IO_L22N_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports pmod0[4]] ; ## IO_L23P_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports pmod0[5]] ; ## IO_L23N_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports pmod0[6]] ; ## IO_L24P_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports pmod0[7]] ; ## IO_L24N_T3_13
|
|
||||||
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports pmod1[0]] ; ## IO_L19P_T3_34
|
|
||||||
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports pmod1[1]] ; ## IO_L19N_T3_VREF_34
|
|
||||||
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports pmod1[2]] ; ## IO_L20P_T3_34
|
|
||||||
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmod1[3]] ; ## IO_L20N_T3_34
|
|
||||||
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports pmod1[4]] ; ## IO_L21P_T3_DQS_34
|
|
||||||
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports pmod1[5]] ; ## IO_L21N_T3_DQS_34
|
|
||||||
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports pmod1[6]] ; ## IO_L22P_T3_34
|
|
||||||
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports pmod1[7]] ; ## IO_L22N_T3_34
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN W6} [get_ports fmc_gt_ref_clk_p] ; ## MGTREFCLK0P_111
|
|
||||||
set_property -dict {PACKAGE_PIN W5} [get_ports fmc_gt_ref_clk_n] ; ## MGTREFCLK0N_111
|
|
||||||
set_property -dict {PACKAGE_PIN AF8} [get_ports fmc_gt_tx_p] ; ## MGTXTXP0_111
|
|
||||||
set_property -dict {PACKAGE_PIN AF7} [get_ports fmc_gt_tx_n] ; ## MGTXTXN0_111
|
|
||||||
set_property -dict {PACKAGE_PIN AD8} [get_ports fmc_gt_rx_p] ; ## MGTXRXP0_111
|
|
||||||
set_property -dict {PACKAGE_PIN AD7} [get_ports fmc_gt_rx_n] ; ## MGTXRXN0_111
|
|
||||||
|
|
||||||
# clocks
|
|
||||||
|
|
||||||
create_clock -name ref_clk -period 4.00 [get_ports fmc_gt_ref_clk_p]
|
|
||||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
|
||||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
|
||||||
|
|
||||||
|
|
@ -1,22 +0,0 @@
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
source ../../scripts/adi_env.tcl -notrace
|
|
||||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl -notrace
|
|
||||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl -notrace
|
|
||||||
|
|
||||||
adi_project_create pzslb_rfsom
|
|
||||||
adi_project_files pzslb_rfsom [list \
|
|
||||||
"system_top.v" \
|
|
||||||
"system_constr.xdc"\
|
|
||||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
|
||||||
"$ad_hdl_dir/projects/pzsdr/rfsom/system_constr.xdc" \
|
|
||||||
"$ad_hdl_dir/projects/common/rfsom/rfsom_system_constr.xdc" ]
|
|
||||||
|
|
||||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/rfsom/rfsom_system_constr.xdc]
|
|
||||||
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/pzsdr/rfsom/system_constr.xdc]
|
|
||||||
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
|
|
||||||
|
|
||||||
adi_project_run pzslb_rfsom
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,530 +0,0 @@
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
// Copyright 2011(c) Analog Devices, Inc.
|
|
||||||
//
|
|
||||||
// All rights reserved.
|
|
||||||
//
|
|
||||||
// Redistribution and use in source and binary forms, with or without modification,
|
|
||||||
// are permitted provided that the following conditions are met:
|
|
||||||
// - Redistributions of source code must retain the above copyright
|
|
||||||
// notice, this list of conditions and the following disclaimer.
|
|
||||||
// - Redistributions in binary form must reproduce the above copyright
|
|
||||||
// notice, this list of conditions and the following disclaimer in
|
|
||||||
// the documentation and/or other materials provided with the
|
|
||||||
// distribution.
|
|
||||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
|
||||||
// contributors may be used to endorse or promote products derived
|
|
||||||
// from this software without specific prior written permission.
|
|
||||||
// - The use of this software may or may not infringe the patent rights
|
|
||||||
// of one or more patent holders. This license does not release you
|
|
||||||
// from the requirement that you obtain separate licenses from these
|
|
||||||
// patent holders to use this software.
|
|
||||||
// - Use of the software either in source or binary form, must be run
|
|
||||||
// on or directly connected to an Analog Devices Inc. component.
|
|
||||||
//
|
|
||||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
|
||||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
|
||||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
|
||||||
//
|
|
||||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
|
||||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
|
||||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
|
||||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
|
||||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
|
||||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
|
|
||||||
`timescale 1ns/100ps
|
|
||||||
|
|
||||||
module system_top (
|
|
||||||
|
|
||||||
ddr_addr,
|
|
||||||
ddr_ba,
|
|
||||||
ddr_cas_n,
|
|
||||||
ddr_ck_n,
|
|
||||||
ddr_ck_p,
|
|
||||||
ddr_cke,
|
|
||||||
ddr_cs_n,
|
|
||||||
ddr_dm,
|
|
||||||
ddr_dq,
|
|
||||||
ddr_dqs_n,
|
|
||||||
ddr_dqs_p,
|
|
||||||
ddr_odt,
|
|
||||||
ddr_ras_n,
|
|
||||||
ddr_reset_n,
|
|
||||||
ddr_we_n,
|
|
||||||
|
|
||||||
eth1_mdc,
|
|
||||||
eth1_mdio,
|
|
||||||
eth1_rgmii_rxclk,
|
|
||||||
eth1_rgmii_rxctl,
|
|
||||||
eth1_rgmii_rxdata,
|
|
||||||
eth1_rgmii_txclk,
|
|
||||||
eth1_rgmii_txctl,
|
|
||||||
eth1_rgmii_txdata,
|
|
||||||
|
|
||||||
fixed_io_ddr_vrn,
|
|
||||||
fixed_io_ddr_vrp,
|
|
||||||
fixed_io_mio,
|
|
||||||
fixed_io_ps_clk,
|
|
||||||
fixed_io_ps_porb,
|
|
||||||
fixed_io_ps_srstb,
|
|
||||||
|
|
||||||
hdmi_out_clk,
|
|
||||||
hdmi_vsync,
|
|
||||||
hdmi_hsync,
|
|
||||||
hdmi_data_e,
|
|
||||||
hdmi_data,
|
|
||||||
hdmi_pd,
|
|
||||||
hdmi_intn,
|
|
||||||
|
|
||||||
spdif,
|
|
||||||
spdif_in,
|
|
||||||
|
|
||||||
i2s_mclk,
|
|
||||||
i2s_bclk,
|
|
||||||
i2s_lrclk,
|
|
||||||
i2s_sdata_out,
|
|
||||||
i2s_sdata_in,
|
|
||||||
|
|
||||||
iic_scl,
|
|
||||||
iic_sda,
|
|
||||||
|
|
||||||
gpio_bd,
|
|
||||||
|
|
||||||
rx_clk_in_p,
|
|
||||||
rx_clk_in_n,
|
|
||||||
rx_frame_in_p,
|
|
||||||
rx_frame_in_n,
|
|
||||||
rx_data_in_p,
|
|
||||||
rx_data_in_n,
|
|
||||||
tx_clk_out_p,
|
|
||||||
tx_clk_out_n,
|
|
||||||
tx_frame_out_p,
|
|
||||||
tx_frame_out_n,
|
|
||||||
tx_data_out_p,
|
|
||||||
tx_data_out_n,
|
|
||||||
|
|
||||||
enable,
|
|
||||||
txnrx,
|
|
||||||
|
|
||||||
gpio_rf0,
|
|
||||||
gpio_rf1,
|
|
||||||
gpio_rf2,
|
|
||||||
gpio_rf3,
|
|
||||||
gpio_rfpwr_enable,
|
|
||||||
gpio_clksel,
|
|
||||||
gpio_resetb,
|
|
||||||
gpio_sync,
|
|
||||||
gpio_en_agc,
|
|
||||||
gpio_ctl,
|
|
||||||
gpio_status,
|
|
||||||
|
|
||||||
spi_csn,
|
|
||||||
spi_clk,
|
|
||||||
spi_mosi,
|
|
||||||
spi_miso,
|
|
||||||
|
|
||||||
fmc_prstn,
|
|
||||||
fmc_clk0_p,
|
|
||||||
fmc_clk0_n,
|
|
||||||
fmc_clk1_p,
|
|
||||||
fmc_clk1_n,
|
|
||||||
fmc_la_p,
|
|
||||||
fmc_la_n,
|
|
||||||
pmod0,
|
|
||||||
pmod1,
|
|
||||||
|
|
||||||
fmc_gt_ref_clk_p,
|
|
||||||
fmc_gt_ref_clk_n,
|
|
||||||
fmc_gt_tx_p,
|
|
||||||
fmc_gt_tx_n,
|
|
||||||
fmc_gt_rx_p,
|
|
||||||
fmc_gt_rx_n);
|
|
||||||
|
|
||||||
inout [14:0] ddr_addr;
|
|
||||||
inout [ 2:0] ddr_ba;
|
|
||||||
inout ddr_cas_n;
|
|
||||||
inout ddr_ck_n;
|
|
||||||
inout ddr_ck_p;
|
|
||||||
inout ddr_cke;
|
|
||||||
inout ddr_cs_n;
|
|
||||||
inout [ 3:0] ddr_dm;
|
|
||||||
inout [31:0] ddr_dq;
|
|
||||||
inout [ 3:0] ddr_dqs_n;
|
|
||||||
inout [ 3:0] ddr_dqs_p;
|
|
||||||
inout ddr_odt;
|
|
||||||
inout ddr_ras_n;
|
|
||||||
inout ddr_reset_n;
|
|
||||||
inout ddr_we_n;
|
|
||||||
|
|
||||||
output eth1_mdc;
|
|
||||||
inout eth1_mdio;
|
|
||||||
input eth1_rgmii_rxclk;
|
|
||||||
input eth1_rgmii_rxctl;
|
|
||||||
input [ 3:0] eth1_rgmii_rxdata;
|
|
||||||
output eth1_rgmii_txclk;
|
|
||||||
output eth1_rgmii_txctl;
|
|
||||||
output [ 3:0] eth1_rgmii_txdata;
|
|
||||||
|
|
||||||
inout fixed_io_ddr_vrn;
|
|
||||||
inout fixed_io_ddr_vrp;
|
|
||||||
inout [53:0] fixed_io_mio;
|
|
||||||
inout fixed_io_ps_clk;
|
|
||||||
inout fixed_io_ps_porb;
|
|
||||||
inout fixed_io_ps_srstb;
|
|
||||||
|
|
||||||
output hdmi_out_clk;
|
|
||||||
output hdmi_vsync;
|
|
||||||
output hdmi_hsync;
|
|
||||||
output hdmi_data_e;
|
|
||||||
output [15:0] hdmi_data;
|
|
||||||
output hdmi_pd;
|
|
||||||
input hdmi_intn;
|
|
||||||
|
|
||||||
output spdif;
|
|
||||||
input spdif_in;
|
|
||||||
|
|
||||||
output i2s_mclk;
|
|
||||||
output i2s_bclk;
|
|
||||||
output i2s_lrclk;
|
|
||||||
output i2s_sdata_out;
|
|
||||||
input i2s_sdata_in;
|
|
||||||
|
|
||||||
inout iic_scl;
|
|
||||||
inout iic_sda;
|
|
||||||
|
|
||||||
inout [11:0] gpio_bd;
|
|
||||||
|
|
||||||
input rx_clk_in_p;
|
|
||||||
input rx_clk_in_n;
|
|
||||||
input rx_frame_in_p;
|
|
||||||
input rx_frame_in_n;
|
|
||||||
input [ 5:0] rx_data_in_p;
|
|
||||||
input [ 5:0] rx_data_in_n;
|
|
||||||
output tx_clk_out_p;
|
|
||||||
output tx_clk_out_n;
|
|
||||||
output tx_frame_out_p;
|
|
||||||
output tx_frame_out_n;
|
|
||||||
output [ 5:0] tx_data_out_p;
|
|
||||||
output [ 5:0] tx_data_out_n;
|
|
||||||
|
|
||||||
output enable;
|
|
||||||
output txnrx;
|
|
||||||
|
|
||||||
inout gpio_rf0;
|
|
||||||
inout gpio_rf1;
|
|
||||||
inout gpio_rf2;
|
|
||||||
inout gpio_rf3;
|
|
||||||
inout gpio_rfpwr_enable;
|
|
||||||
inout gpio_clksel;
|
|
||||||
inout gpio_resetb;
|
|
||||||
inout gpio_sync;
|
|
||||||
inout gpio_en_agc;
|
|
||||||
inout [ 3:0] gpio_ctl;
|
|
||||||
inout [ 7:0] gpio_status;
|
|
||||||
|
|
||||||
output spi_csn;
|
|
||||||
output spi_clk;
|
|
||||||
output spi_mosi;
|
|
||||||
input spi_miso;
|
|
||||||
|
|
||||||
input fmc_prstn;
|
|
||||||
input fmc_clk0_p;
|
|
||||||
input fmc_clk0_n;
|
|
||||||
input fmc_clk1_p;
|
|
||||||
input fmc_clk1_n;
|
|
||||||
inout [33:0] fmc_la_p;
|
|
||||||
inout [33:0] fmc_la_n;
|
|
||||||
inout [ 7:0] pmod0;
|
|
||||||
inout [ 7:0] pmod1;
|
|
||||||
|
|
||||||
input fmc_gt_ref_clk_p;
|
|
||||||
input fmc_gt_ref_clk_n;
|
|
||||||
output fmc_gt_tx_p;
|
|
||||||
output fmc_gt_tx_n;
|
|
||||||
input fmc_gt_rx_p;
|
|
||||||
input fmc_gt_rx_n;
|
|
||||||
|
|
||||||
// internal signals
|
|
||||||
|
|
||||||
wire fmc_clk0_s;
|
|
||||||
wire fmc_clk0;
|
|
||||||
wire [31:0] up_clk0_count;
|
|
||||||
wire fmc_clk1_s;
|
|
||||||
wire fmc_clk1;
|
|
||||||
wire [31:0] up_clk1_count;
|
|
||||||
wire fmc_gt_ref_clk;
|
|
||||||
wire [31:0] gpio_0_0_i;
|
|
||||||
wire [31:0] gpio_0_0_o;
|
|
||||||
wire [31:0] gpio_0_0_t;
|
|
||||||
wire [31:0] gpio_0_1_i;
|
|
||||||
wire [31:0] gpio_0_1_o;
|
|
||||||
wire [31:0] gpio_0_1_t;
|
|
||||||
wire [31:0] gpio_1_0_i;
|
|
||||||
wire [31:0] gpio_1_0_o;
|
|
||||||
wire [31:0] gpio_1_0_t;
|
|
||||||
wire [31:0] gpio_1_1_i;
|
|
||||||
wire [31:0] gpio_1_1_o;
|
|
||||||
wire [31:0] gpio_1_1_t;
|
|
||||||
wire [31:0] gpio_3_1_o;
|
|
||||||
wire [63:0] gpio_i;
|
|
||||||
wire [63:0] gpio_o;
|
|
||||||
wire [63:0] gpio_t;
|
|
||||||
wire up_clk;
|
|
||||||
wire up_rst;
|
|
||||||
wire up_rstn;
|
|
||||||
wire up_pn_err_clr;
|
|
||||||
wire up_pn_oos_clr;
|
|
||||||
wire up_pn_err;
|
|
||||||
wire up_pn_oos;
|
|
||||||
|
|
||||||
// assignments
|
|
||||||
|
|
||||||
assign hdmi_pd = 1'b0;
|
|
||||||
|
|
||||||
// instantiations
|
|
||||||
|
|
||||||
IBUFDS i_ibufds_clk0 (
|
|
||||||
.I (fmc_clk0_p),
|
|
||||||
.IB (fmc_clk0_n),
|
|
||||||
.O (fmc_clk0_s));
|
|
||||||
|
|
||||||
BUFG i_bufg_clk0 (
|
|
||||||
.I (fmc_clk0_s),
|
|
||||||
.O (fmc_clk0));
|
|
||||||
|
|
||||||
up_clock_mon i_clk0_mon (
|
|
||||||
.up_rstn (up_rstn),
|
|
||||||
.up_clk (up_clk),
|
|
||||||
.up_d_count (up_clk0_count),
|
|
||||||
.d_rst (up_rst),
|
|
||||||
.d_clk (fmc_clk0));
|
|
||||||
|
|
||||||
IBUFDS i_ibufds_clk1 (
|
|
||||||
.I (fmc_clk1_p),
|
|
||||||
.IB (fmc_clk1_n),
|
|
||||||
.O (fmc_clk1_s));
|
|
||||||
|
|
||||||
BUFG i_bufg_clk1 (
|
|
||||||
.I (fmc_clk1_s),
|
|
||||||
.O (fmc_clk1));
|
|
||||||
|
|
||||||
up_clock_mon i_clk1_mon (
|
|
||||||
.up_rstn (up_rstn),
|
|
||||||
.up_clk (up_clk),
|
|
||||||
.up_d_count (up_clk1_count),
|
|
||||||
.d_rst (up_rst),
|
|
||||||
.d_clk (fmc_clk1));
|
|
||||||
|
|
||||||
IBUFDS_GTE2 i_ibufds_ref_clk (
|
|
||||||
.CEB (1'd0),
|
|
||||||
.I (fmc_gt_ref_clk_p),
|
|
||||||
.IB (fmc_gt_ref_clk_n),
|
|
||||||
.O (fmc_gt_ref_clk),
|
|
||||||
.ODIV2 ());
|
|
||||||
|
|
||||||
assign gpio_0_1_i[31:10] = 'd0;
|
|
||||||
assign gpio_1_1_i[31:10] = 'd0;
|
|
||||||
assign up_pn_err_clr = gpio_3_1_o[1];
|
|
||||||
assign up_pn_oos_clr = gpio_3_1_o[0];
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod0_fmc_p (
|
|
||||||
.dio_t ({gpio_0_1_t[9:0], gpio_0_0_t[31:0]}),
|
|
||||||
.dio_i ({gpio_0_1_o[9:0], gpio_0_0_o[31:0]}),
|
|
||||||
.dio_o ({gpio_0_1_i[9:0], gpio_0_0_i[31:0]}),
|
|
||||||
.dio_p ({ pmod1[3],
|
|
||||||
pmod1[2],
|
|
||||||
pmod1[1],
|
|
||||||
pmod1[0],
|
|
||||||
pmod0[3],
|
|
||||||
pmod0[2],
|
|
||||||
pmod0[1],
|
|
||||||
pmod0[0],
|
|
||||||
fmc_la_n[16:0],
|
|
||||||
fmc_la_p[16:0]}));
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(42)) i_iobuf_pmod1_fmc_n (
|
|
||||||
.dio_t ({gpio_1_1_t[9:0], gpio_1_0_t[31:0]}),
|
|
||||||
.dio_i ({gpio_1_1_o[9:0], gpio_1_0_o[31:0]}),
|
|
||||||
.dio_o ({gpio_1_1_i[9:0], gpio_1_0_i[31:0]}),
|
|
||||||
.dio_p ({ pmod1[7],
|
|
||||||
pmod1[6],
|
|
||||||
pmod1[5],
|
|
||||||
pmod1[4],
|
|
||||||
pmod0[7],
|
|
||||||
pmod0[6],
|
|
||||||
pmod0[5],
|
|
||||||
pmod0[4],
|
|
||||||
fmc_la_n[33:17],
|
|
||||||
fmc_la_p[33:17]}));
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf (
|
|
||||||
.dio_t ({gpio_t[56:51], gpio_t[46:32]}),
|
|
||||||
.dio_i ({gpio_o[56:51], gpio_o[46:32]}),
|
|
||||||
.dio_o ({gpio_i[56:51], gpio_i[46:32]}),
|
|
||||||
.dio_p ({ gpio_rf0, // 56:56
|
|
||||||
gpio_rf1, // 55:55
|
|
||||||
gpio_rf2, // 54:54
|
|
||||||
gpio_rf3, // 53:53
|
|
||||||
gpio_rfpwr_enable, // 52:52
|
|
||||||
gpio_clksel, // 51:51
|
|
||||||
gpio_resetb, // 46:46
|
|
||||||
gpio_sync, // 45:45
|
|
||||||
gpio_en_agc, // 44:44
|
|
||||||
gpio_ctl, // 43:40
|
|
||||||
gpio_status})); // 39:32
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd (
|
|
||||||
.dio_t (gpio_t[11:0]),
|
|
||||||
.dio_i (gpio_o[11:0]),
|
|
||||||
.dio_o (gpio_i[11:0]),
|
|
||||||
.dio_p (gpio_bd));
|
|
||||||
|
|
||||||
system_wrapper i_system_wrapper (
|
|
||||||
.ddr_addr (ddr_addr),
|
|
||||||
.ddr_ba (ddr_ba),
|
|
||||||
.ddr_cas_n (ddr_cas_n),
|
|
||||||
.ddr_ck_n (ddr_ck_n),
|
|
||||||
.ddr_ck_p (ddr_ck_p),
|
|
||||||
.ddr_cke (ddr_cke),
|
|
||||||
.ddr_cs_n (ddr_cs_n),
|
|
||||||
.ddr_dm (ddr_dm),
|
|
||||||
.ddr_dq (ddr_dq),
|
|
||||||
.ddr_dqs_n (ddr_dqs_n),
|
|
||||||
.ddr_dqs_p (ddr_dqs_p),
|
|
||||||
.ddr_odt (ddr_odt),
|
|
||||||
.ddr_ras_n (ddr_ras_n),
|
|
||||||
.ddr_reset_n (ddr_reset_n),
|
|
||||||
.ddr_we_n (ddr_we_n),
|
|
||||||
.enable (enable),
|
|
||||||
.eth1_125mclk (),
|
|
||||||
.eth1_25mclk (),
|
|
||||||
.eth1_2m5clk (),
|
|
||||||
.eth1_clock_speed (),
|
|
||||||
.eth1_duplex_status (),
|
|
||||||
.eth1_intn (1'b1),
|
|
||||||
.eth1_link_status (),
|
|
||||||
.eth1_mdio_mdc (eth1_mdc),
|
|
||||||
.eth1_mdio_mdio_io (eth1_mdio),
|
|
||||||
.eth1_refclk (),
|
|
||||||
.eth1_rgmii_rd (eth1_rgmii_rxdata),
|
|
||||||
.eth1_rgmii_rx_ctl (eth1_rgmii_rxctl),
|
|
||||||
.eth1_rgmii_rxc (eth1_rgmii_rxclk),
|
|
||||||
.eth1_rgmii_td (eth1_rgmii_txdata),
|
|
||||||
.eth1_rgmii_tx_ctl (eth1_rgmii_txctl),
|
|
||||||
.eth1_rgmii_txc (eth1_rgmii_txclk),
|
|
||||||
.eth1_speed_mode (),
|
|
||||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
||||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
||||||
.fixed_io_mio (fixed_io_mio),
|
|
||||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
||||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
||||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
||||||
.fmc_gt_ref_clk0 (fmc_gt_ref_clk),
|
|
||||||
.fmc_gt_ref_clk1 (fmc_gt_ref_clk),
|
|
||||||
.fmc_gt_rx_n (fmc_gt_rx_n),
|
|
||||||
.fmc_gt_rx_p (fmc_gt_rx_p),
|
|
||||||
.fmc_gt_tx_n (fmc_gt_tx_n),
|
|
||||||
.fmc_gt_tx_p (fmc_gt_tx_p),
|
|
||||||
.gpio_0_0_i (gpio_0_0_i),
|
|
||||||
.gpio_0_0_o (gpio_0_0_o),
|
|
||||||
.gpio_0_0_t (gpio_0_0_t),
|
|
||||||
.gpio_0_1_i (gpio_0_1_i),
|
|
||||||
.gpio_0_1_o (gpio_0_1_o),
|
|
||||||
.gpio_0_1_t (gpio_0_1_t),
|
|
||||||
.gpio_1_0_i (gpio_1_0_i),
|
|
||||||
.gpio_1_0_o (gpio_1_0_o),
|
|
||||||
.gpio_1_0_t (gpio_1_0_t),
|
|
||||||
.gpio_1_1_i (gpio_1_1_i),
|
|
||||||
.gpio_1_1_o (gpio_1_1_o),
|
|
||||||
.gpio_1_1_t (gpio_1_1_t),
|
|
||||||
.gpio_2_0_i (up_clk0_count),
|
|
||||||
.gpio_2_0_o (),
|
|
||||||
.gpio_2_0_t (),
|
|
||||||
.gpio_2_1_i (up_clk1_count),
|
|
||||||
.gpio_2_1_o (),
|
|
||||||
.gpio_2_1_t (),
|
|
||||||
.gpio_3_0_i ({31'd0, fmc_prstn}),
|
|
||||||
.gpio_3_0_o (),
|
|
||||||
.gpio_3_0_t (),
|
|
||||||
.gpio_3_1_i ({30'd0, up_pn_err, up_pn_oos}),
|
|
||||||
.gpio_3_1_o (gpio_3_1_o),
|
|
||||||
.gpio_3_1_t (),
|
|
||||||
.gpio_i (gpio_i),
|
|
||||||
.gpio_o (gpio_o),
|
|
||||||
.gpio_t (gpio_t),
|
|
||||||
.hdmi_data (hdmi_data),
|
|
||||||
.hdmi_data_e (hdmi_data_e),
|
|
||||||
.hdmi_hsync (hdmi_hsync),
|
|
||||||
.hdmi_out_clk (hdmi_out_clk),
|
|
||||||
.hdmi_vsync (hdmi_vsync),
|
|
||||||
.i2s_bclk (i2s_bclk),
|
|
||||||
.i2s_lrclk (i2s_lrclk),
|
|
||||||
.i2s_mclk (i2s_mclk),
|
|
||||||
.i2s_sdata_in (i2s_sdata_in),
|
|
||||||
.i2s_sdata_out (i2s_sdata_out),
|
|
||||||
.iic_main_scl_io (iic_scl),
|
|
||||||
.iic_main_sda_io (iic_sda),
|
|
||||||
.otg_vbusoc (1'b0),
|
|
||||||
.ps_intr_00 (1'b0),
|
|
||||||
.ps_intr_01 (1'b0),
|
|
||||||
.ps_intr_02 (1'b0),
|
|
||||||
.ps_intr_03 (1'b0),
|
|
||||||
.ps_intr_04 (1'b0),
|
|
||||||
.ps_intr_05 (1'b0),
|
|
||||||
.ps_intr_06 (1'b0),
|
|
||||||
.ps_intr_07 (1'b0),
|
|
||||||
.ps_intr_08 (1'b0),
|
|
||||||
.ps_intr_09 (1'b0),
|
|
||||||
.ps_intr_10 (1'b0),
|
|
||||||
.ps_intr_11 (1'b0),
|
|
||||||
.rx_clk_in_n (rx_clk_in_n),
|
|
||||||
.rx_clk_in_p (rx_clk_in_p),
|
|
||||||
.rx_data_in_n (rx_data_in_n),
|
|
||||||
.rx_data_in_p (rx_data_in_p),
|
|
||||||
.rx_frame_in_n (rx_frame_in_n),
|
|
||||||
.rx_frame_in_p (rx_frame_in_p),
|
|
||||||
.spdif (spdif),
|
|
||||||
.spi0_clk_i (1'b0),
|
|
||||||
.spi0_clk_o (spi_clk),
|
|
||||||
.spi0_csn_0_o (spi_csn),
|
|
||||||
.spi0_csn_1_o (),
|
|
||||||
.spi0_csn_2_o (),
|
|
||||||
.spi0_csn_i (1'b1),
|
|
||||||
.spi0_sdi_i (spi_miso),
|
|
||||||
.spi0_sdo_i (1'b0),
|
|
||||||
.spi0_sdo_o (spi_mosi),
|
|
||||||
.spi1_clk_i (1'b0),
|
|
||||||
.spi1_clk_o (),
|
|
||||||
.spi1_csn_0_o (),
|
|
||||||
.spi1_csn_1_o (),
|
|
||||||
.spi1_csn_2_o (),
|
|
||||||
.spi1_csn_i (1'b1),
|
|
||||||
.spi1_sdi_i (1'b0),
|
|
||||||
.spi1_sdo_i (1'b0),
|
|
||||||
.spi1_sdo_o (),
|
|
||||||
.tdd_sync_in (),
|
|
||||||
.tdd_sync_out (),
|
|
||||||
.tx_clk_out_n (tx_clk_out_n),
|
|
||||||
.tx_clk_out_p (tx_clk_out_p),
|
|
||||||
.tx_data_out_n (tx_data_out_n),
|
|
||||||
.tx_data_out_p (tx_data_out_p),
|
|
||||||
.tx_frame_out_n (tx_frame_out_n),
|
|
||||||
.tx_frame_out_p (tx_frame_out_p),
|
|
||||||
.txnrx (txnrx),
|
|
||||||
.up_clk (up_clk),
|
|
||||||
.up_enable (gpio_o[47]),
|
|
||||||
.up_pn_err (up_pn_err),
|
|
||||||
.up_pn_err_clr (up_pn_err_clr),
|
|
||||||
.up_pn_oos (up_pn_oos),
|
|
||||||
.up_pn_oos_clr (up_pn_oos_clr),
|
|
||||||
.up_rst (up_rst),
|
|
||||||
.up_rstn (up_rstn),
|
|
||||||
.up_txnrx (gpio_o[48]));
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
Loading…
Reference in New Issue