usdrx1: Add DDR FIFO
The converters on the usdrx1 generate 2.5GB/s. This more than we can transport over the HP interconnects to the system memory. Add a dedicated DDR FIFO to design which can be used to buffer the data before it is transferred to the main memory. Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA FIFO size from 4 to 8, so we can transfer the captured data faster to the main memory. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
bbada6ed8f
commit
9fb336e464
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@ -78,18 +78,22 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt
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set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt
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set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.ID {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.CLKS_ASYNC_REQ_SRC {1}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.CLKS_ASYNC_SRC_DEST {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma
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set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_usdrx1_dma
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set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_usdrx1_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
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@ -199,7 +203,7 @@ ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data
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ad_connect gt_rx_sof_2 axi_ad9671_core_2/rx_sof
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ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data
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ad_connect gt_rx_sof_3 axi_ad9671_core_3/rx_sof
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ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk
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ad_connect axi_ad9671_core_0/adc_clk usdrx1_fifo/adc_clk
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ad_connect adc_data_0 axi_ad9671_core_0/adc_data
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ad_connect adc_data_1 axi_ad9671_core_1/adc_data
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ad_connect adc_data_2 axi_ad9671_core_2/adc_data
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@ -216,9 +220,8 @@ ad_connect adc_dovf_0 axi_ad9671_core_0/adc_dovf
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ad_connect adc_dovf_1 axi_ad9671_core_1/adc_dovf
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ad_connect adc_dovf_2 axi_ad9671_core_2/adc_dovf
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ad_connect adc_dovf_3 axi_ad9671_core_3/adc_dovf
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ad_connect adc_wr_en axi_usdrx1_dma/fifo_wr_en
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ad_connect adc_data axi_usdrx1_dma/fifo_wr_din
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ad_connect adc_dovf axi_usdrx1_dma/fifo_wr_overflow
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ad_connect adc_wr_en usdrx1_fifo/adc_wr
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ad_connect adc_data usdrx1_fifo/adc_wdata
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ad_connect axi_ad9671_adc_raddr axi_ad9671_core_0/adc_raddr_out
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ad_connect axi_ad9671_adc_raddr axi_ad9671_core_1/adc_raddr_in
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ad_connect axi_ad9671_adc_raddr axi_ad9671_core_2/adc_raddr_in
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@ -228,6 +231,16 @@ ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in
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ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in
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ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in
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ad_connect axi_usdrx1_gt/rx_rst usdrx1_fifo/adc_rst
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ad_connect adc_dovf usdrx1_fifo/adc_wovf
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ad_connect usdrx1_fifo/dma_wdata axi_usdrx1_dma/s_axis_data
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ad_connect usdrx1_fifo/dma_wr axi_usdrx1_dma/s_axis_valid
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ad_connect usdrx1_fifo/dma_wready axi_usdrx1_dma/s_axis_ready
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ad_connect usdrx1_fifo/dma_xfer_req axi_usdrx1_dma/s_axis_xfer_req
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ad_connect sys_200m_clk axi_usdrx1_dma/s_axis_aclk
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ad_connect sys_200m_clk usdrx1_fifo/dma_clk
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# address map
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ad_cpu_interconnect 0x44A00000 axi_ad9671_core_0
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@ -240,8 +253,8 @@ ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd
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ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma
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ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk axi_usdrx1_dma/m_dest_axi
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ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi
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ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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@ -1,4 +1,22 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source ../common/usdrx1_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
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ad_connect sys_rst usdrx1_fifo/sys_rst
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ad_connect sys_clk usdrx1_fifo/sys_clk
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ad_connect ddr3 usdrx1_fifo/ddr3
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create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
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[get_bd_addr_spaces usdrx1_fifo/axi_adcfifo/axi] \
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[get_bd_addr_segs usdrx1_fifo/axi_ddr_cntrl/memmap/memaddr] \
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SEG_axi_ddr_cntrl_memaddr
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source ../common/usdrx1_bd.tcl
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@ -10,6 +10,7 @@ adi_project_files usdrx1_zc706 [list \
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"system_top.v" \
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"system_constr.xdc" \
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"../common/usdrx1_spi.v" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
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adi_project_run usdrx1_zc706
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@ -74,6 +74,26 @@ module system_top (
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spdif,
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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iic_scl,
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iic_sda,
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@ -152,6 +172,26 @@ module system_top (
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output spdif;
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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inout iic_scl;
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inout iic_sda;
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@ -360,6 +400,24 @@ module system_top (
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endgenerate
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system_wrapper i_system_wrapper (
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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