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ad_serdes_clk- syntax errors

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Rejeesh Kutty 2016-09-13 14:02:11 -04:00
parent 734b39a8ed
commit a0318ae868
1 changed files with 1 additions and 1 deletions
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library/altera/common/ad_serdes_clk.v
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@ -78,7 +78,7 @@ module ad_serdes_clk (
// internal signals // internal signals
wire [31:0] up_drp_rdata_int_s, wire [31:0] up_drp_rdata_int_s;
wire up_drp_busy_int_s; wire up_drp_busy_int_s;
wire up_drp_locked_int_s; wire up_drp_locked_int_s;