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axi_ad9361_tdd: Define control bits for continuous receive/transmit

main
Istvan Csomortani 2015-05-14 17:21:32 +03:00
parent c9c05e21c2
commit a07d11c3e9
3 changed files with 33 additions and 22 deletions
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9
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -112,9 +112,10 @@ module axi_ad9361_tdd (
wire tdd_secondary_s; wire tdd_secondary_s;
wire tdd_burst_en_s; wire tdd_burst_en_s;
wire [ 5:0] tdd_burst_count_s; wire [ 5:0] tdd_burst_count_s;
wire tdd_continuous_tx_s;
wire tdd_continuous_rx_s;
wire [21:0] tdd_counter_init_s; wire [21:0] tdd_counter_init_s;
wire [21:0] tdd_frame_length_s; wire [21:0] tdd_frame_length_s;
wire [ 7:0] tdd_tx_dp_delay_s;
wire [21:0] tdd_vco_rx_on_1_s; wire [21:0] tdd_vco_rx_on_1_s;
wire [21:0] tdd_vco_rx_off_1_s; wire [21:0] tdd_vco_rx_off_1_s;
wire [21:0] tdd_vco_tx_on_1_s; wire [21:0] tdd_vco_tx_on_1_s;
@ -152,9 +153,10 @@ module axi_ad9361_tdd (
.tdd_secondary(tdd_secondary_s), .tdd_secondary(tdd_secondary_s),
.tdd_burst_en(tdd_burst_en_s), .tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s), .tdd_burst_count(tdd_burst_count_s),
.tdd_continuous_tx(tdd_continuous_tx_s),
.tdd_continuous_rx(tdd_continuous_rx_s),
.tdd_counter_init(tdd_counter_init_s), .tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s), .tdd_frame_length(tdd_frame_length_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
@ -197,7 +199,8 @@ module axi_ad9361_tdd (
.tdd_frame_length(tdd_frame_length_s), .tdd_frame_length(tdd_frame_length_s),
.tdd_burst_en(tdd_burst_en_s), .tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s), .tdd_burst_count(tdd_burst_count_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s), .tdd_continuous_tx(tdd_continuous_tx_s),
.tdd_continuous_rx(tdd_continuous_rx_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),

16
library/common/ad_tdd_control.v
View File

@ -55,7 +55,8 @@ module ad_tdd_control(
tdd_frame_length, tdd_frame_length,
tdd_burst_en, tdd_burst_en,
tdd_burst_count, tdd_burst_count,
tdd_tx_dp_delay, tdd_continuous_tx,
tdd_continuous_rx,
tdd_vco_rx_on_1, tdd_vco_rx_on_1,
tdd_vco_rx_off_1, tdd_vco_rx_off_1,
@ -110,7 +111,8 @@ module ad_tdd_control(
input [21:0] tdd_frame_length; input [21:0] tdd_frame_length;
input tdd_burst_en; input tdd_burst_en;
input [ 5:0] tdd_burst_count; input [ 5:0] tdd_burst_count;
input [ 7:0] tdd_tx_dp_delay; input tdd_continuous_tx;
input tdd_continuous_rx;
input [21:0] tdd_vco_rx_on_1; input [21:0] tdd_vco_rx_on_1;
input [21:0] tdd_vco_rx_off_1; input [21:0] tdd_vco_rx_off_1;
@ -486,7 +488,7 @@ module ad_tdd_control(
always @(posedge clk) begin always @(posedge clk) begin
if(tdd_counter_state == ON) begin if(tdd_counter_state == ON) begin
if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2 || tdd_continuous_rx) begin
tdd_rx_vco_en <= 1'b1; tdd_rx_vco_en <= 1'b1;
end end
else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin
@ -499,7 +501,7 @@ module ad_tdd_control(
always @(posedge clk) begin always @(posedge clk) begin
if(tdd_counter_state == ON) begin if(tdd_counter_state == ON) begin
if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2 || tdd_continuous_tx) begin
tdd_tx_vco_en <= 1'b1; tdd_tx_vco_en <= 1'b1;
end end
else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin
@ -512,7 +514,7 @@ module ad_tdd_control(
always @(posedge clk) begin always @(posedge clk) begin
if(tdd_counter_state == ON) begin if(tdd_counter_state == ON) begin
if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2 || tdd_continuous_rx) begin
tdd_rx_rf_en <= 1'b1; tdd_rx_rf_en <= 1'b1;
end end
else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin
@ -525,7 +527,7 @@ module ad_tdd_control(
always @(posedge clk) begin always @(posedge clk) begin
if(tdd_counter_state == ON) begin if(tdd_counter_state == ON) begin
if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2 || tdd_continuous_tx) begin
tdd_tx_rf_en <= 1'b1; tdd_tx_rf_en <= 1'b1;
end end
else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin
@ -538,7 +540,7 @@ module ad_tdd_control(
always @(posedge clk) begin always @(posedge clk) begin
if(tdd_counter_state == ON) begin if(tdd_counter_state == ON) begin
if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2 || tdd_continuous_tx) begin
tdd_tx_dp_en <= 1'b1; tdd_tx_dp_en <= 1'b1;
end end
else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin

30
library/common/up_tdd_cntrl.v
View File

@ -51,9 +51,10 @@ module up_tdd_cntrl (
tdd_secondary, tdd_secondary,
tdd_burst_en, tdd_burst_en,
tdd_burst_count, tdd_burst_count,
tdd_continuous_tx,
tdd_continuous_rx,
tdd_counter_init, tdd_counter_init,
tdd_frame_length, tdd_frame_length,
tdd_tx_dp_delay,
tdd_vco_rx_on_1, tdd_vco_rx_on_1,
tdd_vco_rx_off_1, tdd_vco_rx_off_1,
tdd_vco_tx_on_1, tdd_vco_tx_on_1,
@ -107,8 +108,10 @@ module up_tdd_cntrl (
output tdd_burst_en; output tdd_burst_en;
output [ 5:0] tdd_burst_count; output [ 5:0] tdd_burst_count;
output tdd_continuous_tx;
output tdd_continuous_rx;
output [ 7:0] tdd_tx_dp_delay;
output [21:0] tdd_vco_rx_on_1; output [21:0] tdd_vco_rx_on_1;
output [21:0] tdd_vco_rx_off_1; output [21:0] tdd_vco_rx_off_1;
output [21:0] tdd_vco_tx_on_1; output [21:0] tdd_vco_tx_on_1;
@ -162,7 +165,8 @@ module up_tdd_cntrl (
reg up_tdd_burst_en = 1'h0; reg up_tdd_burst_en = 1'h0;
reg [ 5:0] up_tdd_burst_count = 6'h0; reg [ 5:0] up_tdd_burst_count = 6'h0;
reg [ 7:0] up_tdd_tx_dp_delay = 8'h0; reg up_tdd_continuous_tx = 1'h0;
reg up_tdd_continuous_rx = 1'h0;
reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0; reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0;
reg [21:0] up_tdd_vco_tx2rx_1 = 22'h0; reg [21:0] up_tdd_vco_tx2rx_1 = 22'h0;
@ -217,6 +221,8 @@ module up_tdd_cntrl (
up_tdd_counter_init <= 22'h0; up_tdd_counter_init <= 22'h0;
up_tdd_frame_length <= 22'h0; up_tdd_frame_length <= 22'h0;
up_tdd_burst_en <= 1'h0; up_tdd_burst_en <= 1'h0;
up_tdd_continuous_rx <= 1'h0;
up_tdd_continuous_tx <= 1'h0;
up_tdd_burst_count <= 6'h0; up_tdd_burst_count <= 6'h0;
up_tdd_vco_rx_on_1 <= 22'h0; up_tdd_vco_rx_on_1 <= 22'h0;
up_tdd_vco_rx_off_1 <= 22'h0; up_tdd_vco_rx_off_1 <= 22'h0;
@ -258,6 +264,8 @@ module up_tdd_cntrl (
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_burst_count <= up_wdata[21:16]; up_tdd_burst_count <= up_wdata[21:16];
up_tdd_continuous_rx <= up_wdata[3];
up_tdd_continuous_tx <= up_wdata[2];
up_tdd_burst_en <= up_wdata[1]; up_tdd_burst_en <= up_wdata[1];
up_tdd_secondary <= up_wdata[0]; up_tdd_secondary <= up_wdata[0];
end end
@ -267,9 +275,6 @@ module up_tdd_cntrl (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_frame_length <= up_wdata[21:0]; up_tdd_frame_length <= up_wdata[21:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h15)) begin
up_tdd_tx_dp_delay <= up_wdata[ 7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[21:0]; up_tdd_vco_rx_on_1 <= up_wdata[21:0];
end end
@ -348,10 +353,9 @@ module up_tdd_cntrl (
8'h02: up_rdata <= up_scratch; 8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'h0, up_resetn}; 8'h10: up_rdata <= {31'h0, up_resetn};
8'h11: up_rdata <= {29'h0, up_tdd_counter_reset, up_tdd_start, up_tdd_enable}; 8'h11: up_rdata <= {29'h0, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 14'h0, up_tdd_burst_en, up_tdd_secondary}; 8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 12'h0, up_tdd_continuous_rx, up_tdd_continuous_tx, up_tdd_burst_en, up_tdd_secondary};
8'h13: up_rdata <= {10'h0, up_tdd_counter_init}; 8'h13: up_rdata <= {10'h0, up_tdd_counter_init};
8'h14: up_rdata <= {10'h0, up_tdd_frame_length}; 8'h14: up_rdata <= {10'h0, up_tdd_frame_length};
8'h15: up_rdata <= {24'h0, up_tdd_tx_dp_delay};
8'h1A: up_rdata <= {24'h0, up_tdd_status_s}; 8'h1A: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= {10'h0, up_tdd_vco_rx_on_1}; 8'h20: up_rdata <= {10'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= {10'h0, up_tdd_vco_rx_off_1}; 8'h21: up_rdata <= {10'h0, up_tdd_vco_rx_off_1};
@ -389,7 +393,7 @@ module up_tdd_cntrl (
// rf tdd control signal CDC // rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(11)) i_tdd_control ( up_xfer_cntrl #(.DATA_WIDTH(13)) i_tdd_control (
.up_rstn(up_rstn), .up_rstn(up_rstn),
.up_clk(up_clk), .up_clk(up_clk),
.up_data_cntrl({up_tdd_enable, .up_data_cntrl({up_tdd_enable,
@ -397,6 +401,8 @@ module up_tdd_cntrl (
up_tdd_secondary, up_tdd_secondary,
up_tdd_start, up_tdd_start,
up_tdd_burst_en, up_tdd_burst_en,
up_tdd_continuous_tx,
up_tdd_continuous_rx,
up_tdd_burst_count up_tdd_burst_count
}), }),
.up_xfer_done(up_cntrl_xfer_done), .up_xfer_done(up_cntrl_xfer_done),
@ -407,15 +413,16 @@ module up_tdd_cntrl (
tdd_secondary, tdd_secondary,
tdd_start, tdd_start,
tdd_burst_en, tdd_burst_en,
tdd_continuous_tx,
tdd_continuous_rx,
tdd_burst_count tdd_burst_count
})); }));
up_xfer_cntrl #(.DATA_WIDTH(492)) i_tdd_counter_values ( up_xfer_cntrl #(.DATA_WIDTH(484)) i_tdd_counter_values (
.up_rstn(up_rstn), .up_rstn(up_rstn),
.up_clk(up_clk), .up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init, .up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length, up_tdd_frame_length,
up_tdd_tx_dp_delay,
up_tdd_vco_rx_on_1, up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1, up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1, up_tdd_vco_tx_on_1,
@ -442,7 +449,6 @@ module up_tdd_cntrl (
.d_clk(clk), .d_clk(clk),
.d_data_cntrl({tdd_counter_init, .d_data_cntrl({tdd_counter_init,
tdd_frame_length, tdd_frame_length,
tdd_tx_dp_delay,
tdd_vco_rx_on_1, tdd_vco_rx_on_1,
tdd_vco_rx_off_1, tdd_vco_rx_off_1,
tdd_vco_tx_on_1, tdd_vco_tx_on_1,