axi_ad9361_tdd: Define control bits for continuous receive/transmit
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c9c05e21c2
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a07d11c3e9
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@ -112,9 +112,10 @@ module axi_ad9361_tdd (
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wire tdd_secondary_s;
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wire tdd_burst_en_s;
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wire [ 5:0] tdd_burst_count_s;
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wire tdd_continuous_tx_s;
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wire tdd_continuous_rx_s;
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wire [21:0] tdd_counter_init_s;
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wire [21:0] tdd_frame_length_s;
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wire [ 7:0] tdd_tx_dp_delay_s;
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wire [21:0] tdd_vco_rx_on_1_s;
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wire [21:0] tdd_vco_rx_off_1_s;
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wire [21:0] tdd_vco_tx_on_1_s;
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@ -152,9 +153,10 @@ module axi_ad9361_tdd (
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.tdd_secondary(tdd_secondary_s),
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.tdd_burst_en(tdd_burst_en_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_continuous_tx(tdd_continuous_tx_s),
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.tdd_continuous_rx(tdd_continuous_rx_s),
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.tdd_counter_init(tdd_counter_init_s),
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -197,7 +199,8 @@ module axi_ad9361_tdd (
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.tdd_frame_length(tdd_frame_length_s),
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.tdd_burst_en(tdd_burst_en_s),
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.tdd_burst_count(tdd_burst_count_s),
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.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
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.tdd_continuous_tx(tdd_continuous_tx_s),
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.tdd_continuous_rx(tdd_continuous_rx_s),
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.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
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.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
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.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
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@ -55,7 +55,8 @@ module ad_tdd_control(
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tdd_frame_length,
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tdd_burst_en,
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tdd_burst_count,
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tdd_tx_dp_delay,
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tdd_continuous_tx,
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tdd_continuous_rx,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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@ -110,7 +111,8 @@ module ad_tdd_control(
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input [21:0] tdd_frame_length;
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input tdd_burst_en;
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input [ 5:0] tdd_burst_count;
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input [ 7:0] tdd_tx_dp_delay;
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input tdd_continuous_tx;
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input tdd_continuous_rx;
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input [21:0] tdd_vco_rx_on_1;
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input [21:0] tdd_vco_rx_off_1;
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@ -486,7 +488,7 @@ module ad_tdd_control(
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always @(posedge clk) begin
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if(tdd_counter_state == ON) begin
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if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
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if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2 || tdd_continuous_rx) begin
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tdd_rx_vco_en <= 1'b1;
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end
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else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin
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@ -499,7 +501,7 @@ module ad_tdd_control(
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always @(posedge clk) begin
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if(tdd_counter_state == ON) begin
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if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
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if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2 || tdd_continuous_tx) begin
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tdd_tx_vco_en <= 1'b1;
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end
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else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin
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@ -512,7 +514,7 @@ module ad_tdd_control(
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always @(posedge clk) begin
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if(tdd_counter_state == ON) begin
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if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
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if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2 || tdd_continuous_rx) begin
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tdd_rx_rf_en <= 1'b1;
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end
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else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin
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@ -525,7 +527,7 @@ module ad_tdd_control(
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always @(posedge clk) begin
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if(tdd_counter_state == ON) begin
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if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
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if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2 || tdd_continuous_tx) begin
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tdd_tx_rf_en <= 1'b1;
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end
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else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin
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@ -538,7 +540,7 @@ module ad_tdd_control(
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always @(posedge clk) begin
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if(tdd_counter_state == ON) begin
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if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
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if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2 || tdd_continuous_tx) begin
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tdd_tx_dp_en <= 1'b1;
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end
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else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin
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@ -51,9 +51,10 @@ module up_tdd_cntrl (
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tdd_secondary,
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tdd_burst_en,
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tdd_burst_count,
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tdd_continuous_tx,
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tdd_continuous_rx,
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tdd_counter_init,
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tdd_frame_length,
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tdd_tx_dp_delay,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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tdd_vco_tx_on_1,
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@ -107,8 +108,10 @@ module up_tdd_cntrl (
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output tdd_burst_en;
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output [ 5:0] tdd_burst_count;
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output tdd_continuous_tx;
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output tdd_continuous_rx;
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output [ 7:0] tdd_tx_dp_delay;
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output [21:0] tdd_vco_rx_on_1;
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output [21:0] tdd_vco_rx_off_1;
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output [21:0] tdd_vco_tx_on_1;
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@ -162,7 +165,8 @@ module up_tdd_cntrl (
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reg up_tdd_burst_en = 1'h0;
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reg [ 5:0] up_tdd_burst_count = 6'h0;
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reg [ 7:0] up_tdd_tx_dp_delay = 8'h0;
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reg up_tdd_continuous_tx = 1'h0;
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reg up_tdd_continuous_rx = 1'h0;
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reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0;
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reg [21:0] up_tdd_vco_tx2rx_1 = 22'h0;
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@ -217,6 +221,8 @@ module up_tdd_cntrl (
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up_tdd_counter_init <= 22'h0;
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up_tdd_frame_length <= 22'h0;
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up_tdd_burst_en <= 1'h0;
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up_tdd_continuous_rx <= 1'h0;
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up_tdd_continuous_tx <= 1'h0;
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up_tdd_burst_count <= 6'h0;
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up_tdd_vco_rx_on_1 <= 22'h0;
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up_tdd_vco_rx_off_1 <= 22'h0;
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@ -258,6 +264,8 @@ module up_tdd_cntrl (
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
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up_tdd_burst_count <= up_wdata[21:16];
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up_tdd_continuous_rx <= up_wdata[3];
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up_tdd_continuous_tx <= up_wdata[2];
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up_tdd_burst_en <= up_wdata[1];
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up_tdd_secondary <= up_wdata[0];
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end
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@ -267,9 +275,6 @@ module up_tdd_cntrl (
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_tdd_frame_length <= up_wdata[21:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h15)) begin
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up_tdd_tx_dp_delay <= up_wdata[ 7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
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up_tdd_vco_rx_on_1 <= up_wdata[21:0];
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end
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@ -348,10 +353,9 @@ module up_tdd_cntrl (
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8'h02: up_rdata <= up_scratch;
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8'h10: up_rdata <= {31'h0, up_resetn};
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8'h11: up_rdata <= {29'h0, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
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8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 14'h0, up_tdd_burst_en, up_tdd_secondary};
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8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 12'h0, up_tdd_continuous_rx, up_tdd_continuous_tx, up_tdd_burst_en, up_tdd_secondary};
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8'h13: up_rdata <= {10'h0, up_tdd_counter_init};
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8'h14: up_rdata <= {10'h0, up_tdd_frame_length};
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8'h15: up_rdata <= {24'h0, up_tdd_tx_dp_delay};
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8'h1A: up_rdata <= {24'h0, up_tdd_status_s};
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8'h20: up_rdata <= {10'h0, up_tdd_vco_rx_on_1};
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8'h21: up_rdata <= {10'h0, up_tdd_vco_rx_off_1};
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@ -389,7 +393,7 @@ module up_tdd_cntrl (
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// rf tdd control signal CDC
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up_xfer_cntrl #(.DATA_WIDTH(11)) i_tdd_control (
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up_xfer_cntrl #(.DATA_WIDTH(13)) i_tdd_control (
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_data_cntrl({up_tdd_enable,
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@ -397,6 +401,8 @@ module up_tdd_cntrl (
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up_tdd_secondary,
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up_tdd_start,
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up_tdd_burst_en,
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up_tdd_continuous_tx,
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up_tdd_continuous_rx,
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up_tdd_burst_count
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}),
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.up_xfer_done(up_cntrl_xfer_done),
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@ -407,15 +413,16 @@ module up_tdd_cntrl (
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tdd_secondary,
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tdd_start,
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tdd_burst_en,
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tdd_continuous_tx,
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tdd_continuous_rx,
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tdd_burst_count
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}));
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up_xfer_cntrl #(.DATA_WIDTH(492)) i_tdd_counter_values (
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up_xfer_cntrl #(.DATA_WIDTH(484)) i_tdd_counter_values (
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_data_cntrl({up_tdd_counter_init,
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up_tdd_frame_length,
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up_tdd_tx_dp_delay,
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up_tdd_vco_rx_on_1,
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up_tdd_vco_rx_off_1,
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up_tdd_vco_tx_on_1,
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@ -442,7 +449,6 @@ module up_tdd_cntrl (
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.d_clk(clk),
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.d_data_cntrl({tdd_counter_init,
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tdd_frame_length,
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tdd_tx_dp_delay,
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tdd_vco_rx_on_1,
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tdd_vco_rx_off_1,
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tdd_vco_tx_on_1,
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