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axi_hdmi_tx: Use abstract multiplier module supporting both Xilinx and Intel FPGAs

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Adrian Costina 2018-01-25 15:31:21 +02:00 committed by István Csomortáni
parent 9877862517
commit a0cb3af11d
4 changed files with 27 additions and 28 deletions
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1
library/axi_hdmi_tx/Makefile
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@ -19,6 +19,7 @@ M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc

1
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -26,6 +26,7 @@ add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/commo
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_hdmi_tx.v VERILOG PATH $ad_hdl_dir/library/common/up_hdmi_tx.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file axi_hdmi_tx_vdma.v VERILOG PATH axi_hdmi_tx_vdma.v
add_fileset_file axi_hdmi_tx_es.v VERILOG PATH axi_hdmi_tx_es.v
add_fileset_file axi_hdmi_tx_core.v VERILOG PATH axi_hdmi_tx_core.v

1
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
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@ -17,6 +17,7 @@ adi_ip_files axi_hdmi_tx [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_hdmi_tx.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \

52
library/common/ad_csc_1_mul.v
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@ -43,57 +43,53 @@ module ad_csc_1_mul #(
// data_a is signed
input clk,
input [16:0] data_a,
input [ 7:0] data_b,
output [24:0] data_p,
input clk,
input [16:0] data_a,
input [ 7:0] data_b,
output [24:0] data_p,
// delay match
input [DW:0] ddata_in,
output reg [DW:0] ddata_out);
localparam DW = DELAY_DATA_WIDTH - 1;
input [(DELAY_DATA_WIDTH-1):0] ddata_in,
output [(DELAY_DATA_WIDTH-1):0] ddata_out);
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg p1_sign = 'd0;
reg p2_sign = 'd0;
reg sign_p = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p3_ddata = 'd0;
reg p1_sign = 'd0;
reg p2_sign = 'd0;
reg p3_sign = 'd0;
// internal signals
wire [25:0] data_p_s;
wire [33:0] p3_data_s;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
p3_ddata <= p2_ddata;
end
always @(posedge clk) begin
p1_sign <= data_a[16];
p2_sign <= p1_sign;
sign_p <= p2_sign;
p3_sign <= p2_sign;
end
assign data_p = {sign_p, data_p_s[23:0]};
assign ddata_out = p3_ddata;
assign data_p = {p3_sign, p3_data_s[23:0]};
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (9))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A ({1'b0, data_a[15:0]}),
.B ({1'b0, data_b}),
.P (data_p_s));
ad_mul ad_mul_1 (
.clk(clk),
.data_a({1'b0, data_a[15:0]}),
.data_b({9'b0, data_b}),
.data_p(p3_data_s),
.ddata_in(16'h0),
.ddata_out());
endmodule