From a0e30a22110628130ea4ec9a3091c3f0876c20ac Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 27 Mar 2017 16:56:46 +0200
Subject: [PATCH] util_axis_fifo: Improve clock gating of registers and BRAM

Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/util_axis_fifo/util_axis_fifo.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v
index a590d6b21..71ef85a06 100644
--- a/library/util_axis_fifo/util_axis_fifo.v
+++ b/library/util_axis_fifo/util_axis_fifo.v
@@ -94,7 +94,7 @@ assign s_axis_empty = s_axis_ready;
 assign s_axis_room = s_axis_ready;
 
 always @(posedge s_axis_aclk) begin
-  if (s_axis_ready)
+  if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
     cdc_sync_fifo_ram <= s_axis_data;
 end
 
@@ -171,7 +171,7 @@ fifo_address_sync #(
 end
 
 always @(posedge s_axis_aclk) begin
-  if (s_axis_ready)
+  if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
     ram[s_axis_waddr] <= s_axis_data;
 end
 
@@ -192,7 +192,7 @@ always @(posedge m_axis_aclk) begin
 end
 
 always @(posedge m_axis_aclk) begin
-  if (~valid || m_axis_ready)
+  if ((~valid || m_axis_ready) && _m_axis_valid)
     data <= ram[m_axis_raddr];
 end