kcu105: base complete with ethernet errors
Rejeesh Kutty
parent
87d326a474
commit
a10043c4f4
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@ -109,6 +109,9 @@ module axi_hdmi_tx (
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parameter C_BASEADDR = 32'hffffffff;
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parameter C_HIGHADDR = 32'h00000000;
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localparam XILINX_7SERIES = 0;
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localparam XILINX_ULTRASCALE = 1;
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// hdmi interface
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input hdmi_clk;
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@ -362,6 +365,16 @@ module axi_hdmi_tx (
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// hdmi output clock
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generate
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if (PCORE_DEVICE_TYPE == XILINX_ULTRASCALE) begin
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ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
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.SR (1'b0),
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.D1 (1'b1),
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.D2 (1'b0),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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if (PCORE_DEVICE_TYPE == XILINX_7SERIES) begin
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ODDR #(.INIT(1'b0)) i_clk_oddr (
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.R (1'b0),
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.S (1'b0),
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@ -370,6 +383,8 @@ module axi_hdmi_tx (
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.D2 (1'b0),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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endgenerate
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endmodule
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@ -1,3 +1,3 @@
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
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@ -1,14 +1,14 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create adv7511_kcu105
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adi_project_files adv7511_kcu105 [list \
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"system_top.v" \
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"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
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adi_project_run adv7511_kcu105
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create adv7511_kcu105
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adi_project_files adv7511_kcu105 [list \
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"system_top.v" \
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"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
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adi_project_run adv7511_kcu105
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@ -126,7 +126,6 @@ module system_top (
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 7:0] gpio_led;
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inout [ 8:0] gpio_sw;
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@ -142,6 +141,34 @@ module system_top (
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output spdif;
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// internal registers
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reg [31:0] sys_reset_m = 'd0;
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reg sys_cpu_rst = 'd0;
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reg sys_cpu_rstn = 'd0;
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// internal signals
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wire mdm_reset;
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wire mig_reset;
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wire mig_ready;
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wire sys_cpu_clk;
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// default logic
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assign fan_pwm = 1'b1;
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assign sys_reset_req = mdm_reset | mig_reset | ~mig_ready;
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always @(posedge sys_cpu_clk) begin
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if (sys_reset_req == 1'b1) begin
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sys_reset_m <= {32{1'b1}};
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end else begin
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sys_reset_m <= {sys_reset_m[30:0], 1'b0};
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end
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sys_cpu_rst <= sys_reset_m[31];
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sys_cpu_rstn <= ~sys_reset_m[31];
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end
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// instantiations
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system_wrapper i_system_wrapper (
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@ -160,7 +187,6 @@ module system_top (
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.c0_ddr4_odt (ddr4_odt),
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.c0_ddr4_par (ddr4_par),
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.c0_ddr4_reset_n (ddr4_reset_n),
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.fan_pwm (fan_pwm),
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.gpio_lcd_tri_io (),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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@ -174,21 +200,26 @@ module system_top (
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.iic_rstn (iic_rstn),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio_io),
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.mgt_clk_clk_n (sgmii_clk_n),
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.mgt_clk_clk_p (sgmii_clk_p),
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.mdm_reset (mdm_reset),
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.mig_ready (mig_ready),
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.mig_reset (mig_reset),
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.phy_rst_n (phy_rst_n),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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.sgmii_txp (sgmii_txp),
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.phy_sd (1'b1),
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.sgmii_clk_n (sgmii_clk_n),
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.sgmii_clk_p (sgmii_clk_p),
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.sgmii_rx_n (sgmii_rx_n),
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.sgmii_rx_p (sgmii_rx_p),
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.sgmii_tx_n (sgmii_tx_n),
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.sgmii_tx_p (sgmii_tx_p),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_cpu_clk (sys_cpu_clk),
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.sys_cpu_rst (sys_cpu_rst),
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.sys_cpu_rstn (sys_cpu_rstn),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.unc_int0 (1'b0),
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.unc_int1 (1'b0),
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.unc_int2 (1'b0),
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.unc_int3 (1'b0),
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.unc_int4 (1'b0));
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@ -1,490 +1,496 @@
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# create board design
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# interface ports
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set sys_rst [create_bd_port -dir I -type rst sys_rst]
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set sys_clk_p [create_bd_port -dir I sys_clk_p]
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set sys_clk_n [create_bd_port -dir I sys_clk_n]
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set fan_pwm [create_bd_port -dir O fan_pwm]
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set c0_ddr4 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4]
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set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n]
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set mgt_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk]
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set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
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set sgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii]
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set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
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set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
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set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
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set iic_rstn [create_bd_port -dir O iic_rstn]
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set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
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set uart_sin [create_bd_port -dir I uart_sin]
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set uart_sout [create_bd_port -dir O uart_sout]
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set unc_int0 [create_bd_port -dir I unc_int0]
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set unc_int1 [create_bd_port -dir I unc_int1]
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set unc_int2 [create_bd_port -dir I unc_int2]
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set unc_int3 [create_bd_port -dir I unc_int3]
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set unc_int4 [create_bd_port -dir I unc_int4]
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set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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# spdif audio
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set spdif [create_bd_port -dir O spdif]
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
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# instance: microblaze - processor
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set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb]
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set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb
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set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb
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set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb
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set_property -dict [list CONFIG.C_I_LMB {1}] $sys_mb
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set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $sys_mb
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set_property -dict [list CONFIG.C_USE_ICACHE {1}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
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set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb
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# instance: microblaze - local memory & bus
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set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
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set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
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set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
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set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
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set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
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set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
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# instance: microblaze- mdm
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set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.1 sys_mb_debug]
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set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
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# instance: system reset/clocks
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
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# instance: ddr (mig)
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:5.0 axi_ddr_cntrl]
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source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
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# instance: axi interconnect (lite)
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set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect]
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set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect
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set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
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set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
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# instance: axi interconnect
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set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect]
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set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
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set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
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set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
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set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
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# instance: default peripherals
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set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.1 axi_ethernet]
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set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
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set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
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set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
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set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
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set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
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set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
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set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd]
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set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd
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set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led
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set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_sw_led
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_sw_led
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
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# instance: interrupt
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set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
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set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
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set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.0 sys_concat_aux_intc]
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set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc
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set_property -dict [list CONFIG.IN8_WIDTH {5}] $sys_concat_aux_intc
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.0 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
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set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
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set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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# connections
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst]
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst]
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|
||||
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset]
|
||||
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset]
|
||||
|
||||
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset]
|
||||
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst]
|
||||
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst]
|
||||
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
|
||||
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
|
||||
|
||||
# microblaze local memory
|
||||
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
|
||||
connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M]
|
||||
connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M]
|
||||
|
||||
# microblaze debug & interrupt
|
||||
|
||||
connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
|
||||
connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr]
|
||||
connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8]
|
||||
|
||||
# defaults (peripherals)
|
||||
|
||||
connect_bd_net -net axi_ddr_cntrl_calib_complete [get_bd_pins axi_ddr_cntrl/c0_init_calib_complete] [get_bd_pins sys_rstgen/dcm_locked]
|
||||
|
||||
set sys_cpu_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||
set sys_mem_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
|
||||
set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
|
||||
set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
|
||||
|
||||
connect_bd_net -net sys_cpu_resetn $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_mem_resetn $sys_mem_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_mem_clk $sys_mem_clk_source
|
||||
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_mem_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_mem_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_mem_clk_source
|
||||
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_mem_resetn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_uart/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_timer/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_intc/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ethernet_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb/Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/axis_clk] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_uart/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_timer/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_intc/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ethernet/ref_clk] $sys_200m_clk_source
|
||||
|
||||
# defaults (interconnect - processor)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_s00 [get_bd_intf_pins axi_cpu_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_cpu_interconnect/M06_AXI]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m00 [get_bd_intf_pins axi_cpu_aux_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m01 [get_bd_intf_pins axi_cpu_aux_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m02 [get_bd_intf_pins axi_cpu_aux_interconnect/M02_AXI] [get_bd_intf_pins axi_ethernet_dma/S_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m03 [get_bd_intf_pins axi_cpu_aux_interconnect/M03_AXI] [get_bd_intf_pins axi_uart/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04 [get_bd_intf_pins axi_cpu_aux_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05 [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06 [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07 [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_cpu_clk_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
|
||||
# defaults (interconnect - memory)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM]
|
||||
connect_bd_net -net sys_mem_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_mem_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_mem_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_cpu_clk_source
|
||||
|
||||
# ethernet & ethernet dma
|
||||
|
||||
connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS]
|
||||
|
||||
# defaults (interrupts)
|
||||
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||
connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2]
|
||||
connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3]
|
||||
connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4]
|
||||
|
||||
# defaults (external interface)
|
||||
|
||||
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_pins axi_ethernet/signal_detect] [get_bd_ports fan_pwm]
|
||||
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
||||
connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in]
|
||||
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||
|
||||
connect_bd_net -net sys_clk_p [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p]
|
||||
connect_bd_net -net sys_clk_n [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ddr_cntrl_c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4]
|
||||
|
||||
connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet/mgt_clk]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet/sgmii]
|
||||
|
||||
connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||
connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio]
|
||||
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio]
|
||||
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2]
|
||||
|
||||
connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
|
||||
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]
|
||||
|
||||
# hdmi
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||
|
||||
# spdif audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_cpu_clk_source
|
||||
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
|
||||
# address map
|
||||
|
||||
set sys_zynq 0
|
||||
set sys_mem_size 0x40000000
|
||||
set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
|
||||
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 $sys_addr_cntrl_space [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 $sys_addr_cntrl_space [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ethernet/eth_buf/S_AXI/REG] SEG_data_ethernet
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ethernet_dma/S_AXI_LITE/Reg] SEG_data_ethernet_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_lcd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_sw_led
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
||||
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_ethernet_mac
|
||||
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
|
||||
|
||||
|
||||
# create board design
|
||||
# interface ports
|
||||
|
||||
set sys_rst [create_bd_port -dir I -type rst sys_rst]
|
||||
set sys_clk_p [create_bd_port -dir I sys_clk_p]
|
||||
set sys_clk_n [create_bd_port -dir I sys_clk_n]
|
||||
|
||||
set c0_ddr4 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4]
|
||||
|
||||
set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n]
|
||||
set phy_sd [create_bd_port -dir I phy_sd]
|
||||
set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
|
||||
set sgmii_clk_p [create_bd_port -dir I sgmii_clk_p]
|
||||
set sgmii_clk_n [create_bd_port -dir I sgmii_clk_n]
|
||||
set sgmii_rx_p [create_bd_port -dir I sgmii_rx_p]
|
||||
set sgmii_rx_n [create_bd_port -dir I sgmii_rx_n]
|
||||
set sgmii_tx_p [create_bd_port -dir O sgmii_tx_p]
|
||||
set sgmii_tx_n [create_bd_port -dir O sgmii_tx_n]
|
||||
|
||||
set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
|
||||
set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
|
||||
set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
|
||||
|
||||
set iic_rstn [create_bd_port -dir O iic_rstn]
|
||||
set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
|
||||
|
||||
set uart_sin [create_bd_port -dir I uart_sin]
|
||||
set uart_sout [create_bd_port -dir O uart_sout]
|
||||
|
||||
set mdm_reset [create_bd_port -dir O mdm_reset]
|
||||
set mig_reset [create_bd_port -dir O mig_reset]
|
||||
set mig_ready [create_bd_port -dir O mig_ready]
|
||||
set sys_cpu_clk [create_bd_port -dir O sys_cpu_clk]
|
||||
set sys_cpu_rst [create_bd_port -dir I -type rst sys_cpu_rst]
|
||||
set sys_cpu_rstn [create_bd_port -dir I -type rst sys_cpu_rstn]
|
||||
|
||||
set unc_int2 [create_bd_port -dir I unc_int2]
|
||||
set unc_int3 [create_bd_port -dir I unc_int3]
|
||||
set unc_int4 [create_bd_port -dir I unc_int4]
|
||||
|
||||
set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
|
||||
set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
|
||||
set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
|
||||
set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
|
||||
set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
|
||||
|
||||
# spdif audio
|
||||
|
||||
set spdif [create_bd_port -dir O spdif]
|
||||
|
||||
set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
|
||||
set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_cpu_rst
|
||||
set_property -dict [list CONFIG.POLARITY {ACTIVE_LOW}] $sys_cpu_rstn
|
||||
|
||||
# instance: microblaze - processor
|
||||
|
||||
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb]
|
||||
set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_I_LMB {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_USE_ICACHE {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||
|
||||
# instance: microblaze - local memory & bus
|
||||
|
||||
set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
|
||||
set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
|
||||
|
||||
set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
||||
|
||||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
||||
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.1 sys_mb_debug]
|
||||
set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
|
||||
|
||||
# instance: system reset/clocks
|
||||
|
||||
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
|
||||
|
||||
# instance: ddr (mig)
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig:5.0 axi_ddr_cntrl]
|
||||
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
|
||||
|
||||
# instance: axi interconnect (lite)
|
||||
|
||||
set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect
|
||||
|
||||
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
|
||||
|
||||
# instance: axi interconnect
|
||||
|
||||
set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
|
||||
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
|
||||
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
|
||||
set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
|
||||
|
||||
# instance: default peripherals
|
||||
|
||||
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.1 axi_ethernet]
|
||||
set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
|
||||
|
||||
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
|
||||
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
|
||||
set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
|
||||
set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
|
||||
|
||||
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||
|
||||
set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
|
||||
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
|
||||
|
||||
set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
|
||||
|
||||
set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd]
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd
|
||||
|
||||
set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_sw_led
|
||||
set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_sw_led
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
|
||||
|
||||
# instance: interrupt
|
||||
|
||||
set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
|
||||
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
|
||||
|
||||
set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.0 sys_concat_aux_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc
|
||||
set_property -dict [list CONFIG.IN8_WIDTH {5}] $sys_concat_aux_intc
|
||||
|
||||
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.0 sys_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
|
||||
|
||||
# hdmi peripherals
|
||||
|
||||
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
|
||||
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
|
||||
set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_hdmi_core
|
||||
|
||||
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
|
||||
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
|
||||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
|
||||
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
|
||||
|
||||
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
|
||||
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
|
||||
set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
|
||||
|
||||
# connections (reset and clocks)
|
||||
|
||||
connect_bd_net -net mdm_reset [get_bd_pins sys_mb_debug/Debug_SYS_Rst] [get_bd_ports mdm_reset]
|
||||
connect_bd_net -net mig_reset [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] [get_bd_ports mig_reset]
|
||||
connect_bd_net -net mig_ready [get_bd_pins axi_ddr_cntrl/c0_init_calib_complete] [get_bd_ports mig_ready]
|
||||
|
||||
set sys_reset_source [get_bd_ports sys_cpu_rst]
|
||||
set sys_resetn_source [get_bd_ports sys_cpu_rstn]
|
||||
set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
|
||||
set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
|
||||
|
||||
connect_bd_net -net sys_cpu_rst $sys_reset_source
|
||||
connect_bd_net -net sys_cpu_rstn $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_mem_clk $sys_mem_clk_source
|
||||
connect_bd_net -net sys_200m_clk $sys_200m_clk_source
|
||||
|
||||
connect_bd_net -net sys_cpu_rst [get_bd_pins sys_mb/Reset]
|
||||
connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb/SYS_Rst]
|
||||
connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb/SYS_Rst]
|
||||
connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
|
||||
connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
|
||||
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_ports sys_cpu_clk]
|
||||
|
||||
# microblaze local memory
|
||||
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
|
||||
connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M]
|
||||
connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M]
|
||||
|
||||
# microblaze debug & interrupt
|
||||
|
||||
connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
|
||||
connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr]
|
||||
connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In8]
|
||||
|
||||
# defaults (peripherals)
|
||||
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_mem_clk_source
|
||||
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_uart/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_timer/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_intc/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb/Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet/axis_clk] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_uart/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_timer/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_intc/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ethernet/ref_clk] $sys_200m_clk_source
|
||||
|
||||
# defaults (interconnect - processor)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_s00 [get_bd_intf_pins axi_cpu_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_cpu_interconnect/M06_AXI]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m00 [get_bd_intf_pins axi_cpu_aux_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m01 [get_bd_intf_pins axi_cpu_aux_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m02 [get_bd_intf_pins axi_cpu_aux_interconnect/M02_AXI] [get_bd_intf_pins axi_ethernet_dma/S_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m03 [get_bd_intf_pins axi_cpu_aux_interconnect/M03_AXI] [get_bd_intf_pins axi_uart/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04 [get_bd_intf_pins axi_cpu_aux_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05 [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06 [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07 [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_cpu_clk_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
|
||||
# defaults (interconnect - memory)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4_S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_mem_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_cpu_clk_source
|
||||
|
||||
# ethernet & ethernet dma
|
||||
|
||||
connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n]
|
||||
connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS]
|
||||
|
||||
# defaults (interrupts)
|
||||
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_uart/interrupt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_06 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
|
||||
connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||
connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int2]
|
||||
connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int3]
|
||||
connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int4]
|
||||
|
||||
# defaults (external interface)
|
||||
|
||||
connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect]
|
||||
connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||
|
||||
connect_bd_net -net sys_clk_p [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p]
|
||||
connect_bd_net -net sys_clk_n [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ddr_cntrl_c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4]
|
||||
|
||||
connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio]
|
||||
connect_bd_net -net axi_ethernet_sgmii_clk_p [get_bd_ports sgmii_clk_p] [get_bd_pins axi_ethernet/mgt_clk_clk_p]
|
||||
connect_bd_net -net axi_ethernet_sgmii_clk_n [get_bd_ports sgmii_clk_n] [get_bd_pins axi_ethernet/mgt_clk_clk_n]
|
||||
connect_bd_net -net axi_ethernet_sgmii_rx_p [get_bd_ports sgmii_rx_p] [get_bd_pins axi_ethernet/sgmii_rxp]
|
||||
connect_bd_net -net axi_ethernet_sgmii_rx_n [get_bd_ports sgmii_rx_n] [get_bd_pins axi_ethernet/sgmii_rxn]
|
||||
connect_bd_net -net axi_ethernet_sgmii_tx_p [get_bd_ports sgmii_tx_p] [get_bd_pins axi_ethernet/sgmii_txp]
|
||||
connect_bd_net -net axi_ethernet_sgmii_tx_n [get_bd_ports sgmii_tx_n] [get_bd_pins axi_ethernet/sgmii_txn]
|
||||
|
||||
connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||
connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio]
|
||||
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio]
|
||||
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2]
|
||||
|
||||
connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
|
||||
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]
|
||||
|
||||
# hdmi
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||
|
||||
# spdif audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_cpu_clk_source
|
||||
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
|
||||
# address map
|
||||
|
||||
set sys_zynq 0
|
||||
set sys_mem_size 0x40000000
|
||||
set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
|
||||
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 $sys_addr_cntrl_space [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 $sys_addr_cntrl_space [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ethernet/eth_buf/S_AXI/REG] SEG_data_ethernet
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ethernet_dma/S_AXI_LITE/Reg] SEG_data_ethernet_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_lcd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_sw_led
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
||||
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_ethernet_mac
|
||||
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_mem_ddr_cntrl
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,228 +1,228 @@
|
|||
|
||||
# constraints
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
|
||||
|
||||
set_false_path -through [get_ports sys_rst]
|
||||
|
||||
# clocks
|
||||
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_p]
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_n]
|
||||
|
||||
create_clock -name sys_clk -period 3.33 [get_ports sys_clk_p]
|
||||
|
||||
# ddr
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD SSTL12} [get_ports ddr4_act_n]
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL12} [get_ports ddr4_addr[0]]
|
||||
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD SSTL12} [get_ports ddr4_addr[1]]
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD SSTL12} [get_ports ddr4_addr[2]]
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD SSTL12} [get_ports ddr4_addr[3]]
|
||||
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD SSTL12} [get_ports ddr4_addr[4]]
|
||||
set_property -dict {PACKAGE_PIN AL17 IOSTANDARD SSTL12} [get_ports ddr4_addr[5]]
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD SSTL12} [get_ports ddr4_addr[6]]
|
||||
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD SSTL12} [get_ports ddr4_addr[7]]
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD SSTL12} [get_ports ddr4_addr[8]]
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD SSTL12} [get_ports ddr4_addr[9]]
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL12} [get_ports ddr4_addr[10]]
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL12} [get_ports ddr4_addr[11]]
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD SSTL12} [get_ports ddr4_addr[12]]
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD SSTL12} [get_ports ddr4_addr[13]]
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL12} [get_ports ddr4_addr[14]]
|
||||
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD SSTL12} [get_ports ddr4_addr[15]]
|
||||
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL12} [get_ports ddr4_addr[16]]
|
||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL12} [get_ports ddr4_ba[0]]
|
||||
set_property -dict {PACKAGE_PIN AL15 IOSTANDARD SSTL12} [get_ports ddr4_ba[1]]
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD SSTL12} [get_ports ddr4_bg]
|
||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_p]
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_n]
|
||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL12} [get_ports ddr4_cke]
|
||||
set_property -dict {PACKAGE_PIN AL19 IOSTANDARD SSTL12} [get_ports ddr4_cs_n]
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD POD12} [get_ports ddr4_dm_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD POD12} [get_ports ddr4_dm_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD POD12} [get_ports ddr4_dm_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD POD12} [get_ports ddr4_dm_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD POD12} [get_ports ddr4_dm_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AN26 IOSTANDARD POD12} [get_ports ddr4_dm_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD POD12} [get_ports ddr4_dm_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AL32 IOSTANDARD POD12} [get_ports ddr4_dm_n[7]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[0]]
|
||||
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[1]]
|
||||
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[2]]
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[3]]
|
||||
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[4]]
|
||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[5]]
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[6]]
|
||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[7]]
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[8]]
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[9]]
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[10]]
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[11]]
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[12]]
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[13]]
|
||||
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[14]]
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[15]]
|
||||
set_property -dict {PACKAGE_PIN AL22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[16]]
|
||||
set_property -dict {PACKAGE_PIN AL25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[17]]
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[18]]
|
||||
set_property -dict {PACKAGE_PIN AK23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[19]]
|
||||
set_property -dict {PACKAGE_PIN AK22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[20]]
|
||||
set_property -dict {PACKAGE_PIN AL24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[21]]
|
||||
set_property -dict {PACKAGE_PIN AL20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[22]]
|
||||
set_property -dict {PACKAGE_PIN AL23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[23]]
|
||||
set_property -dict {PACKAGE_PIN AM24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[24]]
|
||||
set_property -dict {PACKAGE_PIN AN23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[25]]
|
||||
set_property -dict {PACKAGE_PIN AN24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[26]]
|
||||
set_property -dict {PACKAGE_PIN AP23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[27]]
|
||||
set_property -dict {PACKAGE_PIN AP25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[28]]
|
||||
set_property -dict {PACKAGE_PIN AN22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[29]]
|
||||
set_property -dict {PACKAGE_PIN AP24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[30]]
|
||||
set_property -dict {PACKAGE_PIN AM22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[31]]
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[32]]
|
||||
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[33]]
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[34]]
|
||||
set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[35]]
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[36]]
|
||||
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[37]]
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[38]]
|
||||
set_property -dict {PACKAGE_PIN AM26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[39]]
|
||||
set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[40]]
|
||||
set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[41]]
|
||||
set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[42]]
|
||||
set_property -dict {PACKAGE_PIN AN28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[43]]
|
||||
set_property -dict {PACKAGE_PIN AL29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[44]]
|
||||
set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[45]]
|
||||
set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[46]]
|
||||
set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[47]]
|
||||
set_property -dict {PACKAGE_PIN AH31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[48]]
|
||||
set_property -dict {PACKAGE_PIN AH32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[49]]
|
||||
set_property -dict {PACKAGE_PIN AJ34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[50]]
|
||||
set_property -dict {PACKAGE_PIN AK31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[51]]
|
||||
set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[52]]
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[53]]
|
||||
set_property -dict {PACKAGE_PIN AH34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[54]]
|
||||
set_property -dict {PACKAGE_PIN AK32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[55]]
|
||||
set_property -dict {PACKAGE_PIN AN33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[56]]
|
||||
set_property -dict {PACKAGE_PIN AP33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[57]]
|
||||
set_property -dict {PACKAGE_PIN AM34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[58]]
|
||||
set_property -dict {PACKAGE_PIN AP31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[59]]
|
||||
set_property -dict {PACKAGE_PIN AM32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[60]]
|
||||
set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[61]]
|
||||
set_property -dict {PACKAGE_PIN AL34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[62]]
|
||||
set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[63]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[0]]
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[2]]
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AP20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[3]]
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AL27 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[4]]
|
||||
set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AN29 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[5]]
|
||||
set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AH33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[6]]
|
||||
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AN34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[7]]
|
||||
set_property -dict {PACKAGE_PIN AP34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[7]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD SSTL12} [get_ports ddr4_odt]
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL12} [get_ports ddr4_par]
|
||||
set_property -dict {PACKAGE_PIN AL18 IOSTANDARD LVCMOS12} [get_ports ddr4_reset_n]
|
||||
|
||||
# ethernet
|
||||
|
||||
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
|
||||
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports mdio_mdio_io]
|
||||
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports sgmii_clk_p]
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports sgmii_clk_n]
|
||||
set_property -dict {PACKAGE_PIN P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_rx_p]
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_rx_n]
|
||||
set_property -dict {PACKAGE_PIN N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_tx_p]
|
||||
set_property -dict {PACKAGE_PIN M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_tx_n]
|
||||
|
||||
set_false_path -through [get_ports phy_rst_n]
|
||||
create_clock -name sgmii_clk -period 8.00 [get_ports sgmii_clk_p]
|
||||
|
||||
# uart
|
||||
|
||||
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sin]
|
||||
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sout]
|
||||
|
||||
# fan
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
|
||||
|
||||
# sw/led
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12} [get_ports gpio_sw[0]] ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12} [get_ports gpio_sw[1]] ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12} [get_ports gpio_sw[2]] ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12} [get_ports gpio_sw[3]] ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports gpio_sw[4]] ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18} [get_ports gpio_sw[5]] ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports gpio_sw[6]] ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18} [get_ports gpio_sw[7]] ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gpio_sw[8]] ## GPIO_SW_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports gpio_led[0]]
|
||||
set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports gpio_led[1]]
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports gpio_led[2]]
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports gpio_led[3]]
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports gpio_led[4]]
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports gpio_led[5]]
|
||||
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS18} [get_ports gpio_led[6]]
|
||||
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_led[7]]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
|
||||
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
|
||||
|
||||
# hdmi
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
|
||||
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
|
||||
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
|
||||
set_property -dict {PACKAGE_PIN AK11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
|
||||
set_property -dict {PACKAGE_PIN AP11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
|
||||
set_property -dict {PACKAGE_PIN AP13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
|
||||
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
|
||||
set_property -dict {PACKAGE_PIN AN11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
|
||||
set_property -dict {PACKAGE_PIN AM11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
|
||||
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
|
||||
set_property -dict {PACKAGE_PIN AM12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
|
||||
set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
|
||||
set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
|
||||
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
|
||||
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
|
||||
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
|
||||
|
||||
# spdif
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports spdif]
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1]
|
||||
create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout2]
|
||||
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||
|
||||
set_clock_groups -asynchronous -group {cpu_clk}
|
||||
set_clock_groups -asynchronous -group {mem_clk}
|
||||
set_clock_groups -asynchronous -group {m200_clk}
|
||||
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||
set_clock_groups -asynchronous -group {spdif_clk}
|
||||
|
||||
|
||||
# constraints
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
|
||||
|
||||
set_false_path -through [get_ports sys_rst]
|
||||
|
||||
# clocks
|
||||
|
||||
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_p]
|
||||
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports sys_clk_n]
|
||||
|
||||
create_clock -name sys_clk -period 3.33 [get_ports sys_clk_p]
|
||||
|
||||
# ddr
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD SSTL12} [get_ports ddr4_act_n]
|
||||
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL12} [get_ports ddr4_addr[0]]
|
||||
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD SSTL12} [get_ports ddr4_addr[1]]
|
||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD SSTL12} [get_ports ddr4_addr[2]]
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD SSTL12} [get_ports ddr4_addr[3]]
|
||||
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD SSTL12} [get_ports ddr4_addr[4]]
|
||||
set_property -dict {PACKAGE_PIN AL17 IOSTANDARD SSTL12} [get_ports ddr4_addr[5]]
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD SSTL12} [get_ports ddr4_addr[6]]
|
||||
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD SSTL12} [get_ports ddr4_addr[7]]
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD SSTL12} [get_ports ddr4_addr[8]]
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD SSTL12} [get_ports ddr4_addr[9]]
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL12} [get_ports ddr4_addr[10]]
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL12} [get_ports ddr4_addr[11]]
|
||||
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD SSTL12} [get_ports ddr4_addr[12]]
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD SSTL12} [get_ports ddr4_addr[13]]
|
||||
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL12} [get_ports ddr4_addr[14]]
|
||||
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD SSTL12} [get_ports ddr4_addr[15]]
|
||||
set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL12} [get_ports ddr4_addr[16]]
|
||||
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL12} [get_ports ddr4_ba[0]]
|
||||
set_property -dict {PACKAGE_PIN AL15 IOSTANDARD SSTL12} [get_ports ddr4_ba[1]]
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD SSTL12} [get_ports ddr4_bg]
|
||||
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_p]
|
||||
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD DIFF_POD12} [get_ports ddr4_ck_n]
|
||||
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL12} [get_ports ddr4_cke]
|
||||
set_property -dict {PACKAGE_PIN AL19 IOSTANDARD SSTL12} [get_ports ddr4_cs_n]
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD POD12} [get_ports ddr4_dm_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD POD12} [get_ports ddr4_dm_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD POD12} [get_ports ddr4_dm_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD POD12} [get_ports ddr4_dm_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD POD12} [get_ports ddr4_dm_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AN26 IOSTANDARD POD12} [get_ports ddr4_dm_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD POD12} [get_ports ddr4_dm_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AL32 IOSTANDARD POD12} [get_ports ddr4_dm_n[7]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[0]]
|
||||
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[1]]
|
||||
set_property -dict {PACKAGE_PIN AF22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[2]]
|
||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[3]]
|
||||
set_property -dict {PACKAGE_PIN AE22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[4]]
|
||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[5]]
|
||||
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[6]]
|
||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[7]]
|
||||
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[8]]
|
||||
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[9]]
|
||||
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[10]]
|
||||
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[11]]
|
||||
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[12]]
|
||||
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[13]]
|
||||
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[14]]
|
||||
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[15]]
|
||||
set_property -dict {PACKAGE_PIN AL22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[16]]
|
||||
set_property -dict {PACKAGE_PIN AL25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[17]]
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[18]]
|
||||
set_property -dict {PACKAGE_PIN AK23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[19]]
|
||||
set_property -dict {PACKAGE_PIN AK22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[20]]
|
||||
set_property -dict {PACKAGE_PIN AL24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[21]]
|
||||
set_property -dict {PACKAGE_PIN AL20 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[22]]
|
||||
set_property -dict {PACKAGE_PIN AL23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[23]]
|
||||
set_property -dict {PACKAGE_PIN AM24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[24]]
|
||||
set_property -dict {PACKAGE_PIN AN23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[25]]
|
||||
set_property -dict {PACKAGE_PIN AN24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[26]]
|
||||
set_property -dict {PACKAGE_PIN AP23 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[27]]
|
||||
set_property -dict {PACKAGE_PIN AP25 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[28]]
|
||||
set_property -dict {PACKAGE_PIN AN22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[29]]
|
||||
set_property -dict {PACKAGE_PIN AP24 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[30]]
|
||||
set_property -dict {PACKAGE_PIN AM22 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[31]]
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[32]]
|
||||
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[33]]
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[34]]
|
||||
set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[35]]
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[36]]
|
||||
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[37]]
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[38]]
|
||||
set_property -dict {PACKAGE_PIN AM26 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[39]]
|
||||
set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[40]]
|
||||
set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[41]]
|
||||
set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[42]]
|
||||
set_property -dict {PACKAGE_PIN AN28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[43]]
|
||||
set_property -dict {PACKAGE_PIN AL29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[44]]
|
||||
set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[45]]
|
||||
set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[46]]
|
||||
set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[47]]
|
||||
set_property -dict {PACKAGE_PIN AH31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[48]]
|
||||
set_property -dict {PACKAGE_PIN AH32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[49]]
|
||||
set_property -dict {PACKAGE_PIN AJ34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[50]]
|
||||
set_property -dict {PACKAGE_PIN AK31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[51]]
|
||||
set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[52]]
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[53]]
|
||||
set_property -dict {PACKAGE_PIN AH34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[54]]
|
||||
set_property -dict {PACKAGE_PIN AK32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[55]]
|
||||
set_property -dict {PACKAGE_PIN AN33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[56]]
|
||||
set_property -dict {PACKAGE_PIN AP33 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[57]]
|
||||
set_property -dict {PACKAGE_PIN AM34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[58]]
|
||||
set_property -dict {PACKAGE_PIN AP31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[59]]
|
||||
set_property -dict {PACKAGE_PIN AM32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[60]]
|
||||
set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[61]]
|
||||
set_property -dict {PACKAGE_PIN AL34 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[62]]
|
||||
set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI} [get_ports ddr4_dq[63]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[0]]
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[0]]
|
||||
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[1]]
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[2]]
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[2]]
|
||||
set_property -dict {PACKAGE_PIN AP20 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[3]]
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[3]]
|
||||
set_property -dict {PACKAGE_PIN AL27 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[4]]
|
||||
set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[4]]
|
||||
set_property -dict {PACKAGE_PIN AN29 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[5]]
|
||||
set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[5]]
|
||||
set_property -dict {PACKAGE_PIN AH33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[6]]
|
||||
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[6]]
|
||||
set_property -dict {PACKAGE_PIN AN34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_p[7]]
|
||||
set_property -dict {PACKAGE_PIN AP34 IOSTANDARD DIFF_POD12} [get_ports ddr4_dqs_n[7]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD SSTL12} [get_ports ddr4_odt]
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL12} [get_ports ddr4_par]
|
||||
set_property -dict {PACKAGE_PIN AL18 IOSTANDARD LVCMOS12} [get_ports ddr4_reset_n]
|
||||
|
||||
# ethernet
|
||||
|
||||
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
|
||||
set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports mdio_mdio_io]
|
||||
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
|
||||
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports sgmii_clk_p]
|
||||
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25} [get_ports sgmii_clk_n]
|
||||
set_property -dict {PACKAGE_PIN P24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_rx_p]
|
||||
set_property -dict {PACKAGE_PIN P25 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_rx_n]
|
||||
set_property -dict {PACKAGE_PIN N24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_tx_p]
|
||||
set_property -dict {PACKAGE_PIN M24 IOSTANDARD DIFF_HSTL_I_18} [get_ports sgmii_tx_n]
|
||||
|
||||
set_false_path -through [get_ports phy_rst_n]
|
||||
create_clock -name sgmii_clk -period 8.00 [get_ports sgmii_clk_p]
|
||||
|
||||
# uart
|
||||
|
||||
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sin]
|
||||
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sout]
|
||||
|
||||
# fan
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
|
||||
|
||||
# sw/led
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[0]]; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[1]]; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[2]]; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[3]]; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[4]]; ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[5]]; ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[6]]; ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[7]]; ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[8]]; ## GPIO_SW_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports gpio_led[0]]
|
||||
set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports gpio_led[1]]
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports gpio_led[2]]
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports gpio_led[3]]
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports gpio_led[4]]
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports gpio_led[5]]
|
||||
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS18} [get_ports gpio_led[6]]
|
||||
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS18} [get_ports gpio_led[7]]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
|
||||
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
|
||||
|
||||
# hdmi
|
||||
|
||||
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
|
||||
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
|
||||
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
|
||||
set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
|
||||
set_property -dict {PACKAGE_PIN AK11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
|
||||
set_property -dict {PACKAGE_PIN AP11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
|
||||
set_property -dict {PACKAGE_PIN AP13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
|
||||
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
|
||||
set_property -dict {PACKAGE_PIN AN11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
|
||||
set_property -dict {PACKAGE_PIN AM11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
|
||||
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
|
||||
set_property -dict {PACKAGE_PIN AM12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
|
||||
set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
|
||||
set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
|
||||
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
|
||||
set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
|
||||
set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
|
||||
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN AJ11 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
|
||||
|
||||
# spdif
|
||||
|
||||
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports spdif]
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1]
|
||||
#create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout2]
|
||||
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||
|
||||
set_clock_groups -asynchronous -group {cpu_clk}
|
||||
#set_clock_groups -asynchronous -group {mem_clk}
|
||||
set_clock_groups -asynchronous -group {m200_clk}
|
||||
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||
set_clock_groups -asynchronous -group {spdif_clk}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,159 +1,159 @@
|
|||
|
||||
# ddr controller
|
||||
|
||||
set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-083}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3333}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiSelection {true}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiNarrowBurst {true}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_adr_0 {bank45.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_1 {bank45.byte2.pin1}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_2 {bank45.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_3 {bank45.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_4 {bank45.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_5 {bank45.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_6 {bank45.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_7 {bank45.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_8 {bank45.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_9 {bank45.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_10 {bank45.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_11 {bank45.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_12 {bank45.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_13 {bank45.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_14 {bank45.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_15 {bank45.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_16 {bank45.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_0 {bank44.byte0.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_1 {bank44.byte0.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_2 {bank44.byte0.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_3 {bank44.byte0.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_4 {bank44.byte0.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_5 {bank44.byte0.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_6 {bank44.byte0.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_7 {bank44.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_0 {bank44.byte0.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_0 {bank44.byte0.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_0 {bank44.byte0.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_8 {bank44.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_9 {bank44.byte1.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_10 {bank44.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_11 {bank44.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_12 {bank44.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_13 {bank44.byte1.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_14 {bank44.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_15 {bank44.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_1 {bank44.byte1.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_1 {bank44.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_1 {bank44.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_16 {bank44.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_17 {bank44.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_18 {bank44.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_19 {bank44.byte2.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_20 {bank44.byte2.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_21 {bank44.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_22 {bank44.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_23 {bank44.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_2 {bank44.byte2.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_2 {bank44.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_2 {bank44.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_24 {bank44.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_25 {bank44.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_26 {bank44.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_27 {bank44.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_28 {bank44.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_29 {bank44.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_30 {bank44.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_31 {bank44.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_3 {bank44.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_3 {bank44.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_3 {bank44.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_32 {bank46.byte0.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_33 {bank46.byte0.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_34 {bank46.byte0.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_35 {bank46.byte0.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_36 {bank46.byte0.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_37 {bank46.byte0.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_38 {bank46.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_39 {bank46.byte0.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_4 {bank46.byte0.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_4 {bank46.byte0.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_4 {bank46.byte0.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_40 {bank46.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_41 {bank46.byte1.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_42 {bank46.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_43 {bank46.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_44 {bank46.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_45 {bank46.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_46 {bank46.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_47 {bank46.byte1.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_5 {bank46.byte1.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_5 {bank46.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_5 {bank46.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_48 {bank46.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_49 {bank46.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_50 {bank46.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_51 {bank46.byte2.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_52 {bank46.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_53 {bank46.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_54 {bank46.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_55 {bank46.byte2.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_6 {bank46.byte2.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_6 {bank46.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_6 {bank46.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_56 {bank46.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_57 {bank46.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_58 {bank46.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_59 {bank46.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_60 {bank46.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_61 {bank46.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_62 {bank46.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_63 {bank46.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_7 {bank46.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_7 {bank46.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_7 {bank46.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_ba_0 {bank45.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ba_1 {bank45.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_bg_0 {bank45.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_cke_0 {bank45.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_cs_n_0 {bank45.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_odt_0 {bank45.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_par {bank45.byte3.pin1}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_reset_n {bank45.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_act_n {bank45.byte2.pin12}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ck_t {bank45.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ck_c {bank45.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
# This loc of sys_clk should be removed from MIG once DRC is fixed - CR782609
|
||||
|
||||
set_property -dict [list CONFIG.c0_sys_clk_p {bank45.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_sys_clk_n {bank45.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
# Currently, it is required to manually unassign the pins in MIG IO Placer
|
||||
|
||||
#set_property -dict [list CONFIG.sys_rst {bank45.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
#set_property -dict [list CONFIG.c0_data_compare_error {bank65.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
#set_property -dict [list CONFIG.c0_init_calib_complete {bank65.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.sys_rst {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_data_compare_error {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_init_calib_complete {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
|
||||
# ddr controller
|
||||
|
||||
set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_MemoryPart {MT40A256M16HA-083}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_BANK_COLUMN}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3333}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiSelection {true}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiNarrowBurst {true}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_adr_0 {bank45.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_1 {bank45.byte2.pin1}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_2 {bank45.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_3 {bank45.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_4 {bank45.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_5 {bank45.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_6 {bank45.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_7 {bank45.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_8 {bank45.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_9 {bank45.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_10 {bank45.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_11 {bank45.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_12 {bank45.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_13 {bank45.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_14 {bank45.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_15 {bank45.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_adr_16 {bank45.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_0 {bank44.byte0.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_1 {bank44.byte0.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_2 {bank44.byte0.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_3 {bank44.byte0.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_4 {bank44.byte0.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_5 {bank44.byte0.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_6 {bank44.byte0.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_7 {bank44.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_0 {bank44.byte0.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_0 {bank44.byte0.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_0 {bank44.byte0.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_8 {bank44.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_9 {bank44.byte1.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_10 {bank44.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_11 {bank44.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_12 {bank44.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_13 {bank44.byte1.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_14 {bank44.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_15 {bank44.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_1 {bank44.byte1.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_1 {bank44.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_1 {bank44.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_16 {bank44.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_17 {bank44.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_18 {bank44.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_19 {bank44.byte2.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_20 {bank44.byte2.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_21 {bank44.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_22 {bank44.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_23 {bank44.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_2 {bank44.byte2.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_2 {bank44.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_2 {bank44.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_24 {bank44.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_25 {bank44.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_26 {bank44.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_27 {bank44.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_28 {bank44.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_29 {bank44.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_30 {bank44.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_31 {bank44.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_3 {bank44.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_3 {bank44.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_3 {bank44.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_32 {bank46.byte0.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_33 {bank46.byte0.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_34 {bank46.byte0.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_35 {bank46.byte0.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_36 {bank46.byte0.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_37 {bank46.byte0.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_38 {bank46.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_39 {bank46.byte0.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_4 {bank46.byte0.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_4 {bank46.byte0.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_4 {bank46.byte0.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_40 {bank46.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_41 {bank46.byte1.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_42 {bank46.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_43 {bank46.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_44 {bank46.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_45 {bank46.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_46 {bank46.byte1.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_47 {bank46.byte1.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_5 {bank46.byte1.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_5 {bank46.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_5 {bank46.byte1.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_48 {bank46.byte2.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_49 {bank46.byte2.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_50 {bank46.byte2.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_51 {bank46.byte2.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_52 {bank46.byte2.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_53 {bank46.byte2.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_54 {bank46.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_55 {bank46.byte2.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_6 {bank46.byte2.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_6 {bank46.byte2.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_6 {bank46.byte2.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_dq_56 {bank46.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_57 {bank46.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_58 {bank46.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_59 {bank46.byte3.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_60 {bank46.byte3.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_61 {bank46.byte3.pin4}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_62 {bank46.byte3.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dq_63 {bank46.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dm_dbi_n_7 {bank46.byte3.pin0}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_t_7 {bank46.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_dqs_c_7 {bank46.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.c0_ba_0 {bank45.byte3.pin9}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ba_1 {bank45.byte1.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_bg_0 {bank45.byte2.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_cke_0 {bank45.byte3.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_cs_n_0 {bank45.byte1.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_odt_0 {bank45.byte1.pin8}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_par {bank45.byte3.pin1}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_reset_n {bank45.byte1.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_act_n {bank45.byte2.pin12}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ck_t {bank45.byte3.pin6}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_ck_c {bank45.byte3.pin7}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
# This loc of sys_clk should be removed from MIG once DRC is fixed - CR782609
|
||||
|
||||
set_property -dict [list CONFIG.c0_sys_clk_p {bank45.byte1.pin10}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_sys_clk_n {bank45.byte1.pin11}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
# Currently, it is required to manually unassign the pins in MIG IO Placer
|
||||
|
||||
#set_property -dict [list CONFIG.sys_rst {bank45.byte0.pin5}] [get_bd_cells axi_ddr_cntrl]
|
||||
#set_property -dict [list CONFIG.c0_data_compare_error {bank65.byte3.pin2}] [get_bd_cells axi_ddr_cntrl]
|
||||
#set_property -dict [list CONFIG.c0_init_calib_complete {bank65.byte3.pin3}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
set_property -dict [list CONFIG.sys_rst {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_data_compare_error {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.c0_init_calib_complete {Unassigned}] [get_bd_cells axi_ddr_cntrl]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue