kcu105: base complete with ethernet errors
Rejeesh Kutty
parent
87d326a474
commit
a10043c4f4
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@ -109,6 +109,9 @@ module axi_hdmi_tx (
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parameter C_BASEADDR = 32'hffffffff;
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parameter C_HIGHADDR = 32'h00000000;
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localparam XILINX_7SERIES = 0;
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localparam XILINX_ULTRASCALE = 1;
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// hdmi interface
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input hdmi_clk;
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@ -362,6 +365,16 @@ module axi_hdmi_tx (
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// hdmi output clock
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generate
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if (PCORE_DEVICE_TYPE == XILINX_ULTRASCALE) begin
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ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
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.SR (1'b0),
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.D1 (1'b1),
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.D2 (1'b0),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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if (PCORE_DEVICE_TYPE == XILINX_7SERIES) begin
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ODDR #(.INIT(1'b0)) i_clk_oddr (
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.R (1'b0),
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.S (1'b0),
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@ -370,6 +383,8 @@ module axi_hdmi_tx (
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.D2 (1'b0),
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.C (hdmi_clk),
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.Q (hdmi_out_clk));
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end
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endgenerate
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endmodule
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@ -126,7 +126,6 @@ module system_top (
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 7:0] gpio_led;
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inout [ 8:0] gpio_sw;
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@ -142,6 +141,34 @@ module system_top (
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output spdif;
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// internal registers
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reg [31:0] sys_reset_m = 'd0;
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reg sys_cpu_rst = 'd0;
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reg sys_cpu_rstn = 'd0;
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// internal signals
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wire mdm_reset;
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wire mig_reset;
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wire mig_ready;
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wire sys_cpu_clk;
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// default logic
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assign fan_pwm = 1'b1;
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assign sys_reset_req = mdm_reset | mig_reset | ~mig_ready;
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always @(posedge sys_cpu_clk) begin
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if (sys_reset_req == 1'b1) begin
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sys_reset_m <= {32{1'b1}};
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end else begin
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sys_reset_m <= {sys_reset_m[30:0], 1'b0};
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end
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sys_cpu_rst <= sys_reset_m[31];
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sys_cpu_rstn <= ~sys_reset_m[31];
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end
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// instantiations
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system_wrapper i_system_wrapper (
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@ -160,7 +187,6 @@ module system_top (
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.c0_ddr4_odt (ddr4_odt),
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.c0_ddr4_par (ddr4_par),
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.c0_ddr4_reset_n (ddr4_reset_n),
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.fan_pwm (fan_pwm),
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.gpio_lcd_tri_io (),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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@ -174,21 +200,26 @@ module system_top (
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.iic_rstn (iic_rstn),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio_io),
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.mgt_clk_clk_n (sgmii_clk_n),
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.mgt_clk_clk_p (sgmii_clk_p),
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.mdm_reset (mdm_reset),
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.mig_ready (mig_ready),
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.mig_reset (mig_reset),
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.phy_rst_n (phy_rst_n),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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.sgmii_txp (sgmii_txp),
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.phy_sd (1'b1),
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.sgmii_clk_n (sgmii_clk_n),
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.sgmii_clk_p (sgmii_clk_p),
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.sgmii_rx_n (sgmii_rx_n),
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.sgmii_rx_p (sgmii_rx_p),
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.sgmii_tx_n (sgmii_tx_n),
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.sgmii_tx_p (sgmii_tx_p),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_cpu_clk (sys_cpu_clk),
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.sys_cpu_rst (sys_cpu_rst),
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.sys_cpu_rstn (sys_cpu_rstn),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.unc_int0 (1'b0),
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.unc_int1 (1'b0),
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.unc_int2 (1'b0),
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.unc_int3 (1'b0),
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.unc_int4 (1'b0));
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@ -5,14 +5,18 @@
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set sys_rst [create_bd_port -dir I -type rst sys_rst]
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set sys_clk_p [create_bd_port -dir I sys_clk_p]
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set sys_clk_n [create_bd_port -dir I sys_clk_n]
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set fan_pwm [create_bd_port -dir O fan_pwm]
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set c0_ddr4 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 c0_ddr4]
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set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n]
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set mgt_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk]
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set phy_sd [create_bd_port -dir I phy_sd]
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set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
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set sgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii]
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set sgmii_clk_p [create_bd_port -dir I sgmii_clk_p]
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set sgmii_clk_n [create_bd_port -dir I sgmii_clk_n]
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set sgmii_rx_p [create_bd_port -dir I sgmii_rx_p]
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set sgmii_rx_n [create_bd_port -dir I sgmii_rx_n]
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set sgmii_tx_p [create_bd_port -dir O sgmii_tx_p]
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set sgmii_tx_n [create_bd_port -dir O sgmii_tx_n]
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set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
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set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
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@ -24,8 +28,13 @@ set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface
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set uart_sin [create_bd_port -dir I uart_sin]
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set uart_sout [create_bd_port -dir O uart_sout]
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set unc_int0 [create_bd_port -dir I unc_int0]
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set unc_int1 [create_bd_port -dir I unc_int1]
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set mdm_reset [create_bd_port -dir O mdm_reset]
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set mig_reset [create_bd_port -dir O mig_reset]
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set mig_ready [create_bd_port -dir O mig_ready]
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set sys_cpu_clk [create_bd_port -dir O sys_cpu_clk]
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set sys_cpu_rst [create_bd_port -dir I -type rst sys_cpu_rst]
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set sys_cpu_rstn [create_bd_port -dir I -type rst sys_cpu_rstn]
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set unc_int2 [create_bd_port -dir I unc_int2]
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set unc_int3 [create_bd_port -dir I unc_int3]
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set unc_int4 [create_bd_port -dir I unc_int4]
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@ -41,6 +50,8 @@ set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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set spdif [create_bd_port -dir O spdif]
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_cpu_rst
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set_property -dict [list CONFIG.POLARITY {ACTIVE_LOW}] $sys_cpu_rstn
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# instance: microblaze - processor
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@ -58,10 +69,6 @@ set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
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set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
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set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb
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# instance: microblaze - local memory & bus
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@ -84,8 +91,6 @@ set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
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# instance: system reset/clocks
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
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# instance: ddr (mig)
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@ -153,6 +158,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_hdmi_core
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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@ -175,19 +181,31 @@ set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 ax
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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# connections
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# connections (reset and clocks)
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst]
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst]
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connect_bd_net -net mdm_reset [get_bd_pins sys_mb_debug/Debug_SYS_Rst] [get_bd_ports mdm_reset]
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connect_bd_net -net mig_reset [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst] [get_bd_ports mig_reset]
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connect_bd_net -net mig_ready [get_bd_pins axi_ddr_cntrl/c0_init_calib_complete] [get_bd_ports mig_ready]
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connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset]
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connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset]
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set sys_reset_source [get_bd_ports sys_cpu_rst]
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set sys_resetn_source [get_bd_ports sys_cpu_rstn]
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set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
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set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
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set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_cpu_rst $sys_reset_source
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connect_bd_net -net sys_cpu_rstn $sys_resetn_source
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connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
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connect_bd_net -net sys_mem_clk $sys_mem_clk_source
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connect_bd_net -net sys_200m_clk $sys_200m_clk_source
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_mb/Reset]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb/SYS_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb/SYS_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_cpu_rst [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
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connect_bd_net -net sys_cpu_clk [get_bd_ports sys_cpu_clk]
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# microblaze local memory
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@ -207,40 +225,26 @@ connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get
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# defaults (peripherals)
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connect_bd_net -net axi_ddr_cntrl_calib_complete [get_bd_pins axi_ddr_cntrl/c0_init_calib_complete] [get_bd_pins sys_rstgen/dcm_locked]
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set sys_cpu_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
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set sys_mem_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
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set sys_cpu_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout1]
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set sys_mem_clk_source [get_bd_pins axi_ddr_cntrl/c0_ddr4_ui_clk]
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set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/addn_ui_clkout2]
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connect_bd_net -net sys_cpu_resetn $sys_cpu_resetn_source
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connect_bd_net -net sys_mem_resetn $sys_mem_resetn_source
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connect_bd_net -net sys_cpu_clk $sys_cpu_clk_source
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connect_bd_net -net sys_mem_clk $sys_mem_clk_source
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_cpu_resetn_source
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_cpu_resetn_source
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_cpu_resetn_source
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connect_bd_net -net sys_mem_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_mem_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_resetn_source
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connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_cpu_clk_source
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connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_cpu_clk_source
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connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_cpu_clk_source
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connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_mem_clk_source
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connect_bd_net -net sys_cpu_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
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connect_bd_net -net sys_mem_resetn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_cpu_resetn_source
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_uart/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_timer/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_intc/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
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connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_ethernet_dma/axi_resetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ddr_cntrl/c0_ddr4_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_resetn_source
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_uart/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_timer/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_intc/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_iic_main/s_axi_aresetn]
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connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ethernet_dma/axi_resetn]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb/Clk]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
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connect_bd_net -net sys_cpu_clk [get_bd_pins sys_dlmb/LMB_Clk]
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@ -273,15 +277,15 @@ connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04 [get_bd_intf_pins axi
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connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05 [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi]
|
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connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06 [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07 [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_cpu_clk_source
|
||||
|
|
@ -294,8 +298,8 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK]
|
|||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_cpu_clk_source
|
||||
|
||||
|
|
@ -307,12 +311,12 @@ connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem
|
|||
connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM]
|
||||
connect_bd_net -net sys_mem_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_mem_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_mem_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_cpu_clk_source
|
||||
|
|
@ -350,10 +354,8 @@ connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get
|
|||
|
||||
# defaults (external interface)
|
||||
|
||||
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_pins axi_ethernet/signal_detect] [get_bd_ports fan_pwm]
|
||||
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
||||
connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in]
|
||||
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||
connect_bd_net -net phy_sd [get_bd_ports phy_sd] [get_bd_pins axi_ethernet/signal_detect]
|
||||
connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||
|
||||
connect_bd_net -net sys_clk_p [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_p]
|
||||
connect_bd_net -net sys_clk_n [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/c0_sys_clk_n]
|
||||
|
|
@ -361,9 +363,13 @@ connect_bd_net -net sys_clk_n [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntr
|
|||
connect_bd_intf_net -intf_net axi_ddr_cntrl_c0_ddr4 [get_bd_intf_ports c0_ddr4] [get_bd_intf_pins axi_ddr_cntrl/C0_DDR4]
|
||||
|
||||
connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet/mgt_clk]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio]
|
||||
connect_bd_intf_net -intf_net axi_ethernet_sgmii [get_bd_intf_ports sgmii] [get_bd_intf_pins axi_ethernet/sgmii]
|
||||
connect_bd_net -net axi_ethernet_sgmii_clk_p [get_bd_ports sgmii_clk_p] [get_bd_pins axi_ethernet/mgt_clk_clk_p]
|
||||
connect_bd_net -net axi_ethernet_sgmii_clk_n [get_bd_ports sgmii_clk_n] [get_bd_pins axi_ethernet/mgt_clk_clk_n]
|
||||
connect_bd_net -net axi_ethernet_sgmii_rx_p [get_bd_ports sgmii_rx_p] [get_bd_pins axi_ethernet/sgmii_rxp]
|
||||
connect_bd_net -net axi_ethernet_sgmii_rx_n [get_bd_ports sgmii_rx_n] [get_bd_pins axi_ethernet/sgmii_rxn]
|
||||
connect_bd_net -net axi_ethernet_sgmii_tx_p [get_bd_ports sgmii_tx_p] [get_bd_pins axi_ethernet/sgmii_txp]
|
||||
connect_bd_net -net axi_ethernet_sgmii_tx_n [get_bd_ports sgmii_tx_n] [get_bd_pins axi_ethernet/sgmii_txn]
|
||||
|
||||
connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||
connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||
|
|
@ -397,13 +403,13 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
|||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
|
|
@ -430,16 +436,16 @@ connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
|||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_cpu_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_resetn_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_cpu_clk_source
|
||||
connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_cpu_clk_source
|
||||
|
||||
|
|
|
|||
|
|
@ -160,15 +160,15 @@ set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm
|
|||
|
||||
# sw/led
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12} [get_ports gpio_sw[0]] ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12} [get_ports gpio_sw[1]] ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12} [get_ports gpio_sw[2]] ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12} [get_ports gpio_sw[3]] ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports gpio_sw[4]] ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18} [get_ports gpio_sw[5]] ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18} [get_ports gpio_sw[6]] ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18} [get_ports gpio_sw[7]] ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gpio_sw[8]] ## GPIO_SW_C
|
||||
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[0]]; ## GPIO_DIP_SW0
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[1]]; ## GPIO_DIP_SW1
|
||||
set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[2]]; ## GPIO_DIP_SW2
|
||||
set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports gpio_sw[3]]; ## GPIO_DIP_SW3
|
||||
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[4]]; ## GPIO_SW_N
|
||||
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[5]]; ## GPIO_SW_E
|
||||
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[6]]; ## GPIO_SW_S
|
||||
set_property -dict {PACKAGE_PIN AF9 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[7]]; ## GPIO_SW_W
|
||||
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports gpio_sw[8]]; ## GPIO_SW_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports gpio_led[0]]
|
||||
set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports gpio_led[1]]
|
||||
|
|
@ -215,13 +215,13 @@ set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports spdif]
|
|||
# clocks
|
||||
|
||||
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout1]
|
||||
create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
#create_clock -name mem_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/c0_ddr4_ui_clk]
|
||||
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/addn_ui_clkout2]
|
||||
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||
|
||||
set_clock_groups -asynchronous -group {cpu_clk}
|
||||
set_clock_groups -asynchronous -group {mem_clk}
|
||||
#set_clock_groups -asynchronous -group {mem_clk}
|
||||
set_clock_groups -asynchronous -group {m200_clk}
|
||||
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||
set_clock_groups -asynchronous -group {spdif_clk}
|
||||
|
|
|
|||
Loading…
Reference in New Issue