spi_engine: Add support for multiple SDI lines.

By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.

library/spi_engine/axi_spi_engine/axi_spi_engine.v

@@ -42,7 +42,7 @@ module axi_spi_engine (
 
 	output sdi_data_ready,
 	input sdi_data_valid,
-	input [7:0] sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] sdi_data,
 
 	output sync_ready,
 	input sync_valid,
@@ -72,7 +72,9 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4;
 parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4;
 
 parameter ID = 'h00;
-localparam PCORE_VERSION = 'h010061;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+
+localparam PCORE_VERSION = 'h010071;
 
 wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
 wire cmd_fifo_almost_empty;
@@ -307,7 +309,7 @@ assign sdi_fifo_almost_full =
 	`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
 
 util_axis_fifo #(
-	.DATA_WIDTH(8),
+	.DATA_WIDTH(SDI_DATA_WIDTH),
 	.ASYNC_CLK(ASYNC_SPI_CLK),
 	.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
 	.S_AXIS_REGISTERED(0)

library/spi_engine/spi_engine_execution/spi_engine_execution.v

@@ -15,7 +15,7 @@ module spi_engine_execution (
 
   input sdi_data_ready,
   output reg sdi_data_valid,
-	output [7:0] sdi_data,
+  output [(SDI_DATA_WIDTH-1):0] sdi_data,
 
   input sync_ready,
   output reg sync_valid,
@@ -25,6 +25,9 @@ module spi_engine_execution (
   output sdo,
   output reg sdo_t,
   input sdi,
+  input sdi_1,
+  input sdi_2,
+  input sdi_3,
   output reg [NUM_OF_CS-1:0] cs,
   output reg three_wire
 );
@@ -32,7 +35,10 @@ module spi_engine_execution (
 parameter NUM_OF_CS = 1;
 parameter DEFAULT_SPI_CFG = 0;
 parameter DEFAULT_CLK_DIV = 0;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
 
+
+localparam NUM_OF_SDI = SDI_DATA_WIDTH >> 3;
 localparam CMD_TRANSFER = 2'b00;
 localparam CMD_CHIPSELECT = 2'b01;
 localparam CMD_WRITE = 2'b10;
@@ -83,6 +89,9 @@ wire sdo_enabled = cmd_d1[8];
 wire sdi_enabled = cmd_d1[9];
 
 reg [8:0] data_shift = 'h0;
+reg [8:0] data_shift_1 = 'h0;
+reg [8:0] data_shift_2 = 'h0;
+reg [8:0] data_shift_3 = 'h0;
 
 wire [1:0] inst = cmd[13:12];
 wire [1:0] inst_d1 = cmd_d1[13:12];
@@ -290,15 +299,25 @@ always @(posedge clk) begin
                         data_shift[8:1] <= sdo_data;
                 else
                         data_shift[8:1] <= data_shift[7:0];
+            data_shift_1[8:1] <= data_shift_1[7:0];
+            data_shift_2[8:1] <= data_shift_2[7:0];
+            data_shift_3[8:1] <= data_shift_3[7:0];
         end
 end
 
 assign sdo = data_shift[8];
-assign sdi_data = data_shift[7:0];
+assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[7:0] :
+                  (NUM_OF_SDI == 2) ? {data_shift_1[7:0], data_shift[7:0]} :
+                  (NUM_OF_SDI == 3) ? {data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
+                  (NUM_OF_SDI == 4) ? {data_shift_3[7:0], data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
+                  data_shift[7:0];
 
 always @(posedge clk) begin
         if (trigger_rx == 1'b1) begin
                 data_shift[0] <= sdi;
+        data_shift_1[0] <= sdi_1;
+        data_shift_2[0] <= sdi_2;
+        data_shift_3[0] <= sdi_3;
         end
 end
 

library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v

@@ -14,7 +14,7 @@ module spi_engine_interconnect (
 
 	input m_sdi_valid,
 	output m_sdi_ready,
-	input [7:0] m_sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] m_sdi_data,
 
 	input m_sync_valid,
 	output m_sync_ready,
@@ -31,7 +31,7 @@ module spi_engine_interconnect (
 
 	output s0_sdi_valid,
 	input s0_sdi_ready,
-	output [7:0] s0_sdi_data,
+	output [(SDI_DATA_WIDTH-1):0] s0_sdi_data,
 
 	output s0_sync_valid,
 	input s0_sync_ready,
@@ -48,13 +48,15 @@ module spi_engine_interconnect (
 
 	output s1_sdi_valid,
 	input s1_sdi_ready,
-	output [7:0] s1_sdi_data,
+	output [(SDI_DATA_WIDTH-1):0] s1_sdi_data,
 
 	output s1_sync_valid,
 	input s1_sync_ready,
 	output [7:0] s1_sync
 );
 
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
+
 reg s_active = 1'b0;
 
 reg idle = 1'b1;

library/spi_engine/spi_engine_offload/spi_engine_offload.v

@@ -27,7 +27,7 @@ module spi_engine_offload (
 
 	input sdi_data_valid,
 	output sdi_data_ready,
-	input [7:0] sdi_data,
+	input [(SDI_DATA_WIDTH-1):0] sdi_data,
 
 	input sync_valid,
 	output sync_ready,
@@ -35,12 +35,13 @@ module spi_engine_offload (
 
 	output offload_sdi_valid,
 	input offload_sdi_ready,
-	output [7:0] offload_sdi_data
+	output [(SDI_DATA_WIDTH-1):0] offload_sdi_data
 );
 
 parameter ASYNC_SPI_CLK = 0;
 parameter CMD_MEM_ADDRESS_WIDTH = 4;
 parameter SDO_MEM_ADDRESS_WIDTH = 4;
+parameter SDI_DATA_WIDTH = 8;                   // Valid data widths values are 8/16/24/32
 
 reg spi_active = 1'b0;