spi_engine: Add support for multiple SDI lines.
By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines. The supported number of SDI lines are: 1, 2, 3 and 4.main
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8b95520767
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a147acd791
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@ -42,7 +42,7 @@ module axi_spi_engine (
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output sdi_data_ready,
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input sdi_data_valid,
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input [7:0] sdi_data,
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input [(SDI_DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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@ -72,7 +72,9 @@ parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4;
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4;
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parameter ID = 'h00;
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localparam PCORE_VERSION = 'h010061;
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parameter SDI_DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
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localparam PCORE_VERSION = 'h010071;
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wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
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wire cmd_fifo_almost_empty;
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@ -307,7 +309,7 @@ assign sdi_fifo_almost_full =
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`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
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util_axis_fifo #(
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.DATA_WIDTH(8),
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.DATA_WIDTH(SDI_DATA_WIDTH),
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.ASYNC_CLK(ASYNC_SPI_CLK),
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.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
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.S_AXIS_REGISTERED(0)
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@ -15,7 +15,7 @@ module spi_engine_execution (
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input sdi_data_ready,
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output reg sdi_data_valid,
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output [7:0] sdi_data,
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output [(SDI_DATA_WIDTH-1):0] sdi_data,
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input sync_ready,
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output reg sync_valid,
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@ -25,6 +25,9 @@ module spi_engine_execution (
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output sdo,
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output reg sdo_t,
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input sdi,
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input sdi_1,
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input sdi_2,
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input sdi_3,
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output reg [NUM_OF_CS-1:0] cs,
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output reg three_wire
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);
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@ -32,7 +35,10 @@ module spi_engine_execution (
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parameter NUM_OF_CS = 1;
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parameter DEFAULT_SPI_CFG = 0;
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parameter DEFAULT_CLK_DIV = 0;
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parameter SDI_DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
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localparam NUM_OF_SDI = SDI_DATA_WIDTH >> 3;
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localparam CMD_TRANSFER = 2'b00;
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localparam CMD_CHIPSELECT = 2'b01;
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localparam CMD_WRITE = 2'b10;
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@ -83,6 +89,9 @@ wire sdo_enabled = cmd_d1[8];
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wire sdi_enabled = cmd_d1[9];
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reg [8:0] data_shift = 'h0;
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reg [8:0] data_shift_1 = 'h0;
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reg [8:0] data_shift_2 = 'h0;
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reg [8:0] data_shift_3 = 'h0;
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wire [1:0] inst = cmd[13:12];
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wire [1:0] inst_d1 = cmd_d1[13:12];
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@ -290,15 +299,25 @@ always @(posedge clk) begin
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data_shift[8:1] <= sdo_data;
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else
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data_shift[8:1] <= data_shift[7:0];
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data_shift_1[8:1] <= data_shift_1[7:0];
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data_shift_2[8:1] <= data_shift_2[7:0];
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data_shift_3[8:1] <= data_shift_3[7:0];
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end
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end
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assign sdo = data_shift[8];
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assign sdi_data = data_shift[7:0];
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assign sdi_data = (NUM_OF_SDI == 1) ? data_shift[7:0] :
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(NUM_OF_SDI == 2) ? {data_shift_1[7:0], data_shift[7:0]} :
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(NUM_OF_SDI == 3) ? {data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
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(NUM_OF_SDI == 4) ? {data_shift_3[7:0], data_shift_2[7:0], data_shift_1[7:0], data_shift[7:0]} :
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data_shift[7:0];
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always @(posedge clk) begin
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if (trigger_rx == 1'b1) begin
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data_shift[0] <= sdi;
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data_shift_1[0] <= sdi_1;
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data_shift_2[0] <= sdi_2;
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data_shift_3[0] <= sdi_3;
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end
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end
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@ -14,7 +14,7 @@ module spi_engine_interconnect (
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input m_sdi_valid,
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output m_sdi_ready,
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input [7:0] m_sdi_data,
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input [(SDI_DATA_WIDTH-1):0] m_sdi_data,
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input m_sync_valid,
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output m_sync_ready,
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@ -31,7 +31,7 @@ module spi_engine_interconnect (
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output s0_sdi_valid,
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input s0_sdi_ready,
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output [7:0] s0_sdi_data,
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output [(SDI_DATA_WIDTH-1):0] s0_sdi_data,
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output s0_sync_valid,
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input s0_sync_ready,
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@ -48,13 +48,15 @@ module spi_engine_interconnect (
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output s1_sdi_valid,
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input s1_sdi_ready,
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output [7:0] s1_sdi_data,
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output [(SDI_DATA_WIDTH-1):0] s1_sdi_data,
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output s1_sync_valid,
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input s1_sync_ready,
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output [7:0] s1_sync
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);
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parameter SDI_DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
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reg s_active = 1'b0;
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reg idle = 1'b1;
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@ -27,7 +27,7 @@ module spi_engine_offload (
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input sdi_data_valid,
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output sdi_data_ready,
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input [7:0] sdi_data,
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input [(SDI_DATA_WIDTH-1):0] sdi_data,
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input sync_valid,
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output sync_ready,
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@ -35,12 +35,13 @@ module spi_engine_offload (
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output offload_sdi_valid,
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input offload_sdi_ready,
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output [7:0] offload_sdi_data
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output [(SDI_DATA_WIDTH-1):0] offload_sdi_data
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);
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parameter ASYNC_SPI_CLK = 0;
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parameter CMD_MEM_ADDRESS_WIDTH = 4;
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parameter SDO_MEM_ADDRESS_WIDTH = 4;
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parameter SDI_DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
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reg spi_active = 1'b0;
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