util_dec256sinc24b: Avoid generated clock from logic
Do not use word_clk, create a clock enable signal instead.main
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59ce663479
commit
a15afa6c03
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@ -57,7 +57,7 @@ module util_dec256sinc24b (
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reg [36:0] diff1_d = 37'h0;
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reg [36:0] diff1_d = 37'h0;
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reg [36:0] diff2_d = 37'h0;
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reg [36:0] diff2_d = 37'h0;
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reg [15:0] word_count = 16'h0;
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reg [15:0] word_count = 16'h0;
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reg word_clk = 1'b0;
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reg word_en = 1'b0;
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reg enable = 1'b0;
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reg enable = 1'b0;
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/* Perform the Sinc action */
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/* Perform the Sinc action */
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@ -88,6 +88,7 @@ module util_dec256sinc24b (
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end
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end
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/* decimation stage (MCLKOUT/WORD_CLK) */
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/* decimation stage (MCLKOUT/WORD_CLK) */
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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if (reset == 1'b1) begin
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word_count <= 16'd0;
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word_count <= 16'd0;
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@ -101,20 +102,20 @@ module util_dec256sinc24b (
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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if (reset == 1'b1) begin
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word_clk <= 1'b0;
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word_en <= 1'b0;
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end else begin
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end else begin
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if (word_count == (dec_rate/2 - 1))
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if (word_count == (dec_rate/2 - 1))
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word_clk <= 1'b1;
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word_en <= 1'b1;
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else if (word_count == (dec_rate - 1))
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else
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word_clk <= 1'b0;
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word_en <= 1'b0;
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end
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end
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end
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end
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/* Differentiator (including decimation stage)
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/* Differentiator (including decimation stage)
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* Perform the differentiation stage (FIR) at a lower speed.
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* Perform the differentiation stage (FIR) at a lower speed.
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* Z = one sample delay WORD_CLK = output word rate */
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* Z = one sample delay WORD_EN = output word rate */
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always @(posedge word_clk) begin
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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if (reset == 1'b1) begin
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acc3_d <= 37'd0;
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acc3_d <= 37'd0;
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diff1_d <= 37'd0;
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diff1_d <= 37'd0;
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@ -122,7 +123,7 @@ module util_dec256sinc24b (
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diff1 <= 37'd0;
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diff1 <= 37'd0;
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diff2 <= 37'd0;
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diff2 <= 37'd0;
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diff3 <= 37'd0;
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diff3 <= 37'd0;
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end else begin
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end else if (word_en == 1'b1) begin
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diff1 <= acc3 - acc3_d;
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diff1 <= acc3 - acc3_d;
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diff2 <= diff1 - diff1_d;
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diff2 <= diff1 - diff1_d;
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diff3 <= diff2 - diff2_d;
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diff3 <= diff2 - diff2_d;
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@ -133,47 +134,49 @@ module util_dec256sinc24b (
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end
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end
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/* Clock the Sinc output into an output register
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/* Clock the Sinc output into an output register
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* WORD_CLK = output word rate */
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* WORD_EN = output word rate */
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always @(posedge word_clk) begin
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always @(posedge clk) begin
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case (dec_rate)
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if (word_en == 1'b1) begin
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case (dec_rate)
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16'd32: begin
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16'd32: begin
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data_out <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
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data_out <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
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end
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end
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16'd64: begin
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16'd64: begin
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data_out <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2];
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data_out <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2];
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end
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end
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16'd128: begin
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16'd128: begin
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data_out <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5];
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data_out <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5];
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end
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end
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16'd256: begin
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16'd256: begin
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data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
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data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
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end
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end
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16'd512: begin
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16'd512: begin
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data_out <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11];
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data_out <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11];
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end
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end
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16'd1024: begin
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16'd1024: begin
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data_out <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14];
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data_out <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14];
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end
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end
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16'd2048: begin
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16'd2048: begin
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data_out <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17];
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data_out <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17];
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end
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end
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16'd4096: begin
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16'd4096: begin
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data_out <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20];
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data_out <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20];
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end
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end
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default:begin
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default:begin
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data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
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data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
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end
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end
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endcase
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endcase
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end
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end
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end
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/* Synchronize Data Output */
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/* Synchronize Data Output */
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