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util_dec256sinc24b: Avoid generated clock from logic 

Do not use word_clk, create a clock enable signal instead.
main
Istvan Csomortani 2018-01-11 15:45:44 +00:00 committed by István Csomortáni
parent 59ce663479
commit a15afa6c03
1 changed files with 42 additions and 39 deletions
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23
library/common/util_dec256sinc24b.v
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@ -57,7 +57,7 @@ module util_dec256sinc24b (
reg [36:0] diff1_d = 37'h0;
reg [36:0] diff2_d = 37'h0;
reg [15:0] word_count = 16'h0;
reg word_clk = 1'b0;
reg word_en = 1'b0;
reg enable = 1'b0;
/* Perform the Sinc action */
@ -88,6 +88,7 @@ module util_dec256sinc24b (
end
/* decimation stage (MCLKOUT/WORD_CLK) */
always @(posedge clk) begin
if (reset == 1'b1) begin
word_count <= 16'd0;
@ -101,20 +102,20 @@ module util_dec256sinc24b (
always @(posedge clk) begin
if (reset == 1'b1) begin
word_clk <= 1'b0;
word_en <= 1'b0;
end else begin
if (word_count == (dec_rate/2 - 1))
word_clk <= 1'b1;
else if (word_count == (dec_rate - 1))
word_clk <= 1'b0;
word_en <= 1'b1;
else
word_en <= 1'b0;
end
end
/* Differentiator (including decimation stage)
* Perform the differentiation stage (FIR) at a lower speed.
* Z = one sample delay WORD_CLK = output word rate */
* Z = one sample delay WORD_EN = output word rate */
always @(posedge word_clk) begin
always @(posedge clk) begin
if (reset == 1'b1) begin
acc3_d <= 37'd0;
diff1_d <= 37'd0;
@ -122,7 +123,7 @@ module util_dec256sinc24b (
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end else begin
end else if (word_en == 1'b1) begin
diff1 <= acc3 - acc3_d;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
@ -133,9 +134,10 @@ module util_dec256sinc24b (
end
/* Clock the Sinc output into an output register
* WORD_CLK = output word rate */
* WORD_EN = output word rate */
always @(posedge word_clk) begin
always @(posedge clk) begin
if (word_en == 1'b1) begin
case (dec_rate)
16'd32: begin
@ -175,6 +177,7 @@ module util_dec256sinc24b (
end
endcase
end
end
/* Synchronize Data Output */