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a5gt/a5soc - removed

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Rejeesh Kutty 2017-06-15 11:40:58 -04:00
parent 9e2d55ed07
commit a23fb793a0
8 changed files with 0 additions and 2428 deletions
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projects/common/a5gt/a5gt_system_assign.tcl
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# a5gx carrier defaults
# clocks and resets
set_location_assignment PIN_C34 -to sys_clk
set_location_assignment PIN_D34 -to "sys_clk(n)"
set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sys_clk -disable
set_location_assignment PIN_L6 -to sys_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to sys_resetn
# ddr3
set_location_assignment PIN_B31 -to ddr3_a[0]
set_location_assignment PIN_A30 -to ddr3_a[1]
set_location_assignment PIN_A31 -to ddr3_a[2]
set_location_assignment PIN_A32 -to ddr3_a[3]
set_location_assignment PIN_A33 -to ddr3_a[4]
set_location_assignment PIN_B33 -to ddr3_a[5]
set_location_assignment PIN_H31 -to ddr3_a[6]
set_location_assignment PIN_J31 -to ddr3_a[7]
set_location_assignment PIN_C31 -to ddr3_a[8]
set_location_assignment PIN_D31 -to ddr3_a[9]
set_location_assignment PIN_C32 -to ddr3_a[10]
set_location_assignment PIN_D32 -to ddr3_a[11]
set_location_assignment PIN_N31 -to ddr3_a[12]
set_location_assignment PIN_P31 -to ddr3_a[13]
set_location_assignment PIN_M32 -to ddr3_ba[0]
set_location_assignment PIN_N32 -to ddr3_ba[1]
set_location_assignment PIN_J34 -to ddr3_ba[2]
set_location_assignment PIN_B30 -to ddr3_clk_p
set_location_assignment PIN_C30 -to ddr3_clk_n
set_location_assignment PIN_E31 -to ddr3_cke
set_location_assignment PIN_L34 -to ddr3_cs_n
set_location_assignment PIN_K34 -to ddr3_ras_n
set_location_assignment PIN_L33 -to ddr3_cas_n
set_location_assignment PIN_M33 -to ddr3_we_n
set_location_assignment PIN_G30 -to ddr3_reset_n
set_location_assignment PIN_L31 -to ddr3_odt
set_location_assignment PIN_F33 -to ddr3_rzq
set_location_assignment PIN_N30 -to ddr3_dqs_p[0]
set_location_assignment PIN_P30 -to ddr3_dqs_n[0]
set_location_assignment PIN_R29 -to ddr3_dqs_p[1]
set_location_assignment PIN_T29 -to ddr3_dqs_n[1]
set_location_assignment PIN_J30 -to ddr3_dm[0]
set_location_assignment PIN_J29 -to ddr3_dm[1]
set_location_assignment PIN_B28 -to ddr3_dq[0]
set_location_assignment PIN_C29 -to ddr3_dq[1]
set_location_assignment PIN_R30 -to ddr3_dq[2]
set_location_assignment PIN_A29 -to ddr3_dq[3]
set_location_assignment PIN_A28 -to ddr3_dq[4]
set_location_assignment PIN_L30 -to ddr3_dq[5]
set_location_assignment PIN_D30 -to ddr3_dq[6]
set_location_assignment PIN_D29 -to ddr3_dq[7]
set_location_assignment PIN_L28 -to ddr3_dq[8]
set_location_assignment PIN_M28 -to ddr3_dq[9]
set_location_assignment PIN_H28 -to ddr3_dq[10]
set_location_assignment PIN_C28 -to ddr3_dq[11]
set_location_assignment PIN_D28 -to ddr3_dq[12]
set_location_assignment PIN_F28 -to ddr3_dq[13]
set_location_assignment PIN_M29 -to ddr3_dq[14]
set_location_assignment PIN_N29 -to ddr3_dq[15]
set_location_assignment PIN_R28 -to ddr3_dqs_p[2]
set_location_assignment PIN_T28 -to ddr3_dqs_n[2]
set_location_assignment PIN_M26 -to ddr3_dqs_p[3]
set_location_assignment PIN_N26 -to ddr3_dqs_n[3]
set_location_assignment PIN_K27 -to ddr3_dm[2]
set_location_assignment PIN_J26 -to ddr3_dm[3]
set_location_assignment PIN_P27 -to ddr3_dq[16]
set_location_assignment PIN_R27 -to ddr3_dq[17]
set_location_assignment PIN_H27 -to ddr3_dq[18]
set_location_assignment PIN_B27 -to ddr3_dq[19]
set_location_assignment PIN_C27 -to ddr3_dq[20]
set_location_assignment PIN_E27 -to ddr3_dq[21]
set_location_assignment PIN_M27 -to ddr3_dq[22]
set_location_assignment PIN_N27 -to ddr3_dq[23]
set_location_assignment PIN_C26 -to ddr3_dq[24]
set_location_assignment PIN_D26 -to ddr3_dq[25]
set_location_assignment PIN_K25 -to ddr3_dq[26]
set_location_assignment PIN_R26 -to ddr3_dq[27]
set_location_assignment PIN_T27 -to ddr3_dq[28]
set_location_assignment PIN_A26 -to ddr3_dq[29]
set_location_assignment PIN_F26 -to ddr3_dq[30]
set_location_assignment PIN_G26 -to ddr3_dq[31]
set_location_assignment PIN_A20 -to ddr3_dqs_p[4]
set_location_assignment PIN_B21 -to ddr3_dqs_n[4]
set_location_assignment PIN_C23 -to ddr3_dqs_p[5]
set_location_assignment PIN_D23 -to ddr3_dqs_n[5]
set_location_assignment PIN_M21 -to ddr3_dm[4]
set_location_assignment PIN_B22 -to ddr3_dm[5]
set_location_assignment PIN_D20 -to ddr3_dq[32]
set_location_assignment PIN_H21 -to ddr3_dq[33]
set_location_assignment PIN_D21 -to ddr3_dq[34]
set_location_assignment PIN_J21 -to ddr3_dq[35]
set_location_assignment PIN_A21 -to ddr3_dq[36]
set_location_assignment PIN_G21 -to ddr3_dq[37]
set_location_assignment PIN_A22 -to ddr3_dq[38]
set_location_assignment PIN_C20 -to ddr3_dq[39]
set_location_assignment PIN_A23 -to ddr3_dq[40]
set_location_assignment PIN_E22 -to ddr3_dq[41]
set_location_assignment PIN_L22 -to ddr3_dq[42]
set_location_assignment PIN_C22 -to ddr3_dq[43]
set_location_assignment PIN_N22 -to ddr3_dq[44]
set_location_assignment PIN_F22 -to ddr3_dq[45]
set_location_assignment PIN_P22 -to ddr3_dq[46]
set_location_assignment PIN_J22 -to ddr3_dq[47]
set_location_assignment PIN_D24 -to ddr3_dqs_p[6]
set_location_assignment PIN_E24 -to ddr3_dqs_n[6]
set_location_assignment PIN_A25 -to ddr3_dqs_p[7]
set_location_assignment PIN_B25 -to ddr3_dqs_n[7]
set_location_assignment PIN_J23 -to ddr3_dm[6]
set_location_assignment PIN_D25 -to ddr3_dm[7]
set_location_assignment PIN_C24 -to ddr3_dq[48]
set_location_assignment PIN_M23 -to ddr3_dq[49]
set_location_assignment PIN_B24 -to ddr3_dq[50]
set_location_assignment PIN_R23 -to ddr3_dq[51]
set_location_assignment PIN_G24 -to ddr3_dq[52]
set_location_assignment PIN_G23 -to ddr3_dq[53]
set_location_assignment PIN_F24 -to ddr3_dq[54]
set_location_assignment PIN_F23 -to ddr3_dq[55]
set_location_assignment PIN_R24 -to ddr3_dq[56]
set_location_assignment PIN_G25 -to ddr3_dq[57]
set_location_assignment PIN_T26 -to ddr3_dq[58]
set_location_assignment PIN_E25 -to ddr3_dq[59]
set_location_assignment PIN_N24 -to ddr3_dq[60]
set_location_assignment PIN_K24 -to ddr3_dq[61]
set_location_assignment PIN_T25 -to ddr3_dq[62]
set_location_assignment PIN_P24 -to ddr3_dq[63]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_p
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_reset_n
set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_rzq
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[5]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[40]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[41]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[42]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[43]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[44]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[45]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[46]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[47]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[6]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[7]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[48]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[49]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[50]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[52]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[53]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[54]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[55]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[56]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[57]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[58]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[59]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[60]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[61]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[62]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[63]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dm[0]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dm[1]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[0]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[1]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[2]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[3]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[4]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[5]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[6]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[7]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[8]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[9]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[10]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[11]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[12]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[13]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[14]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[15]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dm[2]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dm[3]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[16]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[17]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[18]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[19]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[20]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[21]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[22]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[23]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[24]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[25]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[26]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[27]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[28]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[29]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[30]
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_p
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_n
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_p
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cke
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cs_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ras_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cas_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_we_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_reset_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_odt
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[14]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[15]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[16]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[17]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[18]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[19]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[20]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[21]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[22]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[23]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[24]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[25]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[26]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[27]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[28]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[29]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[30]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[31]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[32]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[33]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[34]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[35]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[36]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[37]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[38]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[39]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[40]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[41]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[42]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[43]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[44]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[45]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[46]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[47]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[48]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[49]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[50]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[51]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[52]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[53]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[54]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[55]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[56]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[57]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[58]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[59]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[60]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[61]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[62]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[63]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[0]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[1]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[4]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[5]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[6]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[7]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[8]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[9]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[10]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[11]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[12]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[13]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[14]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[15]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[2]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[3]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[16]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[17]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[18]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[19]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[20]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[21]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[22]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[23]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[24]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[25]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[26]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[27]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[28]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[29]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30]
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31]
# ethernet interface
set_location_assignment PIN_A6 -to eth_rx_clk
set_location_assignment PIN_B6 -to "eth_rx_clk(n)"
set_location_assignment PIN_D13 -to eth_rx_cntrl
set_location_assignment PIN_E13 -to "eth_rx_cntrl(n)"
set_location_assignment PIN_A13 -to eth_rx_data[0]
set_location_assignment PIN_A12 -to "eth_rx_data[0](n)"
set_location_assignment PIN_D12 -to eth_rx_data[1]
set_location_assignment PIN_E12 -to "eth_rx_data[1](n)"
set_location_assignment PIN_P13 -to eth_rx_data[2]
set_location_assignment PIN_R13 -to "eth_rx_data[2](n)"
set_location_assignment PIN_B10 -to eth_rx_data[3]
set_location_assignment PIN_C10 -to "eth_rx_data[3](n)"
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_clk
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_cntrl
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_data
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_clk
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_cntrl
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_data
set_location_assignment PIN_H18 -to eth_tx_clk_out
set_location_assignment PIN_J18 -to "eth_tx_clk_out(n)"
set_location_assignment PIN_J11 -to eth_tx_cntrl
set_location_assignment PIN_K11 -to "eth_tx_cntrl(n)"
set_location_assignment PIN_K12 -to eth_tx_data[0]
set_location_assignment PIN_L12 -to "eth_tx_data[0](n)"
set_location_assignment PIN_F12 -to eth_tx_data[1]
set_location_assignment PIN_G12 -to "eth_tx_data[1](n)"
set_location_assignment PIN_H10 -to eth_tx_data[2]
set_location_assignment PIN_J10 -to "eth_tx_data[2](n)"
set_location_assignment PIN_A14 -to eth_tx_data[3]
set_location_assignment PIN_B13 -to "eth_tx_data[3](n)"
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_clk_out
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_cntrl
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_data
set_location_assignment PIN_E15 -to eth_mdc
set_location_assignment PIN_F15 -to eth_mdio_i
set_location_assignment PIN_G16 -to eth_mdio_o
set_location_assignment PIN_H16 -to eth_mdio_t
set_location_assignment PIN_K18 -to eth_phy_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_phy_resetn
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_rx_clk
# leds
set_location_assignment PIN_M19 -to gpio_bd_o[0] ; ## led_grn[0]
set_location_assignment PIN_L19 -to gpio_bd_o[1] ; ## led_grn[1]
set_location_assignment PIN_K19 -to gpio_bd_o[2] ; ## led_grn[2]
set_location_assignment PIN_J19 -to gpio_bd_o[3] ; ## led_grn[3]
set_location_assignment PIN_K20 -to gpio_bd_o[4] ; ## led_grn[4]
set_location_assignment PIN_J20 -to gpio_bd_o[5] ; ## led_grn[5]
set_location_assignment PIN_T20 -to gpio_bd_o[6] ; ## led_grn[6]
set_location_assignment PIN_R20 -to gpio_bd_o[7] ; ## led_grn[7]
set_location_assignment PIN_N20 -to gpio_bd_o[8] ; ## led_red[0]
set_location_assignment PIN_C15 -to gpio_bd_o[9] ; ## led_red[1]
set_location_assignment PIN_AL28 -to gpio_bd_o[10] ; ## led_red[2]
set_location_assignment PIN_F11 -to gpio_bd_o[11] ; ## led_red[3]
set_location_assignment PIN_AJ31 -to gpio_bd_o[12] ; ## led_red[4]
set_location_assignment PIN_AN34 -to gpio_bd_o[13] ; ## led_red[5]
set_location_assignment PIN_AJ34 -to gpio_bd_o[14] ; ## led_red[6]
set_location_assignment PIN_AK33 -to gpio_bd_o[15] ; ## led_red[7]
set_location_assignment PIN_C8 -to gpio_bd_i[0] ; ## dip_switches[0]
set_location_assignment PIN_D8 -to gpio_bd_i[1] ; ## dip_switches[1]
set_location_assignment PIN_E7 -to gpio_bd_i[2] ; ## dip_switches[2]
set_location_assignment PIN_E6 -to gpio_bd_i[3] ; ## dip_switches[3]
set_location_assignment PIN_G8 -to gpio_bd_i[4] ; ## dip_switches[4]
set_location_assignment PIN_F8 -to gpio_bd_i[5] ; ## dip_switches[5]
set_location_assignment PIN_D15 -to gpio_bd_i[6] ; ## dip_switches[6]
set_location_assignment PIN_G11 -to gpio_bd_i[7] ; ## dip_switches[7]
set_location_assignment PIN_D6 -to gpio_bd_i[8] ; ## push_buttons[0]
set_location_assignment PIN_C6 -to gpio_bd_i[9] ; ## push_buttons[1]
set_location_assignment PIN_K7 -to gpio_bd_i[10] ; ## push_buttons[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[10]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[11]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[12]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[13]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[14]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[15]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[8]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[9]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10]
set_instance_assignment -name OPTIMIZATION_TECHNIQUE SPEED -to *
set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -to *
set_location_assignment FF_X25_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X25_Y136_N1 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X15_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X15_Y136_N2 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X18_Y136_N5 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X18_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X18_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][2]
set_location_assignment FF_X18_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][3]
set_location_assignment FF_X18_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][4]
set_location_assignment FF_X18_Y136_N29 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][5]
set_location_assignment FF_X25_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X25_Y136_N17 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X25_Y136_N50 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][2]
set_location_assignment FF_X25_Y136_N44 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][3]
set_location_assignment FF_X21_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][4]
set_location_assignment FF_X21_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][5]
set_location_assignment FF_X21_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][6]
set_location_assignment FF_X21_Y136_N16 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][7]
set_location_assignment FF_X20_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][8]
set_location_assignment FF_X20_Y136_N37 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][9]
set_location_assignment FF_X20_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][10]
set_location_assignment FF_X20_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][11]
set_location_assignment FF_X18_Y136_N22 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][12]
set_location_assignment FF_X25_Y136_N41 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][13]
set_location_assignment FF_X25_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][14]
set_location_assignment FF_X25_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][15]
set_location_assignment FF_X25_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][16]
set_location_assignment FF_X21_Y136_N58 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][17]
set_location_assignment FF_X21_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][18]
set_location_assignment FF_X21_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][19]
set_location_assignment FF_X21_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][20]
set_location_assignment FF_X20_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][21]
set_location_assignment FF_X20_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][22]
set_location_assignment FF_X20_Y136_N25 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][23]
set_location_assignment FF_X20_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][24]
set_location_assignment FF_X18_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][25]
set_location_assignment FF_X28_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X28_Y136_N26 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X18_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X18_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X15_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X15_Y136_N34 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X15_Y136_N52 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X15_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][1]
set_location_assignment FF_X15_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][0]
set_location_assignment FF_X15_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][1]

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projects/common/a5gt/a5gt_system_qsys.tcl
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@ -1,359 +0,0 @@
# a5gx carrier qsys
set system_type nios
# clock-&-reset
add_instance sys_ref_clk clock_source
add_interface sys_ref_clk clock sink
add_interface sys_ref_rst reset sink
set_interface_property sys_ref_clk EXPORT_OF sys_ref_clk.clk_in
set_interface_property sys_ref_rst EXPORT_OF sys_ref_clk.clk_in_reset
set_instance_parameter_value sys_ref_clk {clockFrequency} {100000000.0}
set_instance_parameter_value sys_ref_clk {clockFrequencyKnown} {1}
set_instance_parameter_value sys_ref_clk {resetSynchronousEdges} {DEASSERT}
add_instance sys_clk clock_source
add_interface sys_clk clock sink
add_interface sys_rst reset sink
set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
# system-pll
add_instance sys_pll altera_pll
set_instance_parameter_value sys_pll {gui_reference_clock_frequency} {100.0}
set_instance_parameter_value sys_pll {gui_use_locked} {1}
set_instance_parameter_value sys_pll {gui_number_of_clocks} {3}
set_instance_parameter_value sys_pll {gui_output_clock_frequency0} {125.0}
set_instance_parameter_value sys_pll {gui_output_clock_frequency1} {25.0}
set_instance_parameter_value sys_pll {gui_output_clock_frequency2} {2.5}
add_connection sys_ref_clk.clk sys_pll.refclk
add_connection sys_ref_clk.clk_reset sys_pll.reset
add_interface sys_125m_clk clock source
add_interface sys_25m_clk clock source
add_interface sys_2m5_clk clock source
add_interface sys_pll_locked conduit end
set_interface_property sys_125m_clk EXPORT_OF sys_pll.outclk0
set_interface_property sys_25m_clk EXPORT_OF sys_pll.outclk1
set_interface_property sys_2m5_clk EXPORT_OF sys_pll.outclk2
set_interface_property sys_pll_locked EXPORT_OF sys_pll.locked
# memory (int)
add_instance sys_int_mem altera_avalon_onchip_memory2
set_instance_parameter_value sys_int_mem {dataWidth} {32}
set_instance_parameter_value sys_int_mem {dualPort} {0}
set_instance_parameter_value sys_int_mem {initMemContent} {0}
set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
add_connection sys_clk.clk sys_int_mem.clk1
add_connection sys_clk.clk_reset sys_int_mem.reset1
# memory (tlb)
add_instance sys_tlb_mem altera_avalon_onchip_memory2
set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
set_instance_parameter_value sys_tlb_mem {dualPort} {1}
set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
add_connection sys_clk.clk sys_tlb_mem.clk1
add_connection sys_clk.clk_reset sys_tlb_mem.reset1
add_connection sys_clk.clk sys_tlb_mem.clk2
add_connection sys_clk.clk_reset sys_tlb_mem.reset2
# memory (ddr)
add_instance sys_ddr3_cntrl altera_mem_if_ddr3_emif
set_instance_parameter_value sys_ddr3_cntrl {SPEED_GRADE} {3}
set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ} {400.0}
set_instance_parameter_value sys_ddr3_cntrl {REF_CLK_FREQ} {100.0}
set_instance_parameter_value sys_ddr3_cntrl {RATE} {Quarter}
set_instance_parameter_value sys_ddr3_cntrl {EXPORT_AFI_HALF_CLK} {1}
set_instance_parameter_value sys_ddr3_cntrl {MEM_VENDOR} {Micron}
set_instance_parameter_value sys_ddr3_cntrl {MEM_CLK_FREQ_MAX} {666.667}
set_instance_parameter_value sys_ddr3_cntrl {MEM_DQ_WIDTH} {64}
set_instance_parameter_value sys_ddr3_cntrl {MEM_ROW_ADDR_WIDTH} {12}
set_instance_parameter_value sys_ddr3_cntrl {MEM_COL_ADDR_WIDTH} {10}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TCL} {11}
set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_NOM} {RZQ/6}
set_instance_parameter_value sys_ddr3_cntrl {MEM_WTCL} {8}
set_instance_parameter_value sys_ddr3_cntrl {MEM_RTT_WR} {RZQ/4}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIS} {170}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TIH} {120}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDS} {10}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDH} {45}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSQ} {100}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQH} {0.38}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSCK} {255}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDQSS} {0.27}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TQSH} {0.4}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSH} {0.18}
set_instance_parameter_value sys_ddr3_cntrl {TIMING_TDSS} {0.18}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TINIT_US} {500}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TMRD_CK} {4}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRAS_NS} {35.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRCD_NS} {13.75}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRP_NS} {13.75}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TREFI_US} {7.8}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRFC_NS} {110.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TWR_NS} {15.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TWTR} {6}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TFAW_NS} {30.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRRD_NS} {6.0}
set_instance_parameter_value sys_ddr3_cntrl {MEM_TRTP_NS} {7.5}
set_instance_parameter_value sys_ddr3_cntrl {AVL_MAX_SIZE} {256}
add_connection sys_ref_clk.clk sys_ddr3_cntrl.pll_ref_clk
add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.global_reset
add_connection sys_ref_clk.clk_reset sys_ddr3_cntrl.soft_reset
add_interface sys_ddr3_cntrl_mem conduit end
set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.memory
add_interface sys_ddr3_cntrl_oct conduit end
set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
# cpu clock
add_instance sys_cpu_clk clock_source
add_connection sys_ddr3_cntrl.afi_half_clk sys_cpu_clk.clk_in
add_connection sys_ddr3_cntrl.afi_reset sys_cpu_clk.clk_in_reset
add_interface sys_cpu_clk clock source
set_interface_property sys_cpu_clk EXPORT_OF sys_cpu_clk.clk
add_interface sys_cpu_reset reset source
set_interface_property sys_cpu_reset EXPORT_OF sys_cpu_clk.clk_reset
# cpu
add_instance sys_cpu altera_nios2_gen2
set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0}
set_instance_parameter_value sys_cpu {setting_activateTrace} {1}
set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0}
set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096}
set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl.avl}
set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2}
set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl.avl}
set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module}
set_instance_parameter_value sys_cpu {mul_32_impl} {3}
set_instance_parameter_value sys_cpu {shift_rot_impl} {0}
set_instance_parameter_value sys_cpu {icache_size} {32768}
set_instance_parameter_value sys_cpu {icache_numTCIM} {1}
set_instance_parameter_value sys_cpu {dcache_size} {32768}
set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled
add_connection sys_clk.clk sys_cpu.clk
add_connection sys_clk.clk_reset sys_cpu.reset
add_connection sys_cpu.debug_reset_request sys_cpu.reset
add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
add_connection sys_cpu.instruction_master sys_int_mem.s1
add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
add_connection sys_cpu.instruction_master sys_ddr3_cntrl.avl
add_connection sys_cpu.data_master sys_ddr3_cntrl.avl
set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.avl baseAddress {0x0}
set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.avl baseAddress {0x0}
set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
# cpu/hps handling
proc ad_cpu_interrupt {m_irq m_port} {
add_connection sys_cpu.irq ${m_port}
set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq}
}
proc ad_cpu_interconnect {m_base m_port} {
add_connection sys_cpu.data_master ${m_port}
set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)]
}
proc ad_dma_interconnect {m_port} {
add_connection ${m_port} sys_ddr3_cntrl.avl
set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.avl baseAddress {0x0}
}
# common dma interfaces
add_instance sys_dma_clk clock_source
add_connection sys_ddr3_cntrl.afi_clk sys_dma_clk.clk_in
add_connection sys_ddr3_cntrl.afi_reset sys_dma_clk.clk_in_reset
# ethernet
add_instance sys_ethernet altera_eth_tse
set_instance_parameter_value sys_ethernet {core_variation} {MAC_ONLY}
set_instance_parameter_value sys_ethernet {ifGMII} {RGMII}
set_instance_parameter_value sys_ethernet {enable_mac_flow_ctrl} {1}
set_instance_parameter_value sys_ethernet {useMDIO} {1}
set_instance_parameter_value sys_ethernet {mdio_clk_div} {30}
add_instance sys_ethernet_dma_rx altera_msgdma
set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2}
set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64}
set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256}
set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512}
set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0}
set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048}
set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses}
set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64}
set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1}
set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6}
add_instance sys_ethernet_dma_tx altera_msgdma
set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1}
set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64}
set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256}
set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512}
set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048}
set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses}
set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64}
set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1}
set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1}
set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1}
add_connection sys_clk.clk_reset sys_ethernet.reset_connection
add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n
add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n
add_connection sys_clk.clk sys_ethernet.control_port_clock_connection
add_connection sys_clk.clk sys_ethernet.receive_clock_connection
add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
add_connection sys_clk.clk sys_ethernet_dma_rx.clock
add_connection sys_clk.clk sys_ethernet_dma_tx.clock
add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
add_interface sys_ethernet_rx_clk clock sink
add_interface sys_ethernet_tx_clk clock sink
add_interface sys_ethernet_rgmii conduit end
add_interface sys_ethernet_mdio conduit end
add_interface sys_ethernet_status conduit end
set_interface_property sys_ethernet_rx_clk EXPORT_OF sys_ethernet.pcs_mac_rx_clock_connection
set_interface_property sys_ethernet_tx_clk EXPORT_OF sys_ethernet.pcs_mac_tx_clock_connection
set_interface_property sys_ethernet_status EXPORT_OF sys_ethernet.mac_status_connection
set_interface_property sys_ethernet_rgmii EXPORT_OF sys_ethernet.mac_rgmii_connection
set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection
# sys-id
add_instance sys_id altera_avalon_sysid_qsys
set_instance_parameter_value sys_id {id} {182193580}
add_connection sys_clk.clk_reset sys_id.reset
add_connection sys_clk.clk sys_id.clk
# timer-1
add_instance sys_timer_1 altera_avalon_timer
set_instance_parameter_value sys_timer_1 {counterSize} {32}
add_connection sys_clk.clk_reset sys_timer_1.reset
add_connection sys_clk.clk sys_timer_1.clk
# timer-2
add_instance sys_timer_2 altera_avalon_timer
set_instance_parameter_value sys_timer_2 {counterSize} {32}
add_connection sys_clk.clk_reset sys_timer_2.reset
add_connection sys_clk.clk sys_timer_2.clk
# uart
add_instance sys_uart altera_avalon_jtag_uart
set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
add_connection sys_clk.clk_reset sys_uart.reset
add_connection sys_clk.clk sys_uart.clk
# gpio-bd
add_instance sys_gpio_bd altera_avalon_pio
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
set_instance_parameter_value sys_gpio_bd {width} {32}
add_connection sys_clk.clk_reset sys_gpio_bd.reset
add_connection sys_clk.clk sys_gpio_bd.clk
add_interface sys_gpio_bd conduit end
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
# gpio-in
add_instance sys_gpio_in altera_avalon_pio
set_instance_parameter_value sys_gpio_in {direction} {Input}
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
set_instance_parameter_value sys_gpio_in {width} {32}
add_connection sys_clk.clk_reset sys_gpio_in.reset
add_connection sys_clk.clk sys_gpio_in.clk
add_interface sys_gpio_in conduit end
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
# gpio-out
add_instance sys_gpio_out altera_avalon_pio
set_instance_parameter_value sys_gpio_out {direction} {Output}
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
set_instance_parameter_value sys_gpio_out {width} {32}
add_connection sys_clk.clk_reset sys_gpio_out.reset
add_connection sys_clk.clk sys_gpio_out.clk
add_interface sys_gpio_out conduit end
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
# spi
add_instance sys_spi altera_avalon_spi
set_instance_parameter_value sys_spi {clockPhase} {0}
set_instance_parameter_value sys_spi {clockPolarity} {0}
set_instance_parameter_value sys_spi {dataWidth} {8}
set_instance_parameter_value sys_spi {masterSPI} {1}
set_instance_parameter_value sys_spi {numberOfSlaves} {8}
set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
add_connection sys_clk.clk_reset sys_spi.reset
add_connection sys_clk.clk sys_spi.clk
add_interface sys_spi conduit end
set_interface_property sys_spi EXPORT_OF sys_spi.external
# base-addresses
ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave
ad_cpu_interconnect 0x00140000 sys_int_mem.s1
ad_cpu_interconnect 0x00181000 sys_ethernet.control_port
ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr
ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response
ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave
ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr
ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave
ad_cpu_interconnect 0x001814e8 sys_id.control_slave
ad_cpu_interconnect 0x00181420 sys_timer_1.s1
ad_cpu_interconnect 0x00181520 sys_timer_2.s1
ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave
ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port
# dma interconnects
ad_dma_interconnect sys_ethernet_dma_tx.mm_read
ad_dma_interconnect sys_ethernet_dma_rx.mm_write
# interrupts
ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq
ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq
ad_cpu_interrupt 2 sys_uart.irq
ad_cpu_interrupt 3 sys_timer_2.irq
ad_cpu_interrupt 4 sys_timer_1.irq
ad_cpu_interrupt 5 sys_gpio_in.irq
ad_cpu_interrupt 6 sys_gpio_bd.irq
ad_cpu_interrupt 7 sys_spi.irq

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projects/common/a5gte/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
ifeq ($(NIOS2_MMU),)
NIOS2_MMU := 1
endif
export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../../scripts/adi_env.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: a5gte.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
a5gte.sof: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> a5gte_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/common/a5gte/system_constr.sdc
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create_clock -period "8.000 ns" -name phy_rx_clk [get_ports {phy_rx_clk}]
derive_pll_clocks
derive_clock_uncertainty

110
projects/common/a5gte/system_project.tcl
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load_package flow
source ../../scripts/adi_env.tcl
project_new a5gte -overwrite
# device settings
set_global_assignment -name FAMILY "Arria V"
set_global_assignment -name DEVICE 5AGTFD7K3F40I3
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc
# fmc fpga interface
set_location_assignment PIN_H18 -to eth_rx_clk
set_location_assignment PIN_J18 -to "eth_rx_clk(n)"
set_location_assignment PIN_J11 -to eth_rx_cntrl
set_location_assignment PIN_K11 -to "eth_rx_cntrl(n)"
set_location_assignment PIN_F12 -to eth_rx_data[0]
set_location_assignment PIN_G12 -to "eth_rx_data[0](n)"
set_location_assignment PIN_H12 -to eth_rx_data[1]
set_location_assignment PIN_J12 -to "eth_rx_data[1](n)"
set_location_assignment PIN_M13 -to eth_rx_data[2]
set_location_assignment PIN_N13 -to "eth_rx_data[2](n)"
set_location_assignment PIN_G13 -to eth_rx_data[3]
set_location_assignment PIN_H13 -to "eth_rx_data[3](n)"
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_clk
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_cntrl
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_data
set_location_assignment PIN_A6 -to eth_tx_clk
set_location_assignment PIN_B6 -to "eth_tx_clk(n)"
set_location_assignment PIN_P12 -to eth_tx_cntrl
set_location_assignment PIN_R12 -to "eth_tx_cntrl(n)"
set_location_assignment PIN_M12 -to eth_tx_data[0]
set_location_assignment PIN_N12 -to "eth_tx_data[0](n)"
set_location_assignment PIN_D12 -to eth_tx_data[1]
set_location_assignment PIN_E12 -to "eth_tx_data[1](n)"
set_location_assignment PIN_P13 -to eth_tx_data[2]
set_location_assignment PIN_R13 -to "eth_tx_data[2](n)"
set_location_assignment PIN_D13 -to eth_tx_data[3]
set_location_assignment PIN_E13 -to "eth_tx_data[3](n)"
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_clk
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_cntrl
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_data
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_tx_clk
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_tx_cntrl
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_tx_data
set_location_assignment PIN_L15 -to eth_mdc
set_location_assignment PIN_M15 -to eth_mdio_i
set_location_assignment PIN_N15 -to eth_mdio_o
set_location_assignment PIN_P15 -to eth_mdio_t
set_location_assignment PIN_A9 -to eth_phy_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_phy_resetn
# phy interface
set_location_assignment PIN_AK17 -to phy_resetn
set_location_assignment PIN_AJ18 -to phy_mdc
set_location_assignment PIN_AL17 -to phy_mdio
set_location_assignment PIN_AK7 -to phy_rx_clk
set_location_assignment PIN_AW17 -to phy_rx_cntrl
set_location_assignment PIN_AU17 -to phy_rx_data[0]
set_location_assignment PIN_AT17 -to phy_rx_data[1]
set_location_assignment PIN_AW16 -to phy_rx_data[2]
set_location_assignment PIN_AH18 -to phy_rx_data[3]
set_location_assignment PIN_AN16 -to phy_tx_clk_out
set_location_assignment PIN_AP19 -to phy_tx_cntrl
set_location_assignment PIN_AT19 -to phy_tx_data[0]
set_location_assignment PIN_AU18 -to phy_tx_data[1]
set_location_assignment PIN_AH19 -to phy_tx_data[2]
set_location_assignment PIN_AG19 -to phy_tx_data[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_resetn
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_mdio
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_cntrl
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_data[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_data[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_data[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_rx_data[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_clk_out
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_cntrl
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_data[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_data[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_data[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to phy_tx_data[3]
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT $ad_hdl_dir/projects/scripts/adi_tquest.tcl
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
execute_flow -compile

351
projects/common/a5gte/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// fpga-fpga interface
output eth_rx_clk,
output eth_rx_cntrl,
output [ 3:0] eth_rx_data,
input eth_tx_clk,
input eth_tx_cntrl,
input [ 3:0] eth_tx_data,
input eth_mdc,
output eth_mdio_i,
input eth_mdio_o,
input eth_mdio_t,
input eth_phy_resetn,
// phy interface
output phy_resetn,
input phy_rx_clk,
input phy_rx_cntrl,
input [ 3:0] phy_rx_data,
output phy_tx_clk_out,
output phy_tx_cntrl,
output [ 3:0] phy_tx_data,
output phy_mdc,
inout phy_mdio);
wire eth_rx_clk_90;
wire eth_tx_clk_90;
wire [ 4:0] eth_tx_data_h;
wire [ 4:0] eth_tx_data_l;
wire [ 4:0] phy_rx_data_h;
wire [ 4:0] phy_rx_data_l;
reg [ 4:0] eth_tx_data_h_d;
reg [ 4:0] phy_rx_data_h_d;
reg [ 4:0] phy_rx_data_h_d1;
reg [ 4:0] phy_rx_data_l_d;
// RX path
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("125.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("125.000000 MHz"),
.phase_shift0("2000 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) eth_rx_pll_i (
.rst (~eth_phy_resetn),
.outclk (eth_rx_clk_90),
.locked (),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (phy_rx_clk)
);
altddio_in #(
.intended_device_family("Arria V"),
.invert_input_clocks("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_in"),
.power_up_high("OFF"),
.width(5)
) eth_rx_path_in (
.datain ({phy_rx_cntrl,phy_rx_data}),
.inclock (phy_rx_clk),
.dataout_h (phy_rx_data_h),
.dataout_l (phy_rx_data_l),
.aclr (~eth_phy_resetn),
.aset (1'b0),
.inclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
always @(posedge phy_rx_clk)
begin
phy_rx_data_h_d <= phy_rx_data_h;
phy_rx_data_h_d1 <= phy_rx_data_h_d;
phy_rx_data_l_d <= phy_rx_data_l;
end
altddio_out #(
.extend_oe_disable("OFF"),
.intended_device_family("Arria V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(5)
) eth_rx_path_out (
.datain_h (phy_rx_data_h_d1),
.datain_l (phy_rx_data_l_d),
.outclock (phy_rx_clk),
.dataout ({eth_rx_cntrl,eth_rx_data}),
.aclr (~eth_phy_resetn),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
altddio_out #(.width(1)) i_eth_rx_clk (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (1'b0),
.outclock (eth_rx_clk_90),
.dataout (eth_rx_clk));
// assign eth_rx_clk = eth_rx_clk_90;
// TX path
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("125.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("125.000000 MHz"),
.phase_shift0("2000 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) eth_tx_pll_i (
.rst (~eth_phy_resetn),
.outclk (eth_tx_clk_90),
.locked (),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (eth_tx_clk)
);
altddio_in #(
.intended_device_family("Arria V"),
.invert_input_clocks("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_in"),
.power_up_high("OFF"),
.width(5))
eth_tx_path_in (
.datain({eth_tx_cntrl,eth_tx_data}),
.inclock(eth_tx_clk_90),
.dataout_h(eth_tx_data_h),
.dataout_l(eth_tx_data_l));
always @(posedge eth_tx_clk_90)
begin
eth_tx_data_h_d <= eth_tx_data_h;
end
altddio_out #(
.extend_oe_disable("OFF"),
.intended_device_family("Arria V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(5)
) eth_tx_path_out (
.datain_h (eth_tx_data_h_d),
.datain_l (eth_tx_data_l),
.outclock (eth_tx_clk_90),
.dataout ({phy_tx_cntrl,phy_tx_data}),
.aclr (~eth_phy_resetn),
.aset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.sclr (1'b0),
.sset (1'b0));
altddio_out #(.width(1)) i_phy_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (1'b0),
.outclock (eth_tx_clk_90),
.dataout (phy_tx_clk_out));
// assign phy_tx_clk_out = eth_tx_clk_90;
// MDIO
assign phy_mdc = eth_mdc;
assign phy_mdio = (eth_mdio_t == 1'b0) ? eth_mdio_o : 1'bz;
assign eth_mdio_i = phy_mdio;
// Reset
assign phy_resetn = eth_phy_resetn ;
endmodule
// ***************************************************************************
// ***************************************************************************

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projects/common/a5soc/a5soc_system_assign.tcl
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# a10soc carrier defaults
# i2c (fmc)
set_location_assignment PIN_F26 -to fmca_scl
set_location_assignment PIN_G26 -to fmca_sda
set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_scl
set_instance_assignment -name IO_STANDARD "2.5 V" -to fmca_sda
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_scl
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to fmca_sda
# led & switches
set_location_assignment PIN_AH24 -to gpio_bd_o[0] ; ## led[0]
set_location_assignment PIN_AU24 -to gpio_bd_o[1] ; ## led[1]
set_location_assignment PIN_AT24 -to gpio_bd_o[2] ; ## led[2]
set_location_assignment PIN_AD24 -to gpio_bd_o[3] ; ## led[3]
set_location_assignment PIN_AT23 -to gpio_bd_i[0] ; ## push_buttons[0]
set_location_assignment PIN_AP24 -to gpio_bd_i[1] ; ## push_buttons[1]
set_location_assignment PIN_AW24 -to gpio_bd_i[2] ; ## push_buttons[2]
set_location_assignment PIN_AW23 -to gpio_bd_i[3] ; ## push_buttons[3]
set_location_assignment PIN_AL24 -to gpio_bd_i[4] ; ## dip_switches[0]
set_location_assignment PIN_AF24 -to gpio_bd_i[5] ; ## dip_switches[1]
set_location_assignment PIN_AE24 -to gpio_bd_i[6] ; ## dip_switches[2]
set_location_assignment PIN_AU23 -to gpio_bd_i[7] ; ## dip_switches[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_o[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[4]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[5]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[6]
set_instance_assignment -name IO_STANDARD "1.5 V" -to gpio_bd_i[7]
# uart
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_rx
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_tx
# usb
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d7
# sdio
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_cmd
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d3
# qspi
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_ss0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io3
# ethernet
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_txd3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rxd3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio
# ddr
set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_p
set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].read_capture_clk_buffer
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[4]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[4]
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n
set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_p
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_n
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39]
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_oct_rzqin
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_p
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[14]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cas_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_p
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cke
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cs_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[5]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[6]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[7]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[8]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[9]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[10]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[11]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[12]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[13]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[14]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[15]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[16]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[17]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[18]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[19]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[20]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[21]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[22]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[23]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[24]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[25]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[26]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[27]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[28]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[29]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[30]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[31]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[32]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[33]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[34]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[35]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[36]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[37]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[38]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[39]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[0]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[1]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[3]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_odt
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ras_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_reset_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n
set_location_assignment PIN_A11 -to ddr3_ck_p
set_location_assignment PIN_B10 -to ddr3_ck_n
set_location_assignment PIN_N9 -to ddr3_a[0]
set_location_assignment PIN_M9 -to ddr3_a[1]
set_location_assignment PIN_N10 -to ddr3_a[2]
set_location_assignment PIN_M10 -to ddr3_a[3]
set_location_assignment PIN_A8 -to ddr3_a[4]
set_location_assignment PIN_B7 -to ddr3_a[5]
set_location_assignment PIN_B9 -to ddr3_a[6]
set_location_assignment PIN_A9 -to ddr3_a[7]
set_location_assignment PIN_D9 -to ddr3_a[8]
set_location_assignment PIN_C10 -to ddr3_a[9]
set_location_assignment PIN_K7 -to ddr3_a[10]
set_location_assignment PIN_J7 -to ddr3_a[11]
set_location_assignment PIN_F9 -to ddr3_a[12]
set_location_assignment PIN_E9 -to ddr3_a[13]
set_location_assignment PIN_D11 -to ddr3_a[14]
set_location_assignment PIN_L7 -to ddr3_ba[0]
set_location_assignment PIN_C9 -to ddr3_ba[1]
set_location_assignment PIN_D8 -to ddr3_ba[2]
set_location_assignment PIN_G9 -to ddr3_cas_n
set_location_assignment PIN_R8 -to ddr3_cke
set_location_assignment PIN_H9 -to ddr3_cs_n
set_location_assignment PIN_H7 -to ddr3_odt
set_location_assignment PIN_G8 -to ddr3_ras_n
set_location_assignment PIN_E3 -to ddr3_reset_n
set_location_assignment PIN_J8 -to ddr3_we_n
set_location_assignment PIN_C6 -to ddr3_dm[0]
set_location_assignment PIN_E4 -to ddr3_dm[1]
set_location_assignment PIN_D3 -to ddr3_dm[2]
set_location_assignment PIN_D1 -to ddr3_dm[3]
set_location_assignment PIN_T7 -to ddr3_dm[4]
set_location_assignment PIN_D7 -to ddr3_dq[0]
set_location_assignment PIN_C7 -to ddr3_dq[1]
set_location_assignment PIN_R10 -to ddr3_dq[2]
set_location_assignment PIN_G7 -to ddr3_dq[3]
set_location_assignment PIN_A6 -to ddr3_dq[4]
set_location_assignment PIN_A7 -to ddr3_dq[5]
set_location_assignment PIN_L6 -to ddr3_dq[6]
set_location_assignment PIN_D6 -to ddr3_dq[7]
set_location_assignment PIN_H6 -to ddr3_dq[8]
set_location_assignment PIN_G6 -to ddr3_dq[9]
set_location_assignment PIN_N8 -to ddr3_dq[10]
set_location_assignment PIN_G5 -to ddr3_dq[11]
set_location_assignment PIN_A4 -to ddr3_dq[12]
set_location_assignment PIN_A5 -to ddr3_dq[13]
set_location_assignment PIN_R9 -to ddr3_dq[14]
set_location_assignment PIN_F4 -to ddr3_dq[15]
set_location_assignment PIN_J5 -to ddr3_dq[16]
set_location_assignment PIN_K5 -to ddr3_dq[17]
set_location_assignment PIN_N7 -to ddr3_dq[18]
set_location_assignment PIN_F3 -to ddr3_dq[19]
set_location_assignment PIN_H3 -to ddr3_dq[20]
set_location_assignment PIN_J4 -to ddr3_dq[21]
set_location_assignment PIN_M5 -to ddr3_dq[22]
set_location_assignment PIN_C3 -to ddr3_dq[23]
set_location_assignment PIN_A2 -to ddr3_dq[24]
set_location_assignment PIN_A3 -to ddr3_dq[25]
set_location_assignment PIN_P7 -to ddr3_dq[26]
set_location_assignment PIN_C1 -to ddr3_dq[27]
set_location_assignment PIN_G2 -to ddr3_dq[28]
set_location_assignment PIN_F2 -to ddr3_dq[29]
set_location_assignment PIN_M3 -to ddr3_dq[30]
set_location_assignment PIN_E1 -to ddr3_dq[31]
set_location_assignment PIN_G1 -to ddr3_dq[32]
set_location_assignment PIN_F1 -to ddr3_dq[33]
set_location_assignment PIN_P6 -to ddr3_dq[34]
set_location_assignment PIN_L1 -to ddr3_dq[35]
set_location_assignment PIN_M2 -to ddr3_dq[36]
set_location_assignment PIN_M1 -to ddr3_dq[37]
set_location_assignment PIN_N1 -to ddr3_dq[38]
set_location_assignment PIN_R6 -to ddr3_dq[39]
set_location_assignment PIN_E7 -to ddr3_dqs_n[0]
set_location_assignment PIN_E6 -to ddr3_dqs_n[1]
set_location_assignment PIN_H4 -to ddr3_dqs_n[2]
set_location_assignment PIN_D2 -to ddr3_dqs_n[3]
set_location_assignment PIN_H1 -to ddr3_dqs_n[4]
set_location_assignment PIN_F7 -to ddr3_dqs_p[0]
set_location_assignment PIN_D5 -to ddr3_dqs_p[1]
set_location_assignment PIN_G4 -to ddr3_dqs_p[2]
set_location_assignment PIN_C2 -to ddr3_dqs_p[3]
set_location_assignment PIN_J1 -to ddr3_dqs_p[4]
set_location_assignment PIN_K9 -to ddr3_oct_rzqin
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout
# globals
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON
set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name ECO_REGENERATE_REPORT ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"

195
projects/common/a5soc/a5soc_system_qsys.tcl
View File

@ -1,195 +0,0 @@
# a5soc carrier qsys
set system_type a5soc
# clock-&-reset
add_instance sys_clk clock_source
add_interface sys_clk clock sink
add_interface sys_rst reset sink
set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
# memory (int)
add_instance sys_int_mem altera_avalon_onchip_memory2
set_instance_parameter_value sys_int_mem {dataWidth} {64}
set_instance_parameter_value sys_int_mem {dualPort} {0}
set_instance_parameter_value sys_int_mem {initMemContent} {0}
set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
add_connection sys_clk.clk sys_int_mem.clk1
add_connection sys_clk.clk_reset sys_int_mem.reset1
# hps
add_instance sys_hps altera_hps
set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
set_instance_parameter_value sys_hps {F2SDRAM_Type} {}
set_instance_parameter_value sys_hps {F2SDRAM_Width} {}
set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {FPGA}
set_instance_parameter_value sys_hps {SPIM0_Mode} {Full}
set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 1}
set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
set_instance_parameter_value sys_hps {use_default_mpu_clk} {0}
set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {50.0}
set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {1}
set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {0}
set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {40}
set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
set_instance_parameter_value sys_hps {TIMING_TIS} {170}
set_instance_parameter_value sys_hps {TIMING_TIH} {120}
set_instance_parameter_value sys_hps {TIMING_TDS} {10}
set_instance_parameter_value sys_hps {TIMING_TDH} {45}
set_instance_parameter_value sys_hps {TIMING_TDQSQ} {100}
set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
set_instance_parameter_value sys_hps {TIMING_TDQSCK} {225}
set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.27}
set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
set_instance_parameter_value sys_hps {TIMING_TDSH} {0.18}
set_instance_parameter_value sys_hps {TIMING_TDSS} {0.18}
set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
set_instance_parameter_value sys_hps {MEM_TWTR} {4}
set_instance_parameter_value sys_hps {MEM_TFAW_NS} {35.0}
set_instance_parameter_value sys_hps {MEM_TRRD_NS} {6.0}
set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
add_interface sys_hps_cpu_clk clock source
set_interface_property sys_hps_cpu_clk EXPORT_OF sys_hps.h2f_user0_clock
add_interface sys_hps_dma_clk clock source
set_interface_property sys_hps_dma_clk EXPORT_OF sys_hps.h2f_user1_clock
add_interface sys_hps_spim0 conduit end
set_interface_property sys_hps_spim0 EXPORT_OF sys_hps.spim0
add_interface sys_hps_spim0_sclk clock source
set_interface_property sys_hps_spim0_sclk EXPORT_OF sys_hps.spim0_sclk_out
add_interface sys_hps_i2c0_scl clock sink
set_interface_property sys_hps_i2c0_scl EXPORT_OF sys_hps.i2c0_scl_in
add_interface sys_hps_i2c0_clk clock source
set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
add_interface sys_hps_i2c0 conduit end
set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
add_interface sys_hps_ddr3 conduit end
set_interface_property sys_hps_ddr3 EXPORT_OF sys_hps.memory
add_interface sys_hps_io conduit end
set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io
add_interface sys_hps_rstn conduit end
set_interface_property sys_hps_rstn EXPORT_OF sys_hps.h2f_reset
add_connection sys_clk.clk sys_hps.h2f_axi_clock
add_connection sys_hps.h2f_axi_master sys_int_mem.s1
set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0}
add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
# cpu/hps handling
proc ad_cpu_interrupt {m_irq m_port} {
add_connection sys_hps.f2h_irq0 ${m_port}
set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
}
proc ad_cpu_interconnect {m_base m_port} {
add_connection sys_hps.h2f_lw_axi_master ${m_port}
set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress $m_base
}
proc ad_dma_interconnect {m_port} {
add_connection ${m_port} sys_hps.f2h_axi_slave
set_connection_parameter_value ${m_port}/sys_hps.f2h_axi_slave baseAddress {0x0}
}
# common dma interfaces
add_instance sys_dma_clk clock_source
add_interface sys_dma_clk clock sink
add_interface sys_dma_rst reset sink
set_interface_property sys_dma_clk EXPORT_OF sys_dma_clk.clk_in
set_interface_property sys_dma_rst EXPORT_OF sys_dma_clk.clk_in_reset
set_instance_parameter_value sys_dma_clk {clockFrequency} {100000000.0}
set_instance_parameter_value sys_dma_clk {clockFrequencyKnown} {1}
set_instance_parameter_value sys_dma_clk {resetSynchronousEdges} {DEASSERT}
add_connection sys_dma_clk.clk sys_hps.f2h_axi_clock
# sys-id
add_instance sys_id altera_avalon_sysid_qsys
set_instance_parameter_value sys_id {id} {182193580}
add_connection sys_clk.clk_reset sys_id.reset
add_connection sys_clk.clk sys_id.clk
# gpio-bd
add_instance sys_gpio_bd altera_avalon_pio
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
set_instance_parameter_value sys_gpio_bd {width} {32}
add_connection sys_clk.clk_reset sys_gpio_bd.reset
add_connection sys_clk.clk sys_gpio_bd.clk
add_interface sys_gpio_bd conduit end
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
# gpio-in
add_instance sys_gpio_in altera_avalon_pio
set_instance_parameter_value sys_gpio_in {direction} {Input}
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
set_instance_parameter_value sys_gpio_in {width} {32}
add_connection sys_clk.clk_reset sys_gpio_in.reset
add_connection sys_clk.clk sys_gpio_in.clk
add_interface sys_gpio_in conduit end
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
# gpio-out
add_instance sys_gpio_out altera_avalon_pio
set_instance_parameter_value sys_gpio_out {direction} {Output}
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
set_instance_parameter_value sys_gpio_out {width} {32}
add_connection sys_clk.clk_reset sys_gpio_out.reset
add_connection sys_clk.clk sys_gpio_out.clk
add_interface sys_gpio_out conduit end
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
# base-addresses
ad_cpu_interconnect 0x001814e8 sys_id.control_slave
ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
# interrupts
ad_cpu_interrupt 0 sys_gpio_in.irq
ad_cpu_interrupt 1 sys_gpio_bd.irq