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adv7511:kc705: Delete deprecated project

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Istvan Csomortani 2018-04-13 12:35:25 +01:00 committed by István Csomortáni
parent c5b1b905e3
commit a277d55c35
5 changed files with 0 additions and 275 deletions
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18
projects/adv7511/kc705/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := adv7511_kc705
M_DEPS += ../../common/kc705/kc705_system_mig.prj
M_DEPS += ../../common/kc705/kc705_system_constr.xdc
M_DEPS += ../../common/kc705/kc705_system_bd.tcl
M_DEPS += ../../adv7511/common/adv7511_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
include ../../scripts/project-xilinx.mk

6
projects/adv7511/kc705/system_bd.tcl
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source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl
ad_ip_parameter axi_hdmi_dma CONFIG.c_m_axi_mm2s_data_width 512
ad_ip_parameter axi_hdmi_dma CONFIG.c_m_axis_mm2s_tdata_width 64

34
projects/adv7511/kc705/system_constr.xdc
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# hdmi
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports hdmi_hsync]
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS25} [get_ports hdmi_vsync]
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports hdmi_data_e]
set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[0]]
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[1]]
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[2]]
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[3]]
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[4]]
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[5]]
set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS25} [get_ports hdmi_data[6]]
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS25} [get_ports hdmi_data[7]]
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[8]]
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[9]]
set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[10]]
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS25} [get_ports hdmi_data[11]]
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports hdmi_data[12]]
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports hdmi_data[13]]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports hdmi_data[14]]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports hdmi_data[15]]
# spdif
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spdif]
# spi -- because the interface is not used, the leaf registers of the output lines
# should be set to IOB FALSE to prevent a CRITICAL WARNING
set_property IOB FALSE [get_cells i_system_wrapper/system_i/axi_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG]
set_property IOB FALSE [get_cells i_system_wrapper/system_i/axi_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG]

14
projects/adv7511/kc705/system_project.tcl
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx adv7511_kc705
adi_project_files adv7511_kc705 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
adi_project_run adv7511_kc705

203
projects/adv7511/kc705/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input sys_rst,
input sys_clk_p,
input sys_clk_n,
input uart_sin,
output uart_sout,
output [ 2:0] ddr3_1_n,
output [ 1:0] ddr3_1_p,
output ddr3_reset_n,
output [13:0] ddr3_addr,
output [ 2:0] ddr3_ba,
output ddr3_cas_n,
output ddr3_ras_n,
output ddr3_we_n,
output ddr3_ck_n,
output ddr3_ck_p,
output ddr3_cke,
output ddr3_cs_n,
output [ 7:0] ddr3_dm,
inout [63:0] ddr3_dq,
inout [ 7:0] ddr3_dqs_n,
inout [ 7:0] ddr3_dqs_p,
output ddr3_odt,
output mdio_mdc,
inout mdio_mdio,
output mii_rst_n,
input mii_col,
input mii_crs,
input mii_rx_clk,
input mii_rx_er,
input mii_rx_dv,
input [ 3:0] mii_rxd,
input mii_tx_clk,
output mii_tx_en,
output [ 3:0] mii_txd,
output [26:1] linear_flash_addr,
output linear_flash_adv_ldn,
output linear_flash_ce_n,
inout [15:0] linear_flash_dq_io,
output linear_flash_oen,
output linear_flash_wen,
output fan_pwm,
inout [ 6:0] gpio_lcd,
inout [16:0] gpio_bd,
output iic_rstn,
inout iic_scl,
inout iic_sda,
output hdmi_out_clk,
output hdmi_hsync,
output hdmi_vsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// default logic
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
// instantiations
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.hdmi_16_data (hdmi_data),
.hdmi_16_data_e (hdmi_data_e),
.hdmi_16_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_16_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.mb_intr_02 (1'b0),
.mb_intr_03 (1'b0),
.mb_intr_06 (1'b0),
.mb_intr_12 (1'b0),
.mb_intr_13 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.hdmi_24_data (),
.hdmi_24_data_e (),
.hdmi_24_hsync (),
.hdmi_24_vsync (),
.hdmi_36_data (),
.hdmi_36_data_e (),
.hdmi_36_hsync (),
.hdmi_36_vsync (),
.spi_clk_i (1'b0),
.spi_clk_o (),
.spi_csn_i (1'b0),
.spi_csn_o (),
.spi_sdi_i (1'b0),
.spi_sdo_i (1'b0),
.spi_sdo_o (),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.spdif (spdif),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************