From a2da96539194a303d2de0fbb8fd998569be904dd Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 20 May 2022 14:40:04 +0100 Subject: [PATCH] ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable --- .../ad9081_fmca_ebz/vck190/system_constr.xdc | 16 ++--- projects/ad9081_fmca_ebz/vck190/system_top.v | 66 +++++++++++++------ 2 files changed, 53 insertions(+), 29 deletions(-) diff --git a/projects/ad9081_fmca_ebz/vck190/system_constr.xdc b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc index c57e84aed..5f48c5855 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_constr.xdc +++ b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc @@ -48,14 +48,14 @@ set_property -quiet -dict {PACKAGE_PIN V6 set_property -quiet -dict {PACKAGE_PIN V7 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P set_property -quiet -dict {PACKAGE_PIN W8 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N set_property -quiet -dict {PACKAGE_PIN W9 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P -set_property -quiet -dict {PACKAGE_PIN AY25 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66 -set_property -quiet -dict {PACKAGE_PIN AW24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[0] ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66 -set_property -quiet -dict {PACKAGE_PIN AW21 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[1] ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 -set_property -quiet -dict {PACKAGE_PIN AV22 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[1] ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 -set_property -quiet -dict {PACKAGE_PIN BD22 IOSTANDARD LVDS15 } [get_ports fpga_syncout_n[0]] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 -set_property -quiet -dict {PACKAGE_PIN BC23 IOSTANDARD LVDS15 } [get_ports fpga_syncout_p[0]] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 -set_property -quiet -dict {PACKAGE_PIN BD20 IOSTANDARD LVDS15 } [get_ports fpga_syncout_n[1]] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 -set_property -quiet -dict {PACKAGE_PIN BC20 IOSTANDARD LVDS15 } [get_ports fpga_syncout_p[1]] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -quiet -dict {PACKAGE_PIN AY25 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_n ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66 +set_property -quiet -dict {PACKAGE_PIN AW24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_0_p ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66 +set_property -quiet -dict {PACKAGE_PIN AW21 IOSTANDARD LVCMOS15 } [get_ports fpga_syncin_1_n ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -quiet -dict {PACKAGE_PIN AV22 IOSTANDARD LVCMOS15 } [get_ports fpga_syncin_1_p ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -quiet -dict {PACKAGE_PIN BD22 IOSTANDARD LVDS15 } [get_ports fpga_syncout_0_n ] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -quiet -dict {PACKAGE_PIN BC23 IOSTANDARD LVDS15 } [get_ports fpga_syncout_0_p ] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -quiet -dict {PACKAGE_PIN BD20 IOSTANDARD LVCMOS15 } [get_ports fpga_syncout_1_n ] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -quiet -dict {PACKAGE_PIN BC20 IOSTANDARD LVCMOS15 } [get_ports fpga_syncout_1_p ] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS15 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS15 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 set_property -dict {PACKAGE_PIN BA17 IOSTANDARD LVCMOS15 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67 diff --git a/projects/ad9081_fmca_ebz/vck190/system_top.v b/projects/ad9081_fmca_ebz/vck190/system_top.v index 71332f966..2fd76355d 100644 --- a/projects/ad9081_fmca_ebz/vck190/system_top.v +++ b/projects/ad9081_fmca_ebz/vck190/system_top.v @@ -39,7 +39,8 @@ module system_top #( parameter TX_JESD_L = 4, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 4, - parameter RX_NUM_LINKS = 1 + parameter RX_NUM_LINKS = 1, + parameter JESD_MODE = "8B10B" ) ( input sys_clk_n, input sys_clk_p, @@ -77,10 +78,14 @@ module system_top #( input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, - input [TX_NUM_LINKS-1:0] fpga_syncin_n, - input [TX_NUM_LINKS-1:0] fpga_syncin_p, - output [RX_NUM_LINKS-1:0] fpga_syncout_n, - output [RX_NUM_LINKS-1:0] fpga_syncout_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, inout [10:0] gpio, inout hmc_gpio1, output hmc_sync, @@ -149,22 +154,15 @@ module system_top #( .IB (clkin10_n), .O (clkin10)); - genvar i; - generate - for(i=0;i 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + /* Board GPIOS. Buttons, LEDs, etc... */ assign gpio_led = gpio_o[3:0]; assign gpio_i[3:0] = gpio_o[3:0]; @@ -222,7 +245,8 @@ module system_top #( assign gpio_i[9: 8] = gpio_pb; // Unused GPIOs - assign gpio_i[94:54] = gpio_o[94:54]; + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[94:64] = gpio_o[94:64]; assign gpio_i[31:10] = gpio_o[31:10]; system_wrapper i_system_wrapper (