axi_rd_wr_combiner: Add rlast to the AXI MM interface

The DMAC is relying on the rlast signal that marks the end of a burst.
main
Laszlo Nagy 2019-02-21 12:03:49 +00:00 committed by Laszlo Nagy
parent c10c4d4f5e
commit a3ce8c5ca6
1 changed files with 3 additions and 0 deletions

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@ -79,6 +79,7 @@ module axi_rd_wr_combiner (
input m_axi_rvalid, input m_axi_rvalid,
input [ 1:0] m_axi_rresp, input [ 1:0] m_axi_rresp,
input [63:0] m_axi_rdata, input [63:0] m_axi_rdata,
input m_axi_rlast,
output m_axi_rready, output m_axi_rready,
// Slave write address // Slave write address
@ -117,6 +118,7 @@ module axi_rd_wr_combiner (
output s_rd_axi_rvalid, output s_rd_axi_rvalid,
output [ 1:0] s_rd_axi_rresp, output [ 1:0] s_rd_axi_rresp,
output [63:0] s_rd_axi_rdata, output [63:0] s_rd_axi_rdata,
output s_rd_axi_rlast,
input s_rd_axi_rready input s_rd_axi_rready
); );
@ -151,6 +153,7 @@ assign s_rd_axi_arready = m_axi_arready;
assign s_rd_axi_rvalid = m_axi_rvalid; assign s_rd_axi_rvalid = m_axi_rvalid;
assign s_rd_axi_rresp = m_axi_rresp; assign s_rd_axi_rresp = m_axi_rresp;
assign s_rd_axi_rdata = m_axi_rdata; assign s_rd_axi_rdata = m_axi_rdata;
assign s_rd_axi_rlast = m_axi_rlast;
assign m_axi_rready = s_rd_axi_rready; assign m_axi_rready = s_rd_axi_rready;
endmodule endmodule