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fmcjesdadc1/a5gt: split xcvr cores

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Rejeesh Kutty 2015-07-15 09:39:17 -04:00
parent 2d8fa2024b
commit a454b73d27
3 changed files with 91 additions and 651 deletions
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730
projects/fmcjesdadc1/a5gt/system_bd.qsys
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File diff suppressed because one or more lines are too long

4
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -8,6 +8,10 @@ source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE ../common/sys_xcvr.v
set_global_assignment -name QSYS_FILE sys_xcvr_rstcntrl_rx_pll.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_core.qsys
set_global_assignment -name QSYS_FILE sys_xcvr_rx_ip.qsys
# reference clock # reference clock

8
projects/fmcjesdadc1/a5gt/system_top.v
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@ -213,11 +213,10 @@ module system_top (
.dataout (eth_tx_clk_out)); .dataout (eth_tx_clk_out));
system_bd i_system_bd ( system_bd i_system_bd (
.rx_data_rx_serial_data (rx_data), .rx_data_rx_d (rx_data),
.rx_ip_sysref_export (rx_sysref),
.rx_ref_clk_clk (ref_clk), .rx_ref_clk_clk (ref_clk),
.rx_sync_rx_sync (rx_sync), .rx_sync_rx_sync (rx_sync),
.rx_sysref_export (rx_sysref), .rx_sysref_rx_ext_sysref_out (rx_sysref),
.sys_125m_clk_clk (sys_125m_clk), .sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk), .sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk), .sys_2m5_clk_clk (sys_2m5_clk),
@ -261,7 +260,8 @@ module system_top (
.sys_spi_MISO (spi_miso), .sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi), .sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk), .sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn)); .sys_spi_SS_n (spi_csn),
.tx_ref_clk_clk (1'd0));
endmodule endmodule