ad6676evb: Updated project to 2015.2.1
- updated to the new jesd framework - added cpack coremain
Adrian Costina
parent
7f9c526683
commit
a49230ec07
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@ -7,34 +7,42 @@ create_bd_port -dir O rx_sysref
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create_bd_port -dir I -from 1 -to 0 rx_data_p
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create_bd_port -dir I -from 1 -to 0 rx_data_n
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_a
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create_bd_port -dir O adc_valid_a
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create_bd_port -dir O -from 31 -to 0 adc_data_a
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create_bd_port -dir O adc_enable_b
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create_bd_port -dir O adc_valid_b
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create_bd_port -dir O -from 31 -to 0 adc_data_b
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 63 -to 0 adc_ddata
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# adc peripherals
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set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
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set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad6676_jesd]
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set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad6676_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
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set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad6676_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_0 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad6676_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_1 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad6676_gt
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set util_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad6676_gt]
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set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad6676_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad6676_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad6676_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad6676_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad6676_gt
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set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma
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@ -49,73 +57,58 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
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set adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 adc_pack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $adc_pack
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# connections (gt)
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ad_connect axi_ad6676_gt/ref_clk_c rx_ref_clk
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ad_connect axi_ad6676_gt/rx_data_p rx_data_p
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ad_connect axi_ad6676_gt/rx_data_n rx_data_n
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ad_connect axi_ad6676_gt/rx_sync rx_sync
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ad_connect axi_ad6676_gt/rx_sysref rx_sysref
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ad_connect util_ad6676_gt/qpll_ref_clk rx_ref_clk
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ad_connect util_ad6676_gt/cpll_ref_clk rx_ref_clk
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ad_connect axi_ad6676_gt/gt_pll_0 util_ad6676_gt/gt_pll_0
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ad_connect axi_ad6676_gt/gt_pll_1 util_ad6676_gt/gt_pll_1
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ad_connect axi_ad6676_gt/gt_rx_0 util_ad6676_gt/gt_rx_0
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ad_connect axi_ad6676_gt/gt_rx_1 util_ad6676_gt/gt_rx_1
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ad_connect axi_ad6676_gt/gt_rx_ip_0 axi_ad6676_jesd/gt0_rx
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ad_connect axi_ad6676_gt/gt_rx_ip_1 axi_ad6676_jesd/gt1_rx
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ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_0 axi_ad6676_jesd/rxencommaalign_out
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ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_1 axi_ad6676_jesd/rxencommaalign_out
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# connections (adc)
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ad_connect ad6676_clk axi_ad6676_gt/rx_clk_g
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ad_connect ad6676_clk adc_clk
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ad_connect ad6676_clk axi_ad6676_gt/rx_clk
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ad_connect ad6676_clk axi_ad6676_core/rx_clk
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ad_connect ad6676_clk axi_ad6676_jesd/rx_core_clk
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ad_connect ad6676_clk axi_ad6676_dma/fifo_wr_clk
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ad_connect axi_ad6676_gt/rx_jesd_rst axi_ad6676_jesd/rx_reset
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ad_connect axi_ad6676_gt/rx_sysref axi_ad6676_jesd/rx_sysref
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ad_connect axi_ad6676_gt/tx_clk_g axi_ad6676_gt/tx_clk
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ad_connect util_ad6676_gt/rx_p rx_data_p
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ad_connect util_ad6676_gt/rx_n rx_data_n
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ad_connect util_ad6676_gt/rx_sync rx_sync
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ad_connect util_ad6676_gt/rx_ip_sysref rx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_ad6676_gt/rx_out_clk util_ad6676_gt/rx_clk
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ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_jesd/rx_core_clk
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ad_connect util_ad6676_gt/rx_ip_rst axi_ad6676_jesd/rx_reset
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ad_connect util_ad6676_gt/rx_ip_rst_done axi_ad6676_jesd/rx_reset_done
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ad_connect util_ad6676_gt/rx_ip_sysref axi_ad6676_jesd/rx_sysref
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ad_connect util_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync
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ad_connect util_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame
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ad_connect util_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata
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ad_connect util_bsplit_rx_gt_charisk/data axi_ad6676_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad6676_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad6676_jesd/gt1_rxcharisk
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ad_connect axi_ad6676_core/adc_clk adc_pack/adc_clk
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ad_connect axi_ad6676_core/adc_rst adc_pack/adc_rst
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ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_core/rx_clk
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ad_connect util_ad6676_gt/rx_data axi_ad6676_core/rx_data
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_disperr]
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ad_connect axi_ad6676_core/adc_enable_a adc_pack/adc_enable_0
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ad_connect axi_ad6676_core/adc_valid_a adc_pack/adc_valid_0
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ad_connect axi_ad6676_core/adc_data_a adc_pack/adc_data_0
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ad_connect axi_ad6676_core/adc_enable_b adc_pack/adc_enable_1
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ad_connect axi_ad6676_core/adc_valid_b adc_pack/adc_valid_1
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ad_connect axi_ad6676_core/adc_data_b adc_pack/adc_data_1
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ad_connect util_bsplit_rx_gt_disperr/data axi_ad6676_gt/rx_gt_disperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad6676_jesd/gt0_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad6676_jesd/gt1_rxdisperr
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_ad6676_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad6676_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad6676_jesd/gt1_rxnotintable
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_ad6676_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad6676_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad6676_jesd/gt1_rxdata
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ad_connect axi_ad6676_gt/rx_rst_done axi_ad6676_jesd/rx_reset_done
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ad_connect axi_ad6676_gt/rx_ip_comma_align axi_ad6676_jesd/rxencommaalign_out
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ad_connect axi_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync
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ad_connect axi_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame
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ad_connect axi_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata
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ad_connect axi_ad6676_gt/rx_data axi_ad6676_core/rx_data
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ad_connect axi_ad6676_core/adc_enable_a adc_enable_a
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ad_connect axi_ad6676_core/adc_valid_a adc_valid_a
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ad_connect axi_ad6676_core/adc_data_a adc_data_a
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ad_connect axi_ad6676_core/adc_enable_b adc_enable_b
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ad_connect axi_ad6676_core/adc_valid_b adc_valid_b
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ad_connect axi_ad6676_core/adc_data_b adc_data_b
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ad_connect axi_ad6676_dma/fifo_wr_en adc_dwr
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ad_connect axi_ad6676_dma/fifo_wr_sync adc_dsync
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ad_connect axi_ad6676_dma/fifo_wr_din adc_ddata
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ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
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ad_connect axi_ad6676_dma/fifo_wr_en adc_pack/adc_valid
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ad_connect axi_ad6676_dma/fifo_wr_sync adc_pack/adc_sync
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ad_connect axi_ad6676_dma/fifo_wr_din adc_pack/adc_data
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ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
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# interconnect (cpu)
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