axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling

We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.

Also set rlast to 1 instead of 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-09 14:58:51 +02:00
parent c7989925c5
commit a4b9b1254a
2 changed files with 22 additions and 10 deletions

View File

@ -239,7 +239,7 @@ module axi_ad9361_alt (
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [ 15:0] s_axi_araddr;
@ -254,7 +254,7 @@ module axi_ad9361_alt (
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [ 31:0] s_axi_rdata;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
@ -264,10 +264,16 @@ module axi_ad9361_alt (
output [ 61:0] dev_l_dbg_data;
// defaults
always @(posedge s_axi_aclk) begin
if (s_axi_awready)
s_axi_bid <= s_axi_awid;
end
always @(posedge s_axi_aclk) begin
if (s_axi_arready)
s_axi_rid <= s_axi_arid;
end
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
assign s_axi_rlast = 1'd1;
// ad9361 lite version

View File

@ -226,7 +226,7 @@ module axi_dmac_alt (
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
input s_axi_bready;
input s_axi_arvalid;
input [13:0] s_axi_araddr;
@ -241,7 +241,7 @@ module axi_dmac_alt (
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
output s_axi_rlast;
input s_axi_rready;
@ -354,9 +354,15 @@ module axi_dmac_alt (
// defaults
assign s_axi_bid = s_axi_awid;
assign s_axi_rid = s_axi_arid;
assign s_axi_rlast = 1'd0;
always @(posedge s_axi_aclk) begin
if (s_axi_awready)
s_axi_bid <= s_axi_awid;
end
always @(posedge s_axi_aclk) begin
if (s_axi_arready)
s_axi_rid <= s_axi_arid;
end
assign s_axi_rlast = 1'b1;
// instantiation