axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
We must make sure that the response ID is the same as the request ID when we accepted the request. Otherwise we might respond with the wrong ID and the system will lockup. Also set rlast to 1 instead of 0. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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c7989925c5
commit
a4b9b1254a
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@ -239,7 +239,7 @@ module axi_ad9361_alt (
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [ 15:0] s_axi_araddr;
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@ -254,7 +254,7 @@ module axi_ad9361_alt (
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [ 31:0] s_axi_rdata;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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@ -264,10 +264,16 @@ module axi_ad9361_alt (
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output [ 61:0] dev_l_dbg_data;
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// defaults
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always @(posedge s_axi_aclk) begin
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if (s_axi_awready)
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s_axi_bid <= s_axi_awid;
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end
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always @(posedge s_axi_aclk) begin
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if (s_axi_arready)
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s_axi_rid <= s_axi_arid;
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end
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assign s_axi_bid = s_axi_awid;
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assign s_axi_rid = s_axi_arid;
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assign s_axi_rlast = 1'd0;
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assign s_axi_rlast = 1'd1;
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// ad9361 lite version
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@ -226,7 +226,7 @@ module axi_dmac_alt (
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [13:0] s_axi_araddr;
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@ -241,7 +241,7 @@ module axi_dmac_alt (
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output reg [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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@ -354,9 +354,15 @@ module axi_dmac_alt (
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// defaults
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assign s_axi_bid = s_axi_awid;
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assign s_axi_rid = s_axi_arid;
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assign s_axi_rlast = 1'd0;
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always @(posedge s_axi_aclk) begin
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if (s_axi_awready)
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s_axi_bid <= s_axi_awid;
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end
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always @(posedge s_axi_aclk) begin
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if (s_axi_arready)
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s_axi_rid <= s_axi_arid;
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end
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assign s_axi_rlast = 1'b1;
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// instantiation
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