axi_spi_engine: Refactoring sdi_fifo read outs
Context switching with a parameter is not a good idea. The simulator may evaluate both branch of the IF statement, even though the inactive branch may not be valid. Use if..generate to make the code more robust for both synthesizers and simulators.main
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@ -154,6 +154,7 @@ module axi_spi_engine #(
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wire sdo_fifo_in_ready;
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wire sdo_fifo_in_valid;
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wire sdi_fifo_out_data_msb_s;
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wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
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wire sdi_fifo_almost_full;
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@ -335,6 +336,15 @@ module axi_spi_engine #(
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end
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end
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generate
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if (NUM_OF_SDI > 1) begin
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// Only the first two SDI data can be recovered through AXI regmap
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
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end else begin
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
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end
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endgenerate
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always @(posedge clk) begin
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case (up_raddr_s)
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8'h00: up_rdata_ff <= PCORE_VERSION;
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@ -350,8 +360,8 @@ module axi_spi_engine #(
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8'h34: up_rdata_ff <= cmd_fifo_room;
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8'h35: up_rdata_ff <= sdo_fifo_room;
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8'h36: up_rdata_ff <= sdi_fifo_level;
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8'h3a: up_rdata_ff <= sdi_fifo_out_data;
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8'h3b: up_rdata_ff <= (NUM_OF_SDI*DATA_WIDTH > 32) ? sdi_fifo_out_data[NUM_OF_SDI*DATA_WIDTH-1:32] : sdi_fifo_out_data; /* store SDI's 32 bits MSB, if exists */
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8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
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8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
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