zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcjesdadc1: Update projects to xcvr framework 

This commit contains modifications for Xilinx only
main
Istvan Csomortani 2016-11-10 10:59:52 +02:00
parent 6073cdded4
commit a54092c9bb
13 changed files with 131 additions and 181 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

203
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
View File

@ -1,63 +1,26 @@
# ad9250
create_bd_port -dir I rx_ref_clk
create_bd_port -dir O rx_sync
create_bd_port -dir O rx_sysref
create_bd_port -dir I -from 3 -to 0 rx_data_p
create_bd_port -dir I -from 3 -to 0 rx_data_n
# adc peripherals
set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
set axi_ad9250_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9250_xcvr]
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_xcvr
set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9250_xcvr
set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9250_xcvr
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9250_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
set axi_ad9250_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9250_gt]
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9250_gt
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9250_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9250_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9250_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9250_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {2}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9250_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {2}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9250_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9250_gt
set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit
set util_fmcjesdadc1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcjesdadc1_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_fmcjesdadc1_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_fmcjesdadc1_gt
set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_fmcjesdadc1_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcjesdadc1_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcjesdadc1_gt
set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
set axi_ad9250_0_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_0_cpack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_0_cpack
set axi_ad9250_1_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9250_1_cpack]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad9250_1_cpack
set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9250_0_dma
@ -85,111 +48,79 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
set data_bsplit [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 data_bsplit]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64} ] $data_bsplit
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_bsplit
# transceiver core
set data_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_0]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_0
set util_fmcjesdadc1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcjesdadc1_xcvr]
set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_fmcjesdadc1_xcvr
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcjesdadc1_xcvr
set data_pack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 data_pack_1]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $data_pack_1
# connections (gt)
ad_connect util_fmcjesdadc1_gt/qpll_ref_clk rx_ref_clk
ad_connect util_fmcjesdadc1_gt/cpll_ref_clk rx_ref_clk
ad_connect axi_ad9250_gt/gt_pll_0 util_fmcjesdadc1_gt/gt_pll_0
ad_connect axi_ad9250_gt/gt_pll_1 util_fmcjesdadc1_gt/gt_pll_1
ad_connect axi_ad9250_gt/gt_pll_2 util_fmcjesdadc1_gt/gt_pll_2
ad_connect axi_ad9250_gt/gt_pll_3 util_fmcjesdadc1_gt/gt_pll_3
ad_connect axi_ad9250_gt/gt_rx_0 util_fmcjesdadc1_gt/gt_rx_0
ad_connect axi_ad9250_gt/gt_rx_1 util_fmcjesdadc1_gt/gt_rx_1
ad_connect axi_ad9250_gt/gt_rx_2 util_fmcjesdadc1_gt/gt_rx_2
ad_connect axi_ad9250_gt/gt_rx_3 util_fmcjesdadc1_gt/gt_rx_3
ad_connect axi_ad9250_gt/gt_rx_ip_0 axi_ad9250_jesd/gt0_rx
ad_connect axi_ad9250_gt/gt_rx_ip_1 axi_ad9250_jesd/gt1_rx
ad_connect axi_ad9250_gt/gt_rx_ip_2 axi_ad9250_jesd/gt2_rx
ad_connect axi_ad9250_gt/gt_rx_ip_3 axi_ad9250_jesd/gt3_rx
ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_0 axi_ad9250_jesd/rxencommaalign_out
ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_1 axi_ad9250_jesd/rxencommaalign_out
ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_2 axi_ad9250_jesd/rxencommaalign_out
ad_connect axi_ad9250_gt/rx_gt_comma_align_enb_3 axi_ad9250_jesd/rxencommaalign_out
ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
ad_connect sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
# connections (adc)
ad_connect util_fmcjesdadc1_gt/rx_ip_sysref rx_sysref
ad_connect util_fmcjesdadc1_gt/rx_p rx_data_p
ad_connect util_fmcjesdadc1_gt/rx_n rx_data_n
ad_connect util_fmcjesdadc1_gt/rx_sync rx_sync
ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof
ad_connect util_fmcjesdadc1_gt/rx_out_clk util_fmcjesdadc1_gt/rx_clk
ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_jesd/rx_core_clk
ad_connect util_fmcjesdadc1_gt/rx_ip_rst axi_ad9250_jesd/rx_reset
ad_connect util_fmcjesdadc1_gt/rx_ip_rst_done axi_ad9250_jesd/rx_reset_done
ad_connect util_fmcjesdadc1_gt/rx_ip_sysref axi_ad9250_jesd/rx_sysref
ad_connect util_fmcjesdadc1_gt/rx_ip_sync axi_ad9250_jesd/rx_sync
ad_connect util_fmcjesdadc1_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame
ad_connect util_fmcjesdadc1_gt/rx_ip_data axi_ad9250_jesd/rx_tdata
ad_connect axi_ad9250_jesd/rx_tdata data_bsplit/data
ad_connect axi_ad9250_0_core/rx_data data_bsplit/split_data_0
ad_connect axi_ad9250_1_core/rx_data data_bsplit/split_data_1
ad_connect data_bsplit/data util_fmcjesdadc1_gt/rx_data
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_cpack/adc_clk
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_cpack/adc_clk
ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_0_cpack/adc_rst
ad_connect axi_ad9250_jesd_rstgen/peripheral_reset axi_ad9250_1_cpack/adc_rst
ad_connect axi_ad9250_0_core/adc_clk data_pack_0/adc_clk
ad_connect axi_ad9250_0_core/adc_rst data_pack_0/adc_rst
ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_0_core/rx_clk
ad_connect data_bsplit/split_data_0 axi_ad9250_0_core/rx_data
ad_connect axi_ad9250_0_core/adc_enable_a data_pack_0/adc_enable_0
ad_connect axi_ad9250_0_core/adc_valid_a data_pack_0/adc_valid_0
ad_connect axi_ad9250_0_core/adc_data_a data_pack_0/adc_data_0
ad_connect axi_ad9250_0_core/adc_enable_b data_pack_0/adc_enable_1
ad_connect axi_ad9250_0_core/adc_valid_b data_pack_0/adc_valid_1
ad_connect axi_ad9250_0_core/adc_data_b data_pack_0/adc_data_1
ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
ad_connect axi_ad9250_0_dma/fifo_wr_en data_pack_0/adc_valid
ad_connect axi_ad9250_0_dma/fifo_wr_sync data_pack_0/adc_sync
ad_connect axi_ad9250_0_dma/fifo_wr_din data_pack_0/adc_data
ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
ad_connect axi_ad9250_0_core/adc_enable_a axi_ad9250_0_cpack/adc_enable_0
ad_connect axi_ad9250_0_core/adc_valid_a axi_ad9250_0_cpack/adc_valid_0
ad_connect axi_ad9250_0_core/adc_data_a axi_ad9250_0_cpack/adc_data_0
ad_connect axi_ad9250_0_core/adc_enable_b axi_ad9250_0_cpack/adc_enable_1
ad_connect axi_ad9250_0_core/adc_valid_b axi_ad9250_0_cpack/adc_valid_1
ad_connect axi_ad9250_0_core/adc_data_b axi_ad9250_0_cpack/adc_data_1
ad_connect axi_ad9250_1_core/adc_enable_a axi_ad9250_1_cpack/adc_enable_0
ad_connect axi_ad9250_1_core/adc_valid_a axi_ad9250_1_cpack/adc_valid_0
ad_connect axi_ad9250_1_core/adc_data_a axi_ad9250_1_cpack/adc_data_0
ad_connect axi_ad9250_1_core/adc_enable_b axi_ad9250_1_cpack/adc_enable_1
ad_connect axi_ad9250_1_core/adc_valid_b axi_ad9250_1_cpack/adc_valid_1
ad_connect axi_ad9250_1_core/adc_data_b axi_ad9250_1_cpack/adc_data_1
ad_connect axi_ad9250_1_core/adc_clk data_pack_1/adc_clk
ad_connect axi_ad9250_1_core/adc_rst data_pack_1/adc_rst
ad_connect util_fmcjesdadc1_gt/rx_out_clk axi_ad9250_1_core/rx_clk
ad_connect data_bsplit/split_data_1 axi_ad9250_1_core/rx_data
ad_connect axi_ad9250_1_core/adc_enable_a data_pack_1/adc_enable_0
ad_connect axi_ad9250_1_core/adc_valid_a data_pack_1/adc_valid_0
ad_connect axi_ad9250_1_core/adc_data_a data_pack_1/adc_data_0
ad_connect axi_ad9250_1_core/adc_enable_b data_pack_1/adc_enable_1
ad_connect axi_ad9250_1_core/adc_valid_b data_pack_1/adc_valid_1
ad_connect axi_ad9250_1_core/adc_data_b data_pack_1/adc_data_1
ad_connect axi_ad9250_0_core/adc_clk axi_ad9250_0_dma/fifo_wr_clk
ad_connect axi_ad9250_0_dma/fifo_wr_en axi_ad9250_0_cpack/adc_valid
ad_connect axi_ad9250_0_dma/fifo_wr_sync axi_ad9250_0_cpack/adc_sync
ad_connect axi_ad9250_0_dma/fifo_wr_din axi_ad9250_0_cpack/adc_data
ad_connect axi_ad9250_0_core/adc_dovf axi_ad9250_0_dma/fifo_wr_overflow
ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
ad_connect axi_ad9250_1_dma/fifo_wr_en axi_ad9250_1_cpack/adc_valid
ad_connect axi_ad9250_1_dma/fifo_wr_sync axi_ad9250_1_cpack/adc_sync
ad_connect axi_ad9250_1_dma/fifo_wr_din axi_ad9250_1_cpack/adc_data
ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
ad_connect axi_ad9250_1_core/adc_clk axi_ad9250_1_dma/fifo_wr_clk
# interconnect (cpu)
ad_connect axi_ad9250_1_dma/fifo_wr_en data_pack_1/adc_valid
ad_connect axi_ad9250_1_dma/fifo_wr_sync data_pack_1/adc_sync
ad_connect axi_ad9250_1_dma/fifo_wr_din data_pack_1/adc_data
ad_connect axi_ad9250_1_core/adc_dovf axi_ad9250_1_dma/fifo_wr_overflow
ad_cpu_interconnect 0x44A60000 axi_ad9250_xcvr
ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
# interconnects
# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
ad_cpu_interconnect 0x44A10000 axi_ad9250_0_core
ad_cpu_interconnect 0x44A20000 axi_ad9250_1_core
ad_cpu_interconnect 0x44A60000 axi_ad9250_gt
ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9250_0_dma
ad_cpu_interconnect 0x7c430000 axi_ad9250_1_dma
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_xcvr/m_axi
# interconnect (adc)
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_0_dma/m_dest_axi
ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_1_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9250_gt/m_axi
#interrupts
ad_cpu_interrupt ps-13 mb-13 axi_ad9250_0_dma/irq

12
projects/fmcjesdadc1/kc705/Makefile
View File

@ -19,11 +19,11 @@ M_DEPS += ../../common/kc705/kc705_system_constr.xdc
M_DEPS += ../../common/kc705/kc705_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -53,11 +53,11 @@ clean:
clean-all:clean
make -C ../../../library/axi_ad9250 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_jesd_gt clean
fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS)
@ -67,11 +67,11 @@ fmcjesdadc1_kc705.sdk/system_top.hdf: $(M_DEPS)
lib:
make -C ../../../library/axi_ad9250
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_dmac
make -C ../../../library/axi_jesd_gt
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_jesd_gt
####################################################################################
####################################################################################

5
projects/fmcjesdadc1/kc705/system_constr.xdc
View File

@ -21,4 +21,7 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

3
projects/fmcjesdadc1/kc705/system_project.tcl
View File

@ -11,6 +11,5 @@ adi_project_files fmcjesdadc1_kc705 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
adi_project_run fmcjesdadc1_kc705

16
projects/fmcjesdadc1/kc705/system_top.v
View File

@ -266,11 +266,17 @@ module system_top (
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),

12
projects/fmcjesdadc1/vc707/Makefile
View File

@ -19,11 +19,11 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -53,11 +53,11 @@ clean:
clean-all:clean
make -C ../../../library/axi_ad9250 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_jesd_gt clean
fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS)
@ -67,11 +67,11 @@ fmcjesdadc1_vc707.sdk/system_top.hdf: $(M_DEPS)
lib:
make -C ../../../library/axi_ad9250
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_dmac
make -C ../../../library/axi_jesd_gt
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_jesd_gt
####################################################################################
####################################################################################

5
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -21,4 +21,7 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

2
projects/fmcjesdadc1/vc707/system_project.tcl
View File

@ -11,6 +11,4 @@ adi_project_files fmcjesdadc1_vc707 [list \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
adi_project_run fmcjesdadc1_vc707

16
projects/fmcjesdadc1/vc707/system_top.v
View File

@ -256,11 +256,17 @@ module system_top (
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (8'hff),

12
projects/fmcjesdadc1/zc706/Makefile
View File

@ -18,14 +18,14 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
M_VIVADO := vivado -mode batch -source
@ -55,14 +55,14 @@ clean:
clean-all:clean
make -C ../../../library/axi_ad9250 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_jesd_gt clean
fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS)
@ -72,14 +72,14 @@ fmcjesdadc1_zc706.sdk/system_top.hdf: $(M_DEPS)
lib:
make -C ../../../library/axi_ad9250
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_jesd_gt
make -C ../../../library/axi_spdif_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_jesd_gt
####################################################################################
####################################################################################

5
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -21,4 +21,7 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

5
projects/fmcjesdadc1/zc706/system_project.tcl
View File

@ -1,6 +1,4 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
@ -13,8 +11,5 @@ adi_project_files fmcjesdadc1_zc706 [list \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
adi_project_run fmcjesdadc1_zc706

16
projects/fmcjesdadc1/zc706/system_top.v
View File

@ -224,11 +224,17 @@ module system_top (
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),