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Add xfest14 PMODs project 

This project has a SPI controller connected to each of the ZED boards PMOD
ports JA, JB, JC, JD pin 1-4. Pin 7-10 are connected to the PS7 general purpose
GPIOs, except for JC where it is connected to the PS7 UART controller.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-08-12 10:11:02 +02:00
parent 96969079ce
commit a54e4edb08
4 changed files with 542 additions and 0 deletions
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127
projects/pmods/xfest14_zed/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
set pmod_ja1 [create_bd_port -dir O pmod_ja1]
set pmod_ja2 [create_bd_port -dir O pmod_ja2]
set pmod_ja3 [create_bd_port -dir I pmod_ja3]
set pmod_ja4 [create_bd_port -dir O pmod_ja4]
set pmod_jb1 [create_bd_port -dir O pmod_jb1]
set pmod_jb2 [create_bd_port -dir O pmod_jb2]
set pmod_jb3 [create_bd_port -dir I pmod_jb3]
set pmod_jb4 [create_bd_port -dir O pmod_jb4]
set pmod_jc1 [create_bd_port -dir O pmod_jc1]
set pmod_jc2 [create_bd_port -dir O pmod_jc2]
set pmod_jc3 [create_bd_port -dir I pmod_jc3]
set pmod_jc4 [create_bd_port -dir O pmod_jc4]
set pmod_jc7 [create_bd_port -dir I pmod_jc7]
set pmod_jc8 [create_bd_port -dir O pmod_jc8]
set pmod_jc9 [create_bd_port -dir I pmod_jc9]
set pmod_jc10 [create_bd_port -dir O pmod_jc10]
set pmod_jd1 [create_bd_port -dir O pmod_jd1]
set pmod_jd2 [create_bd_port -dir O pmod_jd2]
set pmod_jd3 [create_bd_port -dir I pmod_jd3]
set pmod_jd4 [create_bd_port -dir O pmod_jd4]
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {49}] $sys_ps7
set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UART0_GRP_FULL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_UART0_UART0_IO {EMIO}] $sys_ps7
set_property LEFT 48 [get_bd_ports GPIO_I]
set_property LEFT 48 [get_bd_ports GPIO_O]
set_property LEFT 48 [get_bd_ports GPIO_T]
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc
set sys_const_gnd [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_gnd]
set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {0}] $sys_const_gnd
connect_bd_net -net net_vcc [get_bd_pins sys_const_vcc/const]
connect_bd_net -net net_gnd [get_bd_pins sys_const_gnd/const]
set axi_spi_pmod_jc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_spi_pmod_jc]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi_pmod_jc
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_spi_pmod_jc
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_spi_pmod_jc
set_property -dict [list CONFIG.Multiples16 {4}] $axi_spi_pmod_jc
set axi_spi_pmod_jd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_spi_pmod_jd]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi_pmod_jd
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_spi_pmod_jd
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_spi_pmod_jd
set_property -dict [list CONFIG.Multiples16 {4}] $axi_spi_pmod_jd
connect_bd_net -net pmod_ja1 [get_bd_ports pmod_ja1] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net pmod_ja2 [get_bd_ports pmod_ja2] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net pmod_ja3 [get_bd_ports pmod_ja3] [get_bd_pins sys_ps7/SPI0_MISO_I]
connect_bd_net -net pmod_ja4 [get_bd_ports pmod_ja4] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net pmod_jb1 [get_bd_ports pmod_jb1] [get_bd_pins sys_ps7/SPI1_SS_O]
connect_bd_net -net pmod_jb2 [get_bd_ports pmod_jb2] [get_bd_pins sys_ps7/SPI1_MOSI_O]
connect_bd_net -net pmod_jb3 [get_bd_ports pmod_jb3] [get_bd_pins sys_ps7/SPI1_MISO_I]
connect_bd_net -net pmod_jb4 [get_bd_ports pmod_jb4] [get_bd_pins sys_ps7/SPI1_SCLK_O]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI1_MOSI_I]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI1_SCLK_I]
connect_bd_net -net net_vcc [get_bd_pins sys_ps7/SPI1_SS_I]
connect_bd_net -net pmod_jc1 [get_bd_ports pmod_jc1] [get_bd_pins axi_spi_pmod_jc/ss_o]
connect_bd_net -net pmod_jc2 [get_bd_ports pmod_jc2] [get_bd_pins axi_spi_pmod_jc/io0_o]
connect_bd_net -net pmod_jc3 [get_bd_ports pmod_jc3] [get_bd_pins axi_spi_pmod_jc/io1_i]
connect_bd_net -net pmoc_jc4 [get_bd_ports pmod_jc4] [get_bd_pins axi_spi_pmod_jc/sck_o]
connect_bd_net -net pmod_jc7 [get_bd_ports pmod_jc7] [get_bd_pins sys_ps7/UART0_DCDN]
connect_bd_net -net pmod_jc8 [get_bd_ports pmod_jc8] [get_bd_pins sys_ps7/UART0_TX]
connect_bd_net -net pmod_jc9 [get_bd_ports pmod_jc9] [get_bd_pins sys_ps7/UART0_RX]
connect_bd_net -net pmoc_jc10 [get_bd_ports pmod_jc10] [get_bd_pins sys_ps7/UART0_RTSN]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jc/ss_i]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jc/sck_i]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jc/io0_i]
connect_bd_net -net net_gnd [get_bd_pins sys_ps7/UART0_CTSN]
connect_bd_net -net net_gnd [get_bd_pins sys_ps7/UART0_DSRN]
connect_bd_net -net net_gnd [get_bd_pins sys_ps7/UART0_RIN]
connect_bd_net -net pmod_jd1 [get_bd_ports pmod_jd1] [get_bd_pins axi_spi_pmod_jd/ss_o]
connect_bd_net -net pmod_jd2 [get_bd_ports pmod_jd2] [get_bd_pins axi_spi_pmod_jd/io0_o]
connect_bd_net -net pmod_jd3 [get_bd_ports pmod_jd3] [get_bd_pins axi_spi_pmod_jd/io1_i]
connect_bd_net -net pmoc_jd4 [get_bd_ports pmod_jd4] [get_bd_pins axi_spi_pmod_jd/sck_o]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jd/ss_i]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jd/sck_i]
connect_bd_net -net net_vcc [get_bd_pins axi_spi_pmod_jd/io0_i]
connect_bd_net -net axi_spi_pmod_jc_irq [get_bd_pins axi_spi_pmod_jc/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_spi_pmod_jd_irq [get_bd_pins axi_spi_pmod_jd/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spi_pmod_jc/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spi_pmod_jd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spi_pmod_jc/ext_spi_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spi_pmod_jd/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spi_pmod_jc/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spi_pmod_jd/s_axi_aresetn]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_spi_pmod_jc/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_spi_pmod_jd/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spi_pmod_jc/axi_lite/Reg] SEG_data_spi_pmod_jc
create_bd_addr_seg -range 0x00010000 -offset 0x44A80000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spi_pmod_jd/axi_lite/Reg] SEG_data_spi_pmod_jd

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# PMOD JA
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports pmod_ja1];
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports pmod_ja2];
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pmod_ja3];
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports pmod_ja4];
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports pmod_ja7];
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports pmod_ja8];
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports pmod_ja9];
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports pmod_ja10];
# PMOD JB
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS33} [get_ports pmod_jb1];
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports pmod_jb2];
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pmod_jb3];
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports pmod_jb4];
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33 PULLDOWN true} [get_ports pmod_jb7];
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33 PULLDOWN true} [get_ports pmod_jb8];
set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33 PULLDOWN true} [get_ports pmod_jb9];
set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33 PULLDOWN true} [get_ports pmod_jb10];
# PMOD JC
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports pmod_jc1];
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports pmod_jc2];
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pmod_jc3];
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports pmod_jc4];
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports pmod_jc7];
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports pmod_jc8];
set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports pmod_jc9];
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports pmod_jc10];
# PMOD JD
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports pmod_jd1];
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports pmod_jd2];
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pmod_jd3];
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports pmod_jd4];
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33 PULLDOWN true} [get_ports pmod_jd7];
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports pmod_jd8];
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports pmod_jd9];
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports pmod_jd10];

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projects/pmods/xfest14_zed/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
set project_name pmods_xfest14_zed
adi_project_create $project_name
adi_project_files $project_name [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
adi_project_run $project_name

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projects/pmods/xfest14_zed/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
pmod_ja1,
pmod_ja2,
pmod_ja3,
pmod_ja4,
pmod_ja7,
pmod_ja8,
pmod_ja9,
pmod_ja10,
pmod_jb1,
pmod_jb2,
pmod_jb3,
pmod_jb4,
pmod_jb7,
pmod_jb8,
pmod_jb9,
pmod_jb10,
pmod_jc1,
pmod_jc2,
pmod_jc3,
pmod_jc4,
pmod_jc7,
pmod_jc8,
pmod_jc9,
pmod_jc10,
pmod_jd1,
pmod_jd2,
pmod_jd3,
pmod_jd4,
pmod_jd7,
pmod_jd8,
pmod_jd9,
pmod_jd10,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
output pmod_ja1;
output pmod_ja2;
input pmod_ja3;
output pmod_ja4;
inout pmod_ja7;
inout pmod_ja8;
inout pmod_ja9;
inout pmod_ja10;
output pmod_jb1;
output pmod_jb2;
input pmod_jb3;
output pmod_jb4;
inout pmod_jb7;
inout pmod_jb8;
inout pmod_jb9;
inout pmod_jb10;
output pmod_jc1;
output pmod_jc2;
input pmod_jc3;
output pmod_jc4;
input pmod_jc7;
output pmod_jc8;
input pmod_jc9;
output pmod_jc10;
output pmod_jd1;
output pmod_jd2;
input pmod_jd3;
output pmod_jd4;
inout pmod_jd7;
inout pmod_jd8;
inout pmod_jd9;
inout pmod_jd10;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [48:0] gpio_i;
wire [48:0] gpio_o;
wire [48:0] gpio_t;
wire ref_clk;
wire oddr_ref_clk;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
genvar n;
generate
for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
// For debugging the ADIS16k CS BUSY conflict
// OBUF i_pmod_jb7 (.I(pmod_ja1 == 1'b0 && gpio_i[34] == 1'b0), .O(pmod_jb7));
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0]));
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1]));
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
IOBUF i_pmod_ja7 (.IO(pmod_ja7), .I(gpio_o[32]), .O(gpio_i[32]), .T(gpio_t[32]));
IOBUF i_pmod_ja8 (.IO(pmod_ja8), .I(gpio_o[33]), .O(gpio_i[33]), .T(gpio_t[33]));
IOBUF i_pmod_ja9 (.IO(pmod_ja9), .I(gpio_o[34]), .O(gpio_i[34]), .T(gpio_t[34]));
IOBUF i_pmod_ja10 (.IO(pmod_ja10), .I(gpio_o[35]), .O(gpio_i[35]), .T(gpio_t[35]));
IOBUF i_pmod_jb7 (.IO(pmod_jb7), .I(gpio_o[36]), .O(gpio_i[36]), .T(gpio_t[36]));
IOBUF i_pmod_jb8 (.IO(pmod_jb8), .I(gpio_o[37]), .O(gpio_i[37]), .T(gpio_t[37]));
IOBUF i_pmod_jb9 (.IO(pmod_jb9), .I(gpio_o[38]), .O(gpio_i[38]), .T(gpio_t[38]));
IOBUF i_pmod_jb10 (.IO(pmod_jb10), .I(gpio_o[39]), .O(gpio_i[39]), .T(gpio_t[39]));
/*
IOBUF i_pmod_jc7 (.IO(pmod_jc7), .I(gpio_o[40]), .O(gpio_i[40]), .T(gpio_t[40]));
IOBUF i_pmod_jc8 (.IO(pmod_jc8), .I(gpio_o[41]), .O(gpio_i[41]), .T(gpio_t[41]));
IOBUF i_pmod_jc9 (.IO(pmod_jc9), .I(gpio_o[42]), .O(gpio_i[42]), .T(gpio_t[42]));
IOBUF i_pmod_jc10 (.IO(pmod_jc10), .I(gpio_o[43]), .O(gpio_i[43]), .T(gpio_t[43]));
*/
IOBUF i_pmod_jd7 (.IO(pmod_jd7), .I(gpio_o[44]), .O(gpio_i[44]), .T(gpio_t[44]));
IOBUF i_pmod_jd8 (.IO(pmod_jd8), .I(gpio_o[45]), .O(gpio_i[45]), .T(gpio_t[45]));
IOBUF i_pmod_jd9 (.IO(pmod_jd9), .I(gpio_o[46]), .O(gpio_i[46]), .T(gpio_t[46]));
IOBUF i_pmod_jd10 (.IO(pmod_jd10), .I(gpio_o[47]), .O(gpio_i[47]), .T(gpio_t[47]));
// On the AD7173 MISO also acts as a interrupt signal, so we need to route it
// to both the GPIO and SPI controller
assign gpio_i[48] = pmod_jc3;
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.pmod_ja1 (pmod_ja1),
.pmod_ja2 (pmod_ja2),
.pmod_ja3 (pmod_ja3),
.pmod_ja4 (pmod_ja4),
.pmod_jb1 (pmod_jb1),
.pmod_jb2 (pmod_jb2),
.pmod_jb3 (pmod_jb3),
.pmod_jb4 (pmod_jb4),
.pmod_jc1 (pmod_jc1),
.pmod_jc2 (pmod_jc2),
.pmod_jc3 (pmod_jc3),
.pmod_jc4 (pmod_jc4),
.pmod_jc7 (pmod_jc7),
.pmod_jc8 (pmod_jc8),
.pmod_jc9 (pmod_jc9),
.pmod_jc10 (pmod_jc10),
.pmod_jd1 (pmod_jd1),
.pmod_jd2 (pmod_jd2),
.pmod_jd3 (pmod_jd3),
.pmod_jd4 (pmod_jd4),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************