From a558d4000d0cded355e2d770ba7954650777618f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 8 Dec 2014 11:27:47 +0200 Subject: [PATCH] motcon1_fmc: Added XADC to the project, the external muxing is controlled by generic GPIO, not XADC GPIO --- .../motcon1_fmc/common/motcon1_fmc_bd.tcl | 39 +++++++++---------- projects/motcon1_fmc/zed/system_constr.xdc | 10 +++++ projects/motcon1_fmc/zed/system_top.v | 36 ++++++++--------- 3 files changed, 46 insertions(+), 39 deletions(-) diff --git a/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl b/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl index e3003e052..47fc44ffe 100644 --- a/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl +++ b/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl @@ -50,11 +50,9 @@ # xadc interface - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn - - #set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ] + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn # additions to default configuration @@ -149,14 +147,14 @@ # xadc -# set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ] -# set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1 -# set_property -dict [list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0}] $xadc_wiz_1 + set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ] + set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1 # additional interconnect @@ -321,13 +319,12 @@ # xadc -# connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source -# connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source + connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn] -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0] -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8] -# connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out] + connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn] + connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0] + connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8] # interconnect (cpu) @@ -335,7 +332,7 @@ connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi] -# connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite] connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi] @@ -441,7 +438,7 @@ create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 -# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motcon1_fmc/zed/system_constr.xdc b/projects/motcon1_fmc/zed/system_constr.xdc index 131902b29..351a1b623 100644 --- a/projects/motcon1_fmc/zed/system_constr.xdc +++ b/projects/motcon1_fmc/zed/system_constr.xdc @@ -73,6 +73,16 @@ set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_d_o] set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o] set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o] +set_property PACKAGE_PIN E16 [get_ports vauxn0] +set_property IOSTANDARD LVCMOS25 [get_ports vauxn0] +set_property PACKAGE_PIN D17 [get_ports vauxn8] +set_property IOSTANDARD LVCMOS25 [get_ports vauxn8] +set_property PACKAGE_PIN F16 [get_ports vauxp0] +set_property IOSTANDARD LVCMOS25 [get_ports vauxp0] +set_property PACKAGE_PIN D16 [get_ports vauxp8] +set_property IOSTANDARD LVCMOS25 [get_ports vauxp8] +set_property IOSTANDARD LVCMOS25 [get_ports vn_in] +set_property IOSTANDARD LVCMOS25 [get_ports vp_in] #set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}] #set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}] diff --git a/projects/motcon1_fmc/zed/system_top.v b/projects/motcon1_fmc/zed/system_top.v index 5d38ff5ae..3b3a6a7a7 100644 --- a/projects/motcon1_fmc/zed/system_top.v +++ b/projects/motcon1_fmc/zed/system_top.v @@ -97,12 +97,12 @@ module system_top ( pwm_ch_o, pwm_cl_o, - //vauxn0, - //vauxn8, - //vauxp0, - //vauxp8, - //vn_in, - //vp_in, + vauxn0, + vauxn8, + vauxp0, + vauxp8, + vn_in, + vp_in, //muxaddr_out, i2s_mclk, @@ -176,12 +176,12 @@ module system_top ( output pwm_ch_o; output pwm_cl_o; - //input vauxn0; - //input vauxn8; - //input vauxp0; - //input vauxp8; - //input vn_in; - //input vp_in; + input vauxn0; + input vauxn8; + input vauxp0; + input vauxp8; + input vn_in; + input vp_in; //output [3:0] muxaddr_out; output spdif; @@ -293,12 +293,12 @@ module system_top ( .pwm_bl_o(pwm_bl_o), .pwm_ch_o(pwm_ch_o), .pwm_cl_o(pwm_cl_o), - //.Vaux0_v_n(vauxn0), - //.Vaux0_v_p(vauxp0), - //.vauxn8(vauxn8), - //.vauxp8(vauxp8), - //.Vp_Vn_v_n(vn_in), - //.Vp_Vn_v_p(vp_in), + .Vaux0_v_n(vauxn0), + .Vaux0_v_p(vauxp0), + .Vaux8_v_n(vauxn8), + .Vaux8_v_p(vauxp8), + .Vp_Vn_v_n(vn_in), + .Vp_Vn_v_p(vp_in), //.muxaddr_out(muxaddr_out), .i2s_bclk (i2s_bclk), .i2s_lrclk (i2s_lrclk),