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adrv9009_zu11eg_som: Change design partitioning 

Create a structure similar with ADRV936x projects
main
Adrian Costina 2019-11-12 15:37:55 +00:00
parent 39d19ef401
commit a589a2c7eb
12 changed files with 182 additions and 188 deletions
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147
projects/adrv9009_zu11eg_som/system_bd.tcl
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@ -1,147 +0,0 @@
# create board design
# default ports
create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o
create_bd_port -dir O -from 94 -to 0 gpio_t
# instance: sys_ps8
ad_ip_instance zynq_ultra_ps_e sys_ps8
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 200
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 12.288
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO}
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15}
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 16 .. 17}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__IO {GT Lane0}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4}
ad_ip_parameter sys_ps8 CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.SUBPRESET1 {DDR4_MICRON_MT40A256M16GE_083E}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BG_ADDR_COUNT {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__PARITY_ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__ECC {Enabled}
set_property -dict [list CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} ] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 32 .. 33}] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {DPLL} CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {DPLL}] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {APLL}] [get_bd_cells sys_ps8]
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1}
ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps8/pl_clk0
ad_connect sys_200m_clk sys_ps8/pl_clk1
ad_connect i2s_m_clk sys_ps8/pl_clk2
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
# gpio
ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
ad_connect gpio_t sys_ps8/emio_gpio_t
# add 1 bit GND signal
ad_ip_instance xlconstant GND_1_bit
ad_ip_parameter GND_1_bit CONFIG.CONST_VAL {0}
# spi
ad_ip_instance xlconcat spi0_csn_concat
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
ad_connect spi0_csn_concat/dout spi0_csn
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
ad_connect sys_ps8/emio_spi0_sclk_i GND_1_bit/dout
ad_connect sys_ps8/emio_spi0_s_i GND_1_bit/dout
# interrupts
ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
ad_connect sys_concat_intc_1/In7 GND
ad_connect sys_concat_intc_1/In6 GND
ad_connect sys_concat_intc_1/In5 GND
ad_connect sys_concat_intc_1/In4 GND
ad_connect sys_concat_intc_1/In3 GND
ad_connect sys_concat_intc_1/In2 GND
ad_connect sys_concat_intc_1/In1 GND
ad_connect sys_concat_intc_1/In0 GND
ad_connect sys_concat_intc_0/In7 GND
ad_connect sys_concat_intc_0/In6 GND
ad_connect sys_concat_intc_0/In5 GND
ad_connect sys_concat_intc_0/In4 GND
ad_connect sys_concat_intc_0/In3 GND
ad_connect sys_concat_intc_0/In2 GND
ad_connect sys_concat_intc_0/In1 GND
ad_connect sys_concat_intc_0/In0 GND
connect_bd_net [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/pl_clk0]
source adrv9009_zu11eg_som_bd.tcl
source carrier_bd.tcl

6
projects/adrv9009_zu11eg_som/system_constr.xdc
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@ -1,6 +0,0 @@
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18} [get_ports spi_clk]
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18} [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN AR9 IOSTANDARD LVCMOS18} [get_ports spi_miso]
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]

16
projects/adrv9009_zu11eg_som/system_project.tcl
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@ -1,16 +0,0 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set p_device "xczu11eg-ffvf1517-1-e"
set sys_zynq 2
adi_project adrv9009_zu11eg_som
adi_project_files adrv9009_zu11eg_som [list \
"system_top.v" \
"adrv9009_zu11eg_som_spi.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
adi_project_run adrv9009_zu11eg_som

18
projects/adrv9009_zu11eg_som/Makefile → projects/adrv9009zu11eg/adrv2crr_fmc/Makefile
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@ -3,15 +3,15 @@
## Auto-generated, do not modify! ## Auto-generated, do not modify!
#################################################################################### ####################################################################################
PROJECT_NAME := adrv9009_zu11eg_som PROJECT_NAME := adrv9009zu11eg
M_DEPS += carrier_bd.tcl M_DEPS += ../common/adrv2crr_fmc_bd.tcl
M_DEPS += adrv9009_zu11eg_som_spi.v M_DEPS += ../common/adrv9009zu11eg_spi.v
M_DEPS += adrv9009_zu11eg_som_bd.tcl M_DEPS += ../common/adrv9009zu11eg_bd.tcl
M_DEPS += carrier_constr.xdc M_DEPS += ../common/adrv2crr_fmc_constr.xdc
M_DEPS += adrv9009_zu11eg_som_constr.xdc M_DEPS += ../common/adrv9009zu11eg_constr.xdc
M_DEPS += ../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../library/jesd204/scripts/jesd204.tcl M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_clkgen LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
@ -29,4 +29,4 @@ LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/axi_dacfifo LIB_DEPS += xilinx/axi_dacfifo
LIB_DEPS += xilinx/util_adxcvr LIB_DEPS += xilinx/util_adxcvr
include ../scripts/project-xilinx.mk include ../../scripts/project-xilinx.mk

3
projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl Normal file
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@ -0,0 +1,3 @@
source ../common/adrv9009zu11eg_bd.tcl
source ../common/adrv2crr_fmc_bd.tcl

17
projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl Normal file
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@ -0,0 +1,17 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set p_device "xczu11eg-ffvf1517-1-e"
set sys_zynq 2
adi_project adrv9009zu11eg
adi_project_files adrv9009zu11eg [list \
"system_top.v" \
"../common/adrv9009zu11eg_spi.v" \
"../common/adrv9009zu11eg_constr.xdc" \
"../common/adrv2crr_fmc_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
adi_project_run adrv9009zu11eg

2
projects/adrv9009_zu11eg_som/system_top.v → projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v
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@ -252,7 +252,7 @@ module system_top (
assign spi_csn_hmc7044 = spi_3_to_8_csn[2]; assign spi_csn_hmc7044 = spi_3_to_8_csn[2];
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
adrv9009_zu11eg_som_spi i_spi ( adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn), .spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk), .spi_clk(spi_clk),
.spi_mosi(spi_mosi), .spi_mosi(spi_mosi),

6
projects/adrv9009_zu11eg_som/carrier_bd.tcl → projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl
View File

@ -1,6 +1,4 @@
add_files -fileset constrs_1 -norecurse ./carrier_constr.xdc
create_bd_port -dir O -type clk i2s_mclk create_bd_port -dir O -type clk i2s_mclk
create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
@ -8,11 +6,13 @@ create_bd_port -dir I axi_fan_tacho_i
create_bd_port -dir O axi_fan_pwm_o create_bd_port -dir O axi_fan_pwm_o
# i2s ip # i2s ip
ad_ip_instance axi_i2s_adi axi_i2s_adi ad_ip_instance axi_i2s_adi axi_i2s_adi
ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 0 ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 0
ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 32 ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 32
# dma # dma
ad_ip_instance axi_dmac i2s_tx_dma ad_ip_instance axi_dmac i2s_tx_dma
ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_SRC 0 ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_DEST 1 ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_DEST 1
@ -40,6 +40,7 @@ ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 32
# i2s connections # i2s connections
ad_connect sys_cpu_clk axi_i2s_adi/s_axi_aclk ad_connect sys_cpu_clk axi_i2s_adi/s_axi_aclk
ad_connect sys_cpu_clk axi_i2s_adi/s_axis_aclk ad_connect sys_cpu_clk axi_i2s_adi/s_axis_aclk
ad_connect sys_cpu_clk axi_i2s_adi/m_axis_aclk ad_connect sys_cpu_clk axi_i2s_adi/m_axis_aclk
@ -48,6 +49,7 @@ ad_connect sys_cpu_resetn axi_i2s_adi/s_axis_aresetn
ad_connect i2s_tx_dma/m_axis axi_i2s_adi/s_axis ad_connect i2s_tx_dma/m_axis axi_i2s_adi/s_axis
# not connecting tlast # not connecting tlast
ad_connect i2s_rx_dma/s_axis_data axi_i2s_adi/m_axis_tdata ad_connect i2s_rx_dma/s_axis_data axi_i2s_adi/m_axis_tdata
ad_connect i2s_rx_dma/s_axis_valid axi_i2s_adi/m_axis_tvalid ad_connect i2s_rx_dma/s_axis_valid axi_i2s_adi/m_axis_tvalid
ad_connect i2s_rx_dma/s_axis_ready axi_i2s_adi/m_axis_tready ad_connect i2s_rx_dma/s_axis_ready axi_i2s_adi/m_axis_tready

0
projects/adrv9009_zu11eg_som/carrier_constr.xdc → projects/adrv9009zu11eg/common/adrv2crr_fmc_constr.xdc
View File

147
projects/adrv9009_zu11eg_som/adrv9009_zu11eg_som_bd.tcl → projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl
View File

@ -1,7 +1,13 @@
# default ports
disconnect_bd_net /sys_cpu_clk [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] create_bd_port -dir O -from 2 -to 0 spi0_csn
create_bd_port -dir O spi0_sclk
create_bd_port -dir O spi0_mosi
create_bd_port -dir I spi0_miso
add_files -fileset constrs_1 -norecurse ./adrv9009_zu11eg_som_constr.xdc create_bd_port -dir I -from 94 -to 0 gpio_i
create_bd_port -dir O -from 94 -to 0 gpio_o
create_bd_port -dir O -from 94 -to 0 gpio_t
create_bd_port -dir I sys_reset create_bd_port -dir I sys_reset
@ -11,7 +17,138 @@ create_bd_port -dir I ref_clk_b
create_bd_port -dir I core_clk_a create_bd_port -dir I core_clk_a
create_bd_port -dir I core_clk_b create_bd_port -dir I core_clk_b
create_bd_port -dir I dac_fifo_bypass
# instance: sys_ps8
ad_ip_instance zynq_ultra_ps_e sys_ps8
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 200
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 12.288
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO}
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15}
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 16 .. 17}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__IO {GT Lane0}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel}
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4}
ad_ip_parameter sys_ps8 CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30}
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.SUBPRESET1 {DDR4_MICRON_MT40A256M16GE_083E}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BG_ADDR_COUNT {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__PARITY_ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__ECC {Enabled}
set_property -dict [list CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} ] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 32 .. 33}] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {DPLL} CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {DPLL}] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {APLL}] [get_bd_cells sys_ps8]
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1}
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1}
ad_ip_instance proc_sys_reset sys_rstgen
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
# system reset/clock definitions
ad_connect sys_cpu_clk sys_ps8/pl_clk0
ad_connect sys_200m_clk sys_ps8/pl_clk1
ad_connect i2s_m_clk sys_ps8/pl_clk2
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
# gpio
ad_connect gpio_i sys_ps8/emio_gpio_i
ad_connect gpio_o sys_ps8/emio_gpio_o
ad_connect gpio_t sys_ps8/emio_gpio_t
# spi
ad_ip_instance xlconcat spi0_csn_concat
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
ad_connect spi0_csn_concat/dout spi0_csn
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
ad_connect sys_ps8/emio_spi0_sclk_i GND
ad_connect sys_ps8/emio_spi0_s_i GND
# interrupts
ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
ad_connect sys_concat_intc_1/In7 GND
ad_connect sys_concat_intc_1/In6 GND
ad_connect sys_concat_intc_1/In5 GND
ad_connect sys_concat_intc_1/In4 GND
ad_connect sys_concat_intc_1/In3 GND
ad_connect sys_concat_intc_1/In2 GND
ad_connect sys_concat_intc_1/In1 GND
ad_connect sys_concat_intc_1/In0 GND
ad_connect sys_concat_intc_0/In7 GND
ad_connect sys_concat_intc_0/In6 GND
ad_connect sys_concat_intc_0/In5 GND
ad_connect sys_concat_intc_0/In4 GND
ad_connect sys_concat_intc_0/In3 GND
ad_connect sys_concat_intc_0/In2 GND
ad_connect sys_concat_intc_0/In1 GND
ad_connect sys_concat_intc_0/In0 GND
# ADRV9009 Specific Connections
# TX parameters # TX parameters
set TX_NUM_OF_LANES 8 ; # L set TX_NUM_OF_LANES 8 ; # L
set TX_NUM_OF_CONVERTERS 8 ; # M set TX_NUM_OF_CONVERTERS 8 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S set TX_SAMPLES_PER_FRAME 1 ; # S
@ -20,6 +157,7 @@ set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N) set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
# RX parameters # RX parameters
set RX_NUM_OF_LANES 4 ; # L set RX_NUM_OF_LANES 4 ; # L
set RX_NUM_OF_CONVERTERS 8 ; # M set RX_NUM_OF_CONVERTERS 8 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S set RX_SAMPLES_PER_FRAME 1 ; # S
@ -74,8 +212,6 @@ ad_connect sys_reset ddr4_1/sys_rst
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
create_bd_port -dir I dac_fifo_bypass
ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr
ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.QPLL_ENABLE 1
@ -136,7 +272,6 @@ ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.QPLL_ENABLE 0
@ -236,7 +371,7 @@ for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
} }
ad_connect rx_adrv9009_som_tpl_core/adc_dovf util_som_rx_cpack/fifo_wr_overflow ad_connect rx_adrv9009_som_tpl_core/adc_dovf util_som_rx_cpack/fifo_wr_overflow
# connections (adc-os) # connections (adc-obs)
ad_connect core_clk_a obs_adrv9009_som_tpl_core/link_clk ad_connect core_clk_a obs_adrv9009_som_tpl_core/link_clk
ad_connect axi_adrv9009_som_obs_jesd/rx_sof obs_adrv9009_som_tpl_core/link_sof ad_connect axi_adrv9009_som_obs_jesd/rx_sof obs_adrv9009_som_tpl_core/link_sof

6
projects/adrv9009_zu11eg_som/adrv9009_zu11eg_som_constr.xdc → projects/adrv9009zu11eg/common/adrv9009zu11eg_constr.xdc
View File

@ -213,3 +213,9 @@ set_input_delay -clock rx_dev_clk -min 4 [get_ports sysref_b_p];
set_input_delay -clock tx_dev_clk -max 4 [get_ports sysref_a_p]; set_input_delay -clock tx_dev_clk -max 4 [get_ports sysref_a_p];
set_input_delay -clock tx_dev_clk -min 4 [get_ports sysref_a_p]; set_input_delay -clock tx_dev_clk -min 4 [get_ports sysref_a_p];
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18} [get_ports spi_clk]
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18} [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN AR9 IOSTANDARD LVCMOS18} [get_ports spi_miso]
create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO]

2
projects/adrv9009_zu11eg_som/adrv9009_zu11eg_som_spi.v → projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v
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@ -35,7 +35,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module adrv9009_zu11eg_som_spi ( module adrv9009zu11eg_spi (
input [ 7:0] spi_csn, input [ 7:0] spi_csn,
input spi_clk, input spi_clk,