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pzsdr1/common- updates

main
Rejeesh Kutty 2016-11-17 15:31:25 -05:00
parent aa02ca875f
commit a61da1d2ac
2 changed files with 24 additions and 34 deletions
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16
projects/pzsdr1/common/ccbrk_bd.tcl
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@ -4,26 +4,16 @@
ad_connect sys_ps7/ENET1_GMII_RX_CLK GND ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
ad_connect sys_ps7/ENET1_GMII_TX_CLK GND ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
# un-used io # un-used io (regular)
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg set_property -dict [list CONFIG.NUM_OF_CLK_MONS {0}] $axi_gpreg
set_property -dict [list CONFIG.NUM_OF_IO {2}] $axi_gpreg set_property -dict [list CONFIG.NUM_OF_IO {1}] $axi_gpreg
ad_cpu_interconnect 0x41200000 axi_gpreg
create_bd_port -dir I -from 31 -to 0 gp_in_0 create_bd_port -dir I -from 31 -to 0 gp_in_0
create_bd_port -dir I -from 31 -to 0 gp_in_1
create_bd_port -dir O -from 31 -to 0 gp_out_0 create_bd_port -dir O -from 31 -to 0 gp_out_0
create_bd_port -dir O -from 31 -to 0 gp_out_1
ad_connect gp_in_0 axi_gpreg/up_gp_in_0 ad_connect gp_in_0 axi_gpreg/up_gp_in_0
ad_connect gp_in_1 axi_gpreg/up_gp_in_1
ad_connect gp_out_0 axi_gpreg/up_gp_out_0 ad_connect gp_out_0 axi_gpreg/up_gp_out_0
ad_connect gp_out_1 axi_gpreg/up_gp_out_1 ad_cpu_interconnect 0x41200000 axi_gpreg
## temporary (remove ila indirectly)
delete_bd_objs [get_bd_cells ila_adc]
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]

42
projects/pzsdr1/common/ccbrk_constr.xdc
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@ -2,27 +2,27 @@
## constraints (ccbrk.c + ccbrk_lb.a) ## constraints (ccbrk.c + ccbrk_lb.a)
## ad9361 clkout forward ## ad9361 clkout forward
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS18} [get_ports clkout_out] ; ## (lb: none) U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32 set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports clkout_out] ; ## (lb: none) U1,W16,IO_L18_34_JX4_N,JX4,70,IO_L18_34_JX4_N,P7,32
## push-buttons- led- dip-switches- loopbacks- (ps7 gpio) ## push-buttons- led- dip-switches- loopbacks- (ps7 gpio)
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## (lb: none) U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19 set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## (lb: none) U1,Y14,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1,P6,19
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## (lb: none) U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26 set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## (lb: none) U1,T16,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2,P6,26
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## (lb: none) U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28 set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## (lb: none) U1,U17,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3,P6,28
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## (lb: none) U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16 set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## (lb: none) U1,Y19,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0,P7,16
## orphans- io- (ps7 gpio) ## orphans- io- (ps7 gpio)
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## (lb: none) U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## (lb: none) U1,V5,IO_L06_13_JX2_P,JX2,18,IO_L06_13_JX2_P
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (lb: none) U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52 set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## (lb: none) U1,V11,IO_L21_13_JX2_P,JX2,67,IO_L21_13_JX2_P,P2,52
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (lb: none) U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54 set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## (lb: none) U1,V10,IO_L21_13_JX2_N,JX2,69,IO_L21_13_JX2_N,P2,54
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## (lb: none) U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30 set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## (lb: none) U1,V16,IO_L18_34_JX4_P,JX4,68,IO_L18_34_JX4_P,P7,30
## ps7- fixed io- to- fpga regular io (ps7 gpio) ## ps7- fixed io- to- fpga regular io (ps7 gpio)
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23) set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,V15,IO_L10_34_JX4_P,JX4,42,IO_L10_34_JX4_P,P6,25 (U1,E9,PS_MIO10_500_JX4,JX4,87,PS_MIO10_500_JX4,P6,23)
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11) set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,Y18,IO_L17_34_JX4_P,JX4,67,IO_L17_34_JX4_P,P6,9 (U1,B9,PS_MIO51_501_JX4,JX4,100,PS_MIO51_501_JX4,P6,11)
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21) set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,Y17,IO_L07_34_JX4_N,JX4,37,IO_L07_34_JX4_N,P6,20 (U1,C8,PS_MIO15_500_JX4,JX4,85,PS_MIO15_500_JX4,P6,21)
## ps7- fixed io- to- ps7- fixed io (reference only) ## ps7- fixed io- to- ps7- fixed io (reference only)
## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22 ## U1,B14,PS_MIO47_501_JX4,JX4,94,PS_MIO47_501_JX4,P7,24 == U1,D16,PS_MIO46_501_JX4,JX4,92,PS_MIO46_501_JX4,P7,22
@ -80,16 +80,16 @@ set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports gp_o
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,N20,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1 set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports gp_in[20]] ; ## U1,N20,IO_L14_SRCC_34_JX4_P,JX4,52,IO_L14_SRCC_34_JX4_P,P7,1
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4 set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports gp_out[21]] ; ## U1,P19,IO_L13_MRCC_34_JX4_N,JX4,53,IO_L13_MRCC_34_JX4_N,P7,4
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3 set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports gp_in[21]] ; ## U1,P20,IO_L14_SRCC_34_JX4_N,JX4,54,IO_L14_SRCC_34_JX4_N,P7,3
set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS18} [get_ports gp_out[22]] ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6 set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports gp_out[22]] ; ## U1,T20,IO_L15_34_JX4_P,JX4,57,IO_L15_34_JX4_P,P7,6
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS18} [get_ports gp_in[22]] ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5 set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports gp_in[22]] ; ## U1,V20,IO_L16_34_JX4_P,JX4,58,IO_L16_34_JX4_P,P7,5
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports gp_out[23]] ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8 set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports gp_out[23]] ; ## U1,U20,IO_L15_34_JX4_N,JX4,59,IO_L15_34_JX4_N,P7,8
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports gp_in[23]] ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7 set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[23]] ; ## U1,W20,IO_L16_34_JX4_N,JX4,60,IO_L16_34_JX4_N,P7,7
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS18} [get_ports gp_out[24]] ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18 set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gp_out[24]] ; ## U1,R16,IO_L19_34_JX4_P,JX4,73,IO_L19_34_JX4_P,P7,18
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports gp_in[24]] ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17 set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports gp_in[24]] ; ## U1,T17,IO_L20_34_JX4_P,JX4,74,IO_L20_34_JX4_P,P7,17
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS18} [get_ports gp_out[25]] ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20 set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports gp_out[25]] ; ## U1,R17,IO_L19_34_JX4_N,JX4,75,IO_L19_34_JX4_N,P7,20
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gp_in[25]] ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19 set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gp_in[25]] ; ## U1,R18,IO_L20_34_JX4_N,JX4,76,IO_L20_34_JX4_N,P7,19
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports gp_out[26]] ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26 set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports gp_out[26]] ; ## U1,V17,IO_L21_34_JX4_P,JX4,77,IO_L21_34_JX4_P,P7,26
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports gp_in[26]] ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25 set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[26]] ; ## U1,W18,IO_L22_34_JX4_P,JX4,78,IO_L22_34_JX4_P,P7,25
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS18} [get_ports gp_out[27]] ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28 set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_out[27]] ; ## U1,V18,IO_L21_34_JX4_N,JX4,79,IO_L21_34_JX4_N,P7,28
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports gp_in[27]] ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27 set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_in[27]] ; ## U1,W19,IO_L22_34_JX4_N,JX4,80,IO_L22_34_JX4_N,P7,27